tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* Generic NS8390 register definitions. */
2/* This file is part of Donald Becker's 8390 drivers, and is distributed
3 under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
4 Some of these names and comments originated from the Crynwr
5 packet drivers, which are distributed under the GPL. */
6
7#ifndef _8390_h
8#define _8390_h
9
10#include <linux/config.h>
11#include <linux/if_ether.h>
12#include <linux/ioport.h>
13#include <linux/skbuff.h>
14
15#define TX_PAGES 12 /* Two Tx slots */
16
17#define ETHER_ADDR_LEN 6
18
19/* The 8390 specific per-packet-header format. */
20struct e8390_pkt_hdr {
21 unsigned char status; /* status */
22 unsigned char next; /* pointer to next packet. */
23 unsigned short count; /* header + packet length in bytes */
24};
25
26#ifdef notdef
27extern int ei_debug;
28#else
29#define ei_debug 1
30#endif
31
32#ifdef CONFIG_NET_POLL_CONTROLLER
33extern void ei_poll(struct net_device *dev);
34#endif
35
36extern void NS8390_init(struct net_device *dev, int startp);
37extern int ei_open(struct net_device *dev);
38extern int ei_close(struct net_device *dev);
39extern irqreturn_t ei_interrupt(int irq, void *dev_id, struct pt_regs *regs);
40extern struct net_device *__alloc_ei_netdev(int size);
41static inline struct net_device *alloc_ei_netdev(void)
42{
43 return __alloc_ei_netdev(0);
44}
45
46/* You have one of these per-board */
47struct ei_device {
48 const char *name;
49 void (*reset_8390)(struct net_device *);
50 void (*get_8390_hdr)(struct net_device *, struct e8390_pkt_hdr *, int);
51 void (*block_output)(struct net_device *, int, const unsigned char *, int);
52 void (*block_input)(struct net_device *, int, struct sk_buff *, int);
53 unsigned long rmem_start;
54 unsigned long rmem_end;
55 void __iomem *mem;
56 unsigned char mcfilter[8];
57 unsigned open:1;
58 unsigned word16:1; /* We have the 16-bit (vs 8-bit) version of the card. */
59 unsigned bigendian:1; /* 16-bit big endian mode. Do NOT */
60 /* set this on random 8390 clones! */
61 unsigned txing:1; /* Transmit Active */
62 unsigned irqlock:1; /* 8390's intrs disabled when '1'. */
63 unsigned dmaing:1; /* Remote DMA Active */
64 unsigned char tx_start_page, rx_start_page, stop_page;
65 unsigned char current_page; /* Read pointer in buffer */
66 unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */
67 unsigned char txqueue; /* Tx Packet buffer queue length. */
68 short tx1, tx2; /* Packet lengths for ping-pong tx. */
69 short lasttx; /* Alpha version consistency check. */
70 unsigned char reg0; /* Register '0' in a WD8013 */
71 unsigned char reg5; /* Register '5' in a WD8013 */
72 unsigned char saved_irq; /* Original dev->irq value. */
73 struct net_device_stats stat; /* The new statistics table. */
74 u32 *reg_offset; /* Register mapping table */
75 spinlock_t page_lock; /* Page register locks */
76 unsigned long priv; /* Private field to store bus IDs etc. */
77};
78
79/* The maximum number of 8390 interrupt service routines called per IRQ. */
80#define MAX_SERVICE 12
81
82/* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
83#define TX_TIMEOUT (20*HZ/100)
84
85#define ei_status (*(struct ei_device *)netdev_priv(dev))
86
87/* Some generic ethernet register configurations. */
88#define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */
89#define E8390_RX_IRQ_MASK 0x5
90#define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */
91#define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */
92#define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */
93#define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */
94
95/* Register accessed at EN_CMD, the 8390 base addr. */
96#define E8390_STOP 0x01 /* Stop and reset the chip */
97#define E8390_START 0x02 /* Start the chip, clear reset */
98#define E8390_TRANS 0x04 /* Transmit a frame */
99#define E8390_RREAD 0x08 /* Remote read */
100#define E8390_RWRITE 0x10 /* Remote write */
101#define E8390_NODMA 0x20 /* Remote DMA */
102#define E8390_PAGE0 0x00 /* Select page chip registers */
103#define E8390_PAGE1 0x40 /* using the two high-order bits */
104#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
105
106/*
107 * Only generate indirect loads given a machine that needs them.
108 * - removed AMIGA_PCMCIA from this list, handled as ISA io now
109 */
110
111#if defined(CONFIG_MAC) || \
112 defined(CONFIG_ZORRO8390) || defined(CONFIG_ZORRO8390_MODULE) || \
113 defined(CONFIG_HYDRA) || defined(CONFIG_HYDRA_MODULE)
114#define EI_SHIFT(x) (ei_local->reg_offset[x])
115#undef inb
116#undef inb_p
117#undef outb
118#undef outb_p
119
120#define inb(port) in_8(port)
121#define outb(val,port) out_8(port,val)
122#define inb_p(port) in_8(port)
123#define outb_p(val,port) out_8(port,val)
124
125#elif defined(CONFIG_ARM_ETHERH) || defined(CONFIG_ARM_ETHERH_MODULE)
126#define EI_SHIFT(x) (ei_local->reg_offset[x])
127#undef inb
128#undef inb_p
129#undef outb
130#undef outb_p
131
132#define inb(_p) readb(_p)
133#define outb(_v,_p) writeb(_v,_p)
134#define inb_p(_p) inb(_p)
135#define outb_p(_v,_p) outb(_v,_p)
136
137#elif defined(CONFIG_NET_CBUS) || defined(CONFIG_NE_H8300) || defined(CONFIG_NE_H8300_MODULE)
138#define EI_SHIFT(x) (ei_local->reg_offset[x])
139#else
140#define EI_SHIFT(x) (x)
141#endif
142
143#define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */
144/* Page 0 register offsets. */
145#define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */
146#define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */
147#define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */
148#define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */
149#define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */
150#define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */
151#define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */
152#define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */
153#define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */
154#define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */
155#define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */
156#define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */
157#define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */
158#define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */
159#define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */
160#define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */
161#define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */
162#define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */
163#define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */
164#define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */
165#define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */
166#define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */
167#define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */
168#define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */
169#define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */
170#define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */
171
172/* Bits in EN0_ISR - Interrupt status register */
173#define ENISR_RX 0x01 /* Receiver, no error */
174#define ENISR_TX 0x02 /* Transmitter, no error */
175#define ENISR_RX_ERR 0x04 /* Receiver, with error */
176#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
177#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
178#define ENISR_COUNTERS 0x20 /* Counters need emptying */
179#define ENISR_RDC 0x40 /* remote dma complete */
180#define ENISR_RESET 0x80 /* Reset completed */
181#define ENISR_ALL 0x3f /* Interrupts we will enable */
182
183/* Bits in EN0_DCFG - Data config register */
184#define ENDCFG_WTS 0x01 /* word transfer mode selection */
185#define ENDCFG_BOS 0x02 /* byte order selection */
186
187/* Page 1 register offsets. */
188#define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */
189#define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */
190#define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */
191#define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */
192#define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */
193
194/* Bits in received packet status byte and EN0_RSR*/
195#define ENRSR_RXOK 0x01 /* Received a good packet */
196#define ENRSR_CRC 0x02 /* CRC error */
197#define ENRSR_FAE 0x04 /* frame alignment error */
198#define ENRSR_FO 0x08 /* FIFO overrun */
199#define ENRSR_MPA 0x10 /* missed pkt */
200#define ENRSR_PHY 0x20 /* physical/multicast address */
201#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
202#define ENRSR_DEF 0x80 /* deferring */
203
204/* Transmitted packet status, EN0_TSR. */
205#define ENTSR_PTX 0x01 /* Packet transmitted without error */
206#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
207#define ENTSR_COL 0x04 /* The transmit collided at least once. */
208#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
209#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
210#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
211#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
212#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
213
214#endif /* _8390_h */