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Linux kernel mirror (for testing)
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linux
1/*
2 * Switch a MMU context.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 */
11#ifndef _ASM_MMU_CONTEXT_H
12#define _ASM_MMU_CONTEXT_H
13
14#include <linux/errno.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <asm/cacheflush.h>
18#include <asm/tlbflush.h>
19#ifdef CONFIG_MIPS_MT_SMTC
20#include <asm/mipsmtregs.h>
21#include <asm/smtc.h>
22#endif /* SMTC */
23
24/*
25 * For the fast tlb miss handlers, we keep a per cpu array of pointers
26 * to the current pgd for each processor. Also, the proc. id is stuffed
27 * into the context register.
28 */
29extern unsigned long pgd_current[];
30
31#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
32 pgd_current[smp_processor_id()] = (unsigned long)(pgd)
33
34#ifdef CONFIG_32BIT
35#define TLBMISS_HANDLER_SETUP() \
36 write_c0_context((unsigned long) smp_processor_id() << 25); \
37 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
38#endif
39#ifdef CONFIG_64BIT
40#define TLBMISS_HANDLER_SETUP() \
41 write_c0_context((unsigned long) smp_processor_id() << 26); \
42 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
43#endif
44
45#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
46
47#define ASID_INC 0x40
48#define ASID_MASK 0xfc0
49
50#elif defined(CONFIG_CPU_R8000)
51
52#define ASID_INC 0x10
53#define ASID_MASK 0xff0
54
55#elif defined(CONFIG_CPU_RM9000)
56
57#define ASID_INC 0x1
58#define ASID_MASK 0xfff
59
60/* SMTC/34K debug hack - but maybe we'll keep it */
61#elif defined(CONFIG_MIPS_MT_SMTC)
62
63#define ASID_INC 0x1
64extern unsigned long smtc_asid_mask;
65#define ASID_MASK (smtc_asid_mask)
66#define HW_ASID_MASK 0xff
67/* End SMTC/34K debug hack */
68#else /* FIXME: not correct for R6000 */
69
70#define ASID_INC 0x1
71#define ASID_MASK 0xff
72
73#endif
74
75#define cpu_context(cpu, mm) ((mm)->context[cpu])
76#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
77#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
78
79static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
80{
81}
82
83/*
84 * All unused by hardware upper bits will be considered
85 * as a software asid extension.
86 */
87#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
88#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
89
90#ifndef CONFIG_MIPS_MT_SMTC
91/* Normal, classic MIPS get_new_mmu_context */
92static inline void
93get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
94{
95 unsigned long asid = asid_cache(cpu);
96
97 if (! ((asid += ASID_INC) & ASID_MASK) ) {
98 if (cpu_has_vtag_icache)
99 flush_icache_all();
100 local_flush_tlb_all(); /* start new asid cycle */
101 if (!asid) /* fix version if needed */
102 asid = ASID_FIRST_VERSION;
103 }
104 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
105}
106
107#else /* CONFIG_MIPS_MT_SMTC */
108
109#define get_new_mmu_context(mm,cpu) smtc_get_new_mmu_context((mm),(cpu))
110
111#endif /* CONFIG_MIPS_MT_SMTC */
112
113/*
114 * Initialize the context related info for a new mm_struct
115 * instance.
116 */
117static inline int
118init_new_context(struct task_struct *tsk, struct mm_struct *mm)
119{
120 int i;
121
122 for (i = 0; i < num_online_cpus(); i++)
123 cpu_context(i, mm) = 0;
124
125 return 0;
126}
127
128static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
129 struct task_struct *tsk)
130{
131 unsigned int cpu = smp_processor_id();
132 unsigned long flags;
133#ifdef CONFIG_MIPS_MT_SMTC
134 unsigned long oldasid;
135 unsigned long mtflags;
136 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
137 local_irq_save(flags);
138 mtflags = dvpe();
139#else /* Not SMTC */
140 local_irq_save(flags);
141#endif /* CONFIG_MIPS_MT_SMTC */
142
143 /* Check if our ASID is of an older version and thus invalid */
144 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
145 get_new_mmu_context(next, cpu);
146#ifdef CONFIG_MIPS_MT_SMTC
147 /*
148 * If the EntryHi ASID being replaced happens to be
149 * the value flagged at ASID recycling time as having
150 * an extended life, clear the bit showing it being
151 * in use by this "CPU", and if that's the last bit,
152 * free up the ASID value for use and flush any old
153 * instances of it from the TLB.
154 */
155 oldasid = (read_c0_entryhi() & ASID_MASK);
156 if(smtc_live_asid[mytlb][oldasid]) {
157 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
158 if(smtc_live_asid[mytlb][oldasid] == 0)
159 smtc_flush_tlb_asid(oldasid);
160 }
161 /*
162 * Tread softly on EntryHi, and so long as we support
163 * having ASID_MASK smaller than the hardware maximum,
164 * make sure no "soft" bits become "hard"...
165 */
166 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
167 | (cpu_context(cpu, next) & ASID_MASK));
168 ehb(); /* Make sure it propagates to TCStatus */
169 evpe(mtflags);
170#else
171 write_c0_entryhi(cpu_context(cpu, next));
172#endif /* CONFIG_MIPS_MT_SMTC */
173 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
174
175 /*
176 * Mark current->active_mm as not "active" anymore.
177 * We don't want to mislead possible IPI tlb flush routines.
178 */
179 cpu_clear(cpu, prev->cpu_vm_mask);
180 cpu_set(cpu, next->cpu_vm_mask);
181
182 local_irq_restore(flags);
183}
184
185/*
186 * Destroy context related info for an mm_struct that is about
187 * to be put to rest.
188 */
189static inline void destroy_context(struct mm_struct *mm)
190{
191}
192
193#define deactivate_mm(tsk,mm) do { } while (0)
194
195/*
196 * After we have set current->mm to a new value, this activates
197 * the context for the new mm so we see the new mappings.
198 */
199static inline void
200activate_mm(struct mm_struct *prev, struct mm_struct *next)
201{
202 unsigned long flags;
203 unsigned int cpu = smp_processor_id();
204
205#ifdef CONFIG_MIPS_MT_SMTC
206 unsigned long oldasid;
207 unsigned long mtflags;
208 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
209#endif /* CONFIG_MIPS_MT_SMTC */
210
211 local_irq_save(flags);
212
213 /* Unconditionally get a new ASID. */
214 get_new_mmu_context(next, cpu);
215
216#ifdef CONFIG_MIPS_MT_SMTC
217 /* See comments for similar code above */
218 mtflags = dvpe();
219 oldasid = read_c0_entryhi() & ASID_MASK;
220 if(smtc_live_asid[mytlb][oldasid]) {
221 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
222 if(smtc_live_asid[mytlb][oldasid] == 0)
223 smtc_flush_tlb_asid(oldasid);
224 }
225 /* See comments for similar code above */
226 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
227 (cpu_context(cpu, next) & ASID_MASK));
228 ehb(); /* Make sure it propagates to TCStatus */
229 evpe(mtflags);
230#else
231 write_c0_entryhi(cpu_context(cpu, next));
232#endif /* CONFIG_MIPS_MT_SMTC */
233 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
234
235 /* mark mmu ownership change */
236 cpu_clear(cpu, prev->cpu_vm_mask);
237 cpu_set(cpu, next->cpu_vm_mask);
238
239 local_irq_restore(flags);
240}
241
242/*
243 * If mm is currently active_mm, we can't really drop it. Instead,
244 * we will get a new one for it.
245 */
246static inline void
247drop_mmu_context(struct mm_struct *mm, unsigned cpu)
248{
249 unsigned long flags;
250#ifdef CONFIG_MIPS_MT_SMTC
251 unsigned long oldasid;
252 /* Can't use spinlock because called from TLB flush within DVPE */
253 unsigned int prevvpe;
254 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
255#endif /* CONFIG_MIPS_MT_SMTC */
256
257 local_irq_save(flags);
258
259 if (cpu_isset(cpu, mm->cpu_vm_mask)) {
260 get_new_mmu_context(mm, cpu);
261#ifdef CONFIG_MIPS_MT_SMTC
262 /* See comments for similar code above */
263 prevvpe = dvpe();
264 oldasid = (read_c0_entryhi() & ASID_MASK);
265 if (smtc_live_asid[mytlb][oldasid]) {
266 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
267 if(smtc_live_asid[mytlb][oldasid] == 0)
268 smtc_flush_tlb_asid(oldasid);
269 }
270 /* See comments for similar code above */
271 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
272 | cpu_asid(cpu, mm));
273 ehb(); /* Make sure it propagates to TCStatus */
274 evpe(prevvpe);
275#else /* not CONFIG_MIPS_MT_SMTC */
276 write_c0_entryhi(cpu_asid(cpu, mm));
277#endif /* CONFIG_MIPS_MT_SMTC */
278 } else {
279 /* will get a new context next time */
280#ifndef CONFIG_MIPS_MT_SMTC
281 cpu_context(cpu, mm) = 0;
282#else /* SMTC */
283 int i;
284
285 /* SMTC shares the TLB (and ASIDs) across VPEs */
286 for (i = 0; i < num_online_cpus(); i++) {
287 if((smtc_status & SMTC_TLB_SHARED)
288 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
289 cpu_context(i, mm) = 0;
290 }
291#endif /* CONFIG_MIPS_MT_SMTC */
292 }
293 local_irq_restore(flags);
294}
295
296#endif /* _ASM_MMU_CONTEXT_H */