1#ifndef MFD_TMIO_H 2#define MFD_TMIO_H 3 4#include <linux/fb.h> 5#include <linux/io.h> 6#include <linux/platform_device.h> 7 8#define tmio_ioread8(addr) readb(addr) 9#define tmio_ioread16(addr) readw(addr) 10#define tmio_ioread16_rep(r, b, l) readsw(r, b, l) 11#define tmio_ioread32(addr) \ 12 (((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16)) 13 14#define tmio_iowrite8(val, addr) writeb((val), (addr)) 15#define tmio_iowrite16(val, addr) writew((val), (addr)) 16#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l) 17#define tmio_iowrite32(val, addr) \ 18 do { \ 19 writew((val), (addr)); \ 20 writew((val) >> 16, (addr) + 2); \ 21 } while (0) 22 23#define CNF_CMD 0x04 24#define CNF_CTL_BASE 0x10 25#define CNF_INT_PIN 0x3d 26#define CNF_STOP_CLK_CTL 0x40 27#define CNF_GCLK_CTL 0x41 28#define CNF_SD_CLK_MODE 0x42 29#define CNF_PIN_STATUS 0x44 30#define CNF_PWR_CTL_1 0x48 31#define CNF_PWR_CTL_2 0x49 32#define CNF_PWR_CTL_3 0x4a 33#define CNF_CARD_DETECT_MODE 0x4c 34#define CNF_SD_SLOT 0x50 35#define CNF_EXT_GCLK_CTL_1 0xf0 36#define CNF_EXT_GCLK_CTL_2 0xf1 37#define CNF_EXT_GCLK_CTL_3 0xf9 38#define CNF_SD_LED_EN_1 0xfa 39#define CNF_SD_LED_EN_2 0xfe 40 41#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/ 42 43#define sd_config_write8(base, shift, reg, val) \ 44 tmio_iowrite8((val), (base) + ((reg) << (shift))) 45#define sd_config_write16(base, shift, reg, val) \ 46 tmio_iowrite16((val), (base) + ((reg) << (shift))) 47#define sd_config_write32(base, shift, reg, val) \ 48 do { \ 49 tmio_iowrite16((val), (base) + ((reg) << (shift))); \ 50 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \ 51 } while (0) 52 53/* tmio MMC platform flags */ 54#define TMIO_MMC_WRPROTECT_DISABLE (1 << 0) 55/* 56 * Some controllers can support a 2-byte block size when the bus width 57 * is configured in 4-bit mode. 58 */ 59#define TMIO_MMC_BLKSZ_2BYTES (1 << 1) 60/* 61 * Some controllers can support SDIO IRQ signalling. 62 */ 63#define TMIO_MMC_SDIO_IRQ (1 << 2) 64 65int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); 66int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); 67void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); 68void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state); 69 70struct tmio_mmc_dma { 71 void *chan_priv_tx; 72 void *chan_priv_rx; 73 int alignment_shift; 74}; 75 76/* 77 * data for the MMC controller 78 */ 79struct tmio_mmc_data { 80 unsigned int hclk; 81 unsigned long capabilities; 82 unsigned long flags; 83 u32 ocr_mask; /* available voltages */ 84 struct tmio_mmc_dma *dma; 85 void (*set_pwr)(struct platform_device *host, int state); 86 void (*set_clk_div)(struct platform_device *host, int state); 87 int (*get_cd)(struct platform_device *host); 88}; 89 90/* 91 * data for the NAND controller 92 */ 93struct tmio_nand_data { 94 struct nand_bbt_descr *badblock_pattern; 95 struct mtd_partition *partition; 96 unsigned int num_partitions; 97}; 98 99#define FBIO_TMIO_ACC_WRITE 0x7C639300 100#define FBIO_TMIO_ACC_SYNC 0x7C639301 101 102struct tmio_fb_data { 103 int (*lcd_set_power)(struct platform_device *fb_dev, 104 bool on); 105 int (*lcd_mode)(struct platform_device *fb_dev, 106 const struct fb_videomode *mode); 107 int num_modes; 108 struct fb_videomode *modes; 109 110 /* in mm: size of screen */ 111 int height; 112 int width; 113}; 114 115 116#endif