tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1#ifndef __SH_CLOCK_H
2#define __SH_CLOCK_H
3
4#include <linux/list.h>
5#include <linux/seq_file.h>
6#include <linux/cpufreq.h>
7#include <linux/types.h>
8#include <linux/kref.h>
9#include <linux/clk.h>
10#include <linux/err.h>
11
12struct clk;
13
14struct clk_mapping {
15 phys_addr_t phys;
16 void __iomem *base;
17 unsigned long len;
18 struct kref ref;
19};
20
21struct clk_ops {
22 void (*init)(struct clk *clk);
23 int (*enable)(struct clk *clk);
24 void (*disable)(struct clk *clk);
25 unsigned long (*recalc)(struct clk *clk);
26 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
27 int (*set_parent)(struct clk *clk, struct clk *parent);
28 long (*round_rate)(struct clk *clk, unsigned long rate);
29};
30
31struct clk {
32 struct list_head node;
33 struct clk *parent;
34 struct clk **parent_table; /* list of parents to */
35 unsigned short parent_num; /* choose between */
36 unsigned char src_shift; /* source clock field in the */
37 unsigned char src_width; /* configuration register */
38 struct clk_ops *ops;
39
40 struct list_head children;
41 struct list_head sibling; /* node for children */
42
43 int usecount;
44
45 unsigned long rate;
46 unsigned long flags;
47
48 void __iomem *enable_reg;
49 unsigned int enable_bit;
50
51 unsigned long arch_flags;
52 void *priv;
53 struct dentry *dentry;
54 struct clk_mapping *mapping;
55 struct cpufreq_frequency_table *freq_table;
56 unsigned int nr_freqs;
57};
58
59#define CLK_ENABLE_ON_INIT (1 << 0)
60
61/* drivers/sh/clk.c */
62unsigned long followparent_recalc(struct clk *);
63void recalculate_root_clocks(void);
64void propagate_rate(struct clk *);
65int clk_reparent(struct clk *child, struct clk *parent);
66int clk_register(struct clk *);
67void clk_unregister(struct clk *);
68void clk_enable_init_clocks(void);
69
70/**
71 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
72 * @clk: clock source
73 * @rate: desired clock rate in Hz
74 * @algo_id: algorithm id to be passed down to ops->set_rate
75 *
76 * Returns success (0) or negative errno.
77 */
78int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
79
80enum clk_sh_algo_id {
81 NO_CHANGE = 0,
82
83 IUS_N1_N1,
84 IUS_322,
85 IUS_522,
86 IUS_N11,
87
88 SB_N1,
89
90 SB3_N1,
91 SB3_32,
92 SB3_43,
93 SB3_54,
94
95 BP_N1,
96
97 IP_N1,
98};
99
100struct clk_div_mult_table {
101 unsigned int *divisors;
102 unsigned int nr_divisors;
103 unsigned int *multipliers;
104 unsigned int nr_multipliers;
105};
106
107struct cpufreq_frequency_table;
108void clk_rate_table_build(struct clk *clk,
109 struct cpufreq_frequency_table *freq_table,
110 int nr_freqs,
111 struct clk_div_mult_table *src_table,
112 unsigned long *bitmap);
113
114long clk_rate_table_round(struct clk *clk,
115 struct cpufreq_frequency_table *freq_table,
116 unsigned long rate);
117
118int clk_rate_table_find(struct clk *clk,
119 struct cpufreq_frequency_table *freq_table,
120 unsigned long rate);
121
122long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
123 unsigned int div_max, unsigned long rate);
124
125long clk_round_parent(struct clk *clk, unsigned long target,
126 unsigned long *best_freq, unsigned long *parent_freq,
127 unsigned int div_min, unsigned int div_max);
128
129#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
130{ \
131 .parent = _parent, \
132 .enable_reg = (void __iomem *)_enable_reg, \
133 .enable_bit = _enable_bit, \
134 .flags = _flags, \
135}
136
137int sh_clk_mstp32_register(struct clk *clks, int nr);
138
139#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
140{ \
141 .parent = _parent, \
142 .enable_reg = (void __iomem *)_reg, \
143 .enable_bit = _shift, \
144 .arch_flags = _div_bitmap, \
145 .flags = _flags, \
146}
147
148struct clk_div4_table {
149 struct clk_div_mult_table *div_mult_table;
150 void (*kick)(struct clk *clk);
151};
152
153int sh_clk_div4_register(struct clk *clks, int nr,
154 struct clk_div4_table *table);
155int sh_clk_div4_enable_register(struct clk *clks, int nr,
156 struct clk_div4_table *table);
157int sh_clk_div4_reparent_register(struct clk *clks, int nr,
158 struct clk_div4_table *table);
159
160#define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents, \
161 _num_parents, _src_shift, _src_width) \
162{ \
163 .parent = _parent, \
164 .enable_reg = (void __iomem *)_reg, \
165 .flags = _flags, \
166 .parent_table = _parents, \
167 .parent_num = _num_parents, \
168 .src_shift = _src_shift, \
169 .src_width = _src_width, \
170}
171
172#define SH_CLK_DIV6(_parent, _reg, _flags) \
173 SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0)
174
175int sh_clk_div6_register(struct clk *clks, int nr);
176int sh_clk_div6_reparent_register(struct clk *clks, int nr);
177
178#endif /* __SH_CLOCK_H */