tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
5 * Copyright (c) 2024, David Wronek <david@mainlining.org>
6 */
7
8#ifndef _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H
9#define _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H
10
11/* DISPCC clock registers */
12#define DISPCC_PLL0 0
13#define DISPCC_MDSS_AHB_CLK 1
14#define DISPCC_MDSS_AHB_CLK_SRC 2
15#define DISPCC_MDSS_BYTE0_CLK 3
16#define DISPCC_MDSS_BYTE0_CLK_SRC 4
17#define DISPCC_MDSS_BYTE0_DIV_CLK_SRC 5
18#define DISPCC_MDSS_BYTE0_INTF_CLK 6
19#define DISPCC_MDSS_BYTE1_CLK 7
20#define DISPCC_MDSS_BYTE1_CLK_SRC 8
21#define DISPCC_MDSS_BYTE1_DIV_CLK_SRC 9
22#define DISPCC_MDSS_BYTE1_INTF_CLK 10
23#define DISPCC_MDSS_DP_AUX_CLK 11
24#define DISPCC_MDSS_DP_AUX_CLK_SRC 12
25#define DISPCC_MDSS_DP_CRYPTO_CLK 13
26#define DISPCC_MDSS_DP_CRYPTO_CLK_SRC 14
27#define DISPCC_MDSS_DP_LINK_CLK 15
28#define DISPCC_MDSS_DP_LINK_CLK_SRC 16
29#define DISPCC_MDSS_DP_LINK_INTF_CLK 17
30#define DISPCC_MDSS_DP_PIXEL1_CLK 18
31#define DISPCC_MDSS_DP_PIXEL1_CLK_SRC 19
32#define DISPCC_MDSS_DP_PIXEL_CLK 20
33#define DISPCC_MDSS_DP_PIXEL_CLK_SRC 21
34#define DISPCC_MDSS_ESC0_CLK 22
35#define DISPCC_MDSS_ESC0_CLK_SRC 23
36#define DISPCC_MDSS_ESC1_CLK 24
37#define DISPCC_MDSS_ESC1_CLK_SRC 25
38#define DISPCC_MDSS_MDP_CLK 26
39#define DISPCC_MDSS_MDP_CLK_SRC 27
40#define DISPCC_MDSS_MDP_LUT_CLK 28
41#define DISPCC_MDSS_NON_GDSC_AHB_CLK 29
42#define DISPCC_MDSS_PCLK0_CLK 30
43#define DISPCC_MDSS_PCLK0_CLK_SRC 31
44#define DISPCC_MDSS_PCLK1_CLK 32
45#define DISPCC_MDSS_PCLK1_CLK_SRC 33
46#define DISPCC_MDSS_ROT_CLK 34
47#define DISPCC_MDSS_ROT_CLK_SRC 35
48#define DISPCC_MDSS_RSCC_AHB_CLK 36
49#define DISPCC_MDSS_RSCC_VSYNC_CLK 37
50#define DISPCC_MDSS_VSYNC_CLK 38
51#define DISPCC_MDSS_VSYNC_CLK_SRC 39
52#define DISPCC_XO_CLK_SRC 40
53#define DISPCC_SLEEP_CLK 41
54#define DISPCC_SLEEP_CLK_SRC 42
55
56/* DISPCC GDSCR */
57#define MDSS_GDSC 0
58
59#endif