tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * M66592 UDC (USB gadget)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29#include <linux/err.h>
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
33#include "m66592-udc.h"
34
35MODULE_DESCRIPTION("M66592 USB gadget driver");
36MODULE_LICENSE("GPL");
37MODULE_AUTHOR("Yoshihiro Shimoda");
38MODULE_ALIAS("platform:m66592_udc");
39
40#define DRIVER_VERSION "21 July 2009"
41
42static const char udc_name[] = "m66592_udc";
43static const char *m66592_ep_name[] = {
44 "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
45};
46
47static void disable_controller(struct m66592 *m66592);
48static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
49static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
50static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
51 gfp_t gfp_flags);
52
53static void transfer_complete(struct m66592_ep *ep,
54 struct m66592_request *req, int status);
55
56/*-------------------------------------------------------------------------*/
57static inline u16 get_usb_speed(struct m66592 *m66592)
58{
59 return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
60}
61
62static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
63 unsigned long reg)
64{
65 u16 tmp;
66
67 tmp = m66592_read(m66592, M66592_INTENB0);
68 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
69 M66592_INTENB0);
70 m66592_bset(m66592, (1 << pipenum), reg);
71 m66592_write(m66592, tmp, M66592_INTENB0);
72}
73
74static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
75 unsigned long reg)
76{
77 u16 tmp;
78
79 tmp = m66592_read(m66592, M66592_INTENB0);
80 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
81 M66592_INTENB0);
82 m66592_bclr(m66592, (1 << pipenum), reg);
83 m66592_write(m66592, tmp, M66592_INTENB0);
84}
85
86static void m66592_usb_connect(struct m66592 *m66592)
87{
88 m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
89 m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
90 M66592_INTENB0);
91 m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
92
93 m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
94}
95
96static void m66592_usb_disconnect(struct m66592 *m66592)
97__releases(m66592->lock)
98__acquires(m66592->lock)
99{
100 m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
101 m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
102 M66592_INTENB0);
103 m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
104 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
105
106 m66592->gadget.speed = USB_SPEED_UNKNOWN;
107 spin_unlock(&m66592->lock);
108 m66592->driver->disconnect(&m66592->gadget);
109 spin_lock(&m66592->lock);
110
111 disable_controller(m66592);
112 INIT_LIST_HEAD(&m66592->ep[0].queue);
113}
114
115static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
116{
117 u16 pid = 0;
118 unsigned long offset;
119
120 if (pipenum == 0)
121 pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
122 else if (pipenum < M66592_MAX_NUM_PIPE) {
123 offset = get_pipectr_addr(pipenum);
124 pid = m66592_read(m66592, offset) & M66592_PID;
125 } else
126 pr_err("unexpect pipe num (%d)\n", pipenum);
127
128 return pid;
129}
130
131static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
132 u16 pid)
133{
134 unsigned long offset;
135
136 if (pipenum == 0)
137 m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
138 else if (pipenum < M66592_MAX_NUM_PIPE) {
139 offset = get_pipectr_addr(pipenum);
140 m66592_mdfy(m66592, pid, M66592_PID, offset);
141 } else
142 pr_err("unexpect pipe num (%d)\n", pipenum);
143}
144
145static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
146{
147 control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
148}
149
150static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
151{
152 control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
153}
154
155static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
156{
157 control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
158}
159
160static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
161{
162 u16 ret = 0;
163 unsigned long offset;
164
165 if (pipenum == 0)
166 ret = m66592_read(m66592, M66592_DCPCTR);
167 else if (pipenum < M66592_MAX_NUM_PIPE) {
168 offset = get_pipectr_addr(pipenum);
169 ret = m66592_read(m66592, offset);
170 } else
171 pr_err("unexpect pipe num (%d)\n", pipenum);
172
173 return ret;
174}
175
176static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
177{
178 unsigned long offset;
179
180 pipe_stop(m66592, pipenum);
181
182 if (pipenum == 0)
183 m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
184 else if (pipenum < M66592_MAX_NUM_PIPE) {
185 offset = get_pipectr_addr(pipenum);
186 m66592_bset(m66592, M66592_SQCLR, offset);
187 } else
188 pr_err("unexpect pipe num(%d)\n", pipenum);
189}
190
191static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
192{
193 u16 tmp;
194 int size;
195
196 if (pipenum == 0) {
197 tmp = m66592_read(m66592, M66592_DCPCFG);
198 if ((tmp & M66592_CNTMD) != 0)
199 size = 256;
200 else {
201 tmp = m66592_read(m66592, M66592_DCPMAXP);
202 size = tmp & M66592_MAXP;
203 }
204 } else {
205 m66592_write(m66592, pipenum, M66592_PIPESEL);
206 tmp = m66592_read(m66592, M66592_PIPECFG);
207 if ((tmp & M66592_CNTMD) != 0) {
208 tmp = m66592_read(m66592, M66592_PIPEBUF);
209 size = ((tmp >> 10) + 1) * 64;
210 } else {
211 tmp = m66592_read(m66592, M66592_PIPEMAXP);
212 size = tmp & M66592_MXPS;
213 }
214 }
215
216 return size;
217}
218
219static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
220{
221 struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
222 unsigned short mbw;
223
224 if (ep->use_dma)
225 return;
226
227 m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
228
229 ndelay(450);
230
231 if (m66592->pdata->on_chip)
232 mbw = M66592_MBW_32;
233 else
234 mbw = M66592_MBW_16;
235
236 m66592_bset(m66592, mbw, ep->fifosel);
237}
238
239static int pipe_buffer_setting(struct m66592 *m66592,
240 struct m66592_pipe_info *info)
241{
242 u16 bufnum = 0, buf_bsize = 0;
243 u16 pipecfg = 0;
244
245 if (info->pipe == 0)
246 return -EINVAL;
247
248 m66592_write(m66592, info->pipe, M66592_PIPESEL);
249
250 if (info->dir_in)
251 pipecfg |= M66592_DIR;
252 pipecfg |= info->type;
253 pipecfg |= info->epnum;
254 switch (info->type) {
255 case M66592_INT:
256 bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
257 buf_bsize = 0;
258 break;
259 case M66592_BULK:
260 /* isochronous pipes may be used as bulk pipes */
261 if (info->pipe > M66592_BASE_PIPENUM_BULK)
262 bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
263 else
264 bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
265
266 bufnum = M66592_BASE_BUFNUM + (bufnum * 16);
267 buf_bsize = 7;
268 pipecfg |= M66592_DBLB;
269 if (!info->dir_in)
270 pipecfg |= M66592_SHTNAK;
271 break;
272 case M66592_ISO:
273 bufnum = M66592_BASE_BUFNUM +
274 (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
275 buf_bsize = 7;
276 break;
277 }
278
279 if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) {
280 pr_err("m66592 pipe memory is insufficient\n");
281 return -ENOMEM;
282 }
283
284 m66592_write(m66592, pipecfg, M66592_PIPECFG);
285 m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
286 m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
287 if (info->interval)
288 info->interval--;
289 m66592_write(m66592, info->interval, M66592_PIPEPERI);
290
291 return 0;
292}
293
294static void pipe_buffer_release(struct m66592 *m66592,
295 struct m66592_pipe_info *info)
296{
297 if (info->pipe == 0)
298 return;
299
300 if (is_bulk_pipe(info->pipe)) {
301 m66592->bulk--;
302 } else if (is_interrupt_pipe(info->pipe))
303 m66592->interrupt--;
304 else if (is_isoc_pipe(info->pipe)) {
305 m66592->isochronous--;
306 if (info->type == M66592_BULK)
307 m66592->bulk--;
308 } else
309 pr_err("ep_release: unexpect pipenum (%d)\n",
310 info->pipe);
311}
312
313static void pipe_initialize(struct m66592_ep *ep)
314{
315 struct m66592 *m66592 = ep->m66592;
316 unsigned short mbw;
317
318 m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
319
320 m66592_write(m66592, M66592_ACLRM, ep->pipectr);
321 m66592_write(m66592, 0, ep->pipectr);
322 m66592_write(m66592, M66592_SQCLR, ep->pipectr);
323 if (ep->use_dma) {
324 m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
325
326 ndelay(450);
327
328 if (m66592->pdata->on_chip)
329 mbw = M66592_MBW_32;
330 else
331 mbw = M66592_MBW_16;
332
333 m66592_bset(m66592, mbw, ep->fifosel);
334 }
335}
336
337static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
338 const struct usb_endpoint_descriptor *desc,
339 u16 pipenum, int dma)
340{
341 if ((pipenum != 0) && dma) {
342 if (m66592->num_dma == 0) {
343 m66592->num_dma++;
344 ep->use_dma = 1;
345 ep->fifoaddr = M66592_D0FIFO;
346 ep->fifosel = M66592_D0FIFOSEL;
347 ep->fifoctr = M66592_D0FIFOCTR;
348 ep->fifotrn = M66592_D0FIFOTRN;
349 } else if (!m66592->pdata->on_chip && m66592->num_dma == 1) {
350 m66592->num_dma++;
351 ep->use_dma = 1;
352 ep->fifoaddr = M66592_D1FIFO;
353 ep->fifosel = M66592_D1FIFOSEL;
354 ep->fifoctr = M66592_D1FIFOCTR;
355 ep->fifotrn = M66592_D1FIFOTRN;
356 } else {
357 ep->use_dma = 0;
358 ep->fifoaddr = M66592_CFIFO;
359 ep->fifosel = M66592_CFIFOSEL;
360 ep->fifoctr = M66592_CFIFOCTR;
361 ep->fifotrn = 0;
362 }
363 } else {
364 ep->use_dma = 0;
365 ep->fifoaddr = M66592_CFIFO;
366 ep->fifosel = M66592_CFIFOSEL;
367 ep->fifoctr = M66592_CFIFOCTR;
368 ep->fifotrn = 0;
369 }
370
371 ep->pipectr = get_pipectr_addr(pipenum);
372 ep->pipenum = pipenum;
373 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
374 m66592->pipenum2ep[pipenum] = ep;
375 m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
376 INIT_LIST_HEAD(&ep->queue);
377}
378
379static void m66592_ep_release(struct m66592_ep *ep)
380{
381 struct m66592 *m66592 = ep->m66592;
382 u16 pipenum = ep->pipenum;
383
384 if (pipenum == 0)
385 return;
386
387 if (ep->use_dma)
388 m66592->num_dma--;
389 ep->pipenum = 0;
390 ep->busy = 0;
391 ep->use_dma = 0;
392}
393
394static int alloc_pipe_config(struct m66592_ep *ep,
395 const struct usb_endpoint_descriptor *desc)
396{
397 struct m66592 *m66592 = ep->m66592;
398 struct m66592_pipe_info info;
399 int dma = 0;
400 int *counter;
401 int ret;
402
403 ep->desc = desc;
404
405 BUG_ON(ep->pipenum);
406
407 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
408 case USB_ENDPOINT_XFER_BULK:
409 if (m66592->bulk >= M66592_MAX_NUM_BULK) {
410 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
411 pr_err("bulk pipe is insufficient\n");
412 return -ENODEV;
413 } else {
414 info.pipe = M66592_BASE_PIPENUM_ISOC
415 + m66592->isochronous;
416 counter = &m66592->isochronous;
417 }
418 } else {
419 info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
420 counter = &m66592->bulk;
421 }
422 info.type = M66592_BULK;
423 dma = 1;
424 break;
425 case USB_ENDPOINT_XFER_INT:
426 if (m66592->interrupt >= M66592_MAX_NUM_INT) {
427 pr_err("interrupt pipe is insufficient\n");
428 return -ENODEV;
429 }
430 info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
431 info.type = M66592_INT;
432 counter = &m66592->interrupt;
433 break;
434 case USB_ENDPOINT_XFER_ISOC:
435 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
436 pr_err("isochronous pipe is insufficient\n");
437 return -ENODEV;
438 }
439 info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
440 info.type = M66592_ISO;
441 counter = &m66592->isochronous;
442 break;
443 default:
444 pr_err("unexpect xfer type\n");
445 return -EINVAL;
446 }
447 ep->type = info.type;
448
449 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
450 info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
451 info.interval = desc->bInterval;
452 if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
453 info.dir_in = 1;
454 else
455 info.dir_in = 0;
456
457 ret = pipe_buffer_setting(m66592, &info);
458 if (ret < 0) {
459 pr_err("pipe_buffer_setting fail\n");
460 return ret;
461 }
462
463 (*counter)++;
464 if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
465 m66592->bulk++;
466
467 m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
468 pipe_initialize(ep);
469
470 return 0;
471}
472
473static int free_pipe_config(struct m66592_ep *ep)
474{
475 struct m66592 *m66592 = ep->m66592;
476 struct m66592_pipe_info info;
477
478 info.pipe = ep->pipenum;
479 info.type = ep->type;
480 pipe_buffer_release(m66592, &info);
481 m66592_ep_release(ep);
482
483 return 0;
484}
485
486/*-------------------------------------------------------------------------*/
487static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
488{
489 enable_irq_ready(m66592, pipenum);
490 enable_irq_nrdy(m66592, pipenum);
491}
492
493static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
494{
495 disable_irq_ready(m66592, pipenum);
496 disable_irq_nrdy(m66592, pipenum);
497}
498
499/* if complete is true, gadget driver complete function is not call */
500static void control_end(struct m66592 *m66592, unsigned ccpl)
501{
502 m66592->ep[0].internal_ccpl = ccpl;
503 pipe_start(m66592, 0);
504 m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
505}
506
507static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
508{
509 struct m66592 *m66592 = ep->m66592;
510
511 pipe_change(m66592, ep->pipenum);
512 m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
513 (M66592_ISEL | M66592_CURPIPE),
514 M66592_CFIFOSEL);
515 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
516 if (req->req.length == 0) {
517 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
518 pipe_start(m66592, 0);
519 transfer_complete(ep, req, 0);
520 } else {
521 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
522 irq_ep0_write(ep, req);
523 }
524}
525
526static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
527{
528 struct m66592 *m66592 = ep->m66592;
529 u16 tmp;
530
531 pipe_change(m66592, ep->pipenum);
532 disable_irq_empty(m66592, ep->pipenum);
533 pipe_start(m66592, ep->pipenum);
534
535 tmp = m66592_read(m66592, ep->fifoctr);
536 if (unlikely((tmp & M66592_FRDY) == 0))
537 pipe_irq_enable(m66592, ep->pipenum);
538 else
539 irq_packet_write(ep, req);
540}
541
542static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
543{
544 struct m66592 *m66592 = ep->m66592;
545 u16 pipenum = ep->pipenum;
546
547 if (ep->pipenum == 0) {
548 m66592_mdfy(m66592, M66592_PIPE0,
549 (M66592_ISEL | M66592_CURPIPE),
550 M66592_CFIFOSEL);
551 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
552 pipe_start(m66592, pipenum);
553 pipe_irq_enable(m66592, pipenum);
554 } else {
555 if (ep->use_dma) {
556 m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
557 pipe_change(m66592, pipenum);
558 m66592_bset(m66592, M66592_TRENB, ep->fifosel);
559 m66592_write(m66592,
560 (req->req.length + ep->ep.maxpacket - 1)
561 / ep->ep.maxpacket,
562 ep->fifotrn);
563 }
564 pipe_start(m66592, pipenum); /* trigger once */
565 pipe_irq_enable(m66592, pipenum);
566 }
567}
568
569static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
570{
571 if (ep->desc->bEndpointAddress & USB_DIR_IN)
572 start_packet_write(ep, req);
573 else
574 start_packet_read(ep, req);
575}
576
577static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
578{
579 u16 ctsq;
580
581 ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
582
583 switch (ctsq) {
584 case M66592_CS_RDDS:
585 start_ep0_write(ep, req);
586 break;
587 case M66592_CS_WRDS:
588 start_packet_read(ep, req);
589 break;
590
591 case M66592_CS_WRND:
592 control_end(ep->m66592, 0);
593 break;
594 default:
595 pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
596 break;
597 }
598}
599
600static void init_controller(struct m66592 *m66592)
601{
602 unsigned int endian;
603
604 if (m66592->pdata->on_chip) {
605 if (m66592->pdata->endian)
606 endian = 0; /* big endian */
607 else
608 endian = M66592_LITTLE; /* little endian */
609
610 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
611 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
612 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
613 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
614
615 /* This is a workaound for SH7722 2nd cut */
616 m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
617 m66592_bset(m66592, 0x1000, M66592_TESTMODE);
618 m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
619
620 m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
621
622 m66592_write(m66592, 0, M66592_CFBCFG);
623 m66592_write(m66592, 0, M66592_D0FBCFG);
624 m66592_bset(m66592, endian, M66592_CFBCFG);
625 m66592_bset(m66592, endian, M66592_D0FBCFG);
626 } else {
627 unsigned int clock, vif, irq_sense;
628
629 if (m66592->pdata->endian)
630 endian = M66592_BIGEND; /* big endian */
631 else
632 endian = 0; /* little endian */
633
634 if (m66592->pdata->vif)
635 vif = M66592_LDRV; /* 3.3v */
636 else
637 vif = 0; /* 1.5v */
638
639 switch (m66592->pdata->xtal) {
640 case M66592_PLATDATA_XTAL_12MHZ:
641 clock = M66592_XTAL12;
642 break;
643 case M66592_PLATDATA_XTAL_24MHZ:
644 clock = M66592_XTAL24;
645 break;
646 case M66592_PLATDATA_XTAL_48MHZ:
647 clock = M66592_XTAL48;
648 break;
649 default:
650 pr_warning("m66592-udc: xtal configuration error\n");
651 clock = 0;
652 }
653
654 switch (m66592->irq_trigger) {
655 case IRQF_TRIGGER_LOW:
656 irq_sense = M66592_INTL;
657 break;
658 case IRQF_TRIGGER_FALLING:
659 irq_sense = 0;
660 break;
661 default:
662 pr_warning("m66592-udc: irq trigger config error\n");
663 irq_sense = 0;
664 }
665
666 m66592_bset(m66592,
667 (vif & M66592_LDRV) | (endian & M66592_BIGEND),
668 M66592_PINCFG);
669 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
670 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL,
671 M66592_SYSCFG);
672 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
673 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
674 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
675
676 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
677
678 msleep(3);
679
680 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
681
682 msleep(1);
683
684 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
685
686 m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
687 m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
688 M66592_DMA0CFG);
689 }
690}
691
692static void disable_controller(struct m66592 *m66592)
693{
694 if (!m66592->pdata->on_chip) {
695 m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
696 udelay(1);
697 m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
698 udelay(1);
699 m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
700 udelay(1);
701 m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
702 }
703}
704
705static void m66592_start_xclock(struct m66592 *m66592)
706{
707 u16 tmp;
708
709 if (!m66592->pdata->on_chip) {
710 tmp = m66592_read(m66592, M66592_SYSCFG);
711 if (!(tmp & M66592_XCKE))
712 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
713 }
714}
715
716/*-------------------------------------------------------------------------*/
717static void transfer_complete(struct m66592_ep *ep,
718 struct m66592_request *req, int status)
719__releases(m66592->lock)
720__acquires(m66592->lock)
721{
722 int restart = 0;
723
724 if (unlikely(ep->pipenum == 0)) {
725 if (ep->internal_ccpl) {
726 ep->internal_ccpl = 0;
727 return;
728 }
729 }
730
731 list_del_init(&req->queue);
732 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
733 req->req.status = -ESHUTDOWN;
734 else
735 req->req.status = status;
736
737 if (!list_empty(&ep->queue))
738 restart = 1;
739
740 spin_unlock(&ep->m66592->lock);
741 req->req.complete(&ep->ep, &req->req);
742 spin_lock(&ep->m66592->lock);
743
744 if (restart) {
745 req = list_entry(ep->queue.next, struct m66592_request, queue);
746 if (ep->desc)
747 start_packet(ep, req);
748 }
749}
750
751static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
752{
753 int i;
754 u16 tmp;
755 unsigned bufsize;
756 size_t size;
757 void *buf;
758 u16 pipenum = ep->pipenum;
759 struct m66592 *m66592 = ep->m66592;
760
761 pipe_change(m66592, pipenum);
762 m66592_bset(m66592, M66592_ISEL, ep->fifosel);
763
764 i = 0;
765 do {
766 tmp = m66592_read(m66592, ep->fifoctr);
767 if (i++ > 100000) {
768 pr_err("pipe0 is busy. maybe cpu i/o bus "
769 "conflict. please power off this controller.");
770 return;
771 }
772 ndelay(1);
773 } while ((tmp & M66592_FRDY) == 0);
774
775 /* prepare parameters */
776 bufsize = get_buffer_size(m66592, pipenum);
777 buf = req->req.buf + req->req.actual;
778 size = min(bufsize, req->req.length - req->req.actual);
779
780 /* write fifo */
781 if (req->req.buf) {
782 if (size > 0)
783 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
784 if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
785 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
786 }
787
788 /* update parameters */
789 req->req.actual += size;
790
791 /* check transfer finish */
792 if ((!req->req.zero && (req->req.actual == req->req.length))
793 || (size % ep->ep.maxpacket)
794 || (size == 0)) {
795 disable_irq_ready(m66592, pipenum);
796 disable_irq_empty(m66592, pipenum);
797 } else {
798 disable_irq_ready(m66592, pipenum);
799 enable_irq_empty(m66592, pipenum);
800 }
801 pipe_start(m66592, pipenum);
802}
803
804static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
805{
806 u16 tmp;
807 unsigned bufsize;
808 size_t size;
809 void *buf;
810 u16 pipenum = ep->pipenum;
811 struct m66592 *m66592 = ep->m66592;
812
813 pipe_change(m66592, pipenum);
814 tmp = m66592_read(m66592, ep->fifoctr);
815 if (unlikely((tmp & M66592_FRDY) == 0)) {
816 pipe_stop(m66592, pipenum);
817 pipe_irq_disable(m66592, pipenum);
818 pr_err("write fifo not ready. pipnum=%d\n", pipenum);
819 return;
820 }
821
822 /* prepare parameters */
823 bufsize = get_buffer_size(m66592, pipenum);
824 buf = req->req.buf + req->req.actual;
825 size = min(bufsize, req->req.length - req->req.actual);
826
827 /* write fifo */
828 if (req->req.buf) {
829 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
830 if ((size == 0)
831 || ((size % ep->ep.maxpacket) != 0)
832 || ((bufsize != ep->ep.maxpacket)
833 && (bufsize > size)))
834 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
835 }
836
837 /* update parameters */
838 req->req.actual += size;
839 /* check transfer finish */
840 if ((!req->req.zero && (req->req.actual == req->req.length))
841 || (size % ep->ep.maxpacket)
842 || (size == 0)) {
843 disable_irq_ready(m66592, pipenum);
844 enable_irq_empty(m66592, pipenum);
845 } else {
846 disable_irq_empty(m66592, pipenum);
847 pipe_irq_enable(m66592, pipenum);
848 }
849}
850
851static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
852{
853 u16 tmp;
854 int rcv_len, bufsize, req_len;
855 int size;
856 void *buf;
857 u16 pipenum = ep->pipenum;
858 struct m66592 *m66592 = ep->m66592;
859 int finish = 0;
860
861 pipe_change(m66592, pipenum);
862 tmp = m66592_read(m66592, ep->fifoctr);
863 if (unlikely((tmp & M66592_FRDY) == 0)) {
864 req->req.status = -EPIPE;
865 pipe_stop(m66592, pipenum);
866 pipe_irq_disable(m66592, pipenum);
867 pr_err("read fifo not ready");
868 return;
869 }
870
871 /* prepare parameters */
872 rcv_len = tmp & M66592_DTLN;
873 bufsize = get_buffer_size(m66592, pipenum);
874
875 buf = req->req.buf + req->req.actual;
876 req_len = req->req.length - req->req.actual;
877 if (rcv_len < bufsize)
878 size = min(rcv_len, req_len);
879 else
880 size = min(bufsize, req_len);
881
882 /* update parameters */
883 req->req.actual += size;
884
885 /* check transfer finish */
886 if ((!req->req.zero && (req->req.actual == req->req.length))
887 || (size % ep->ep.maxpacket)
888 || (size == 0)) {
889 pipe_stop(m66592, pipenum);
890 pipe_irq_disable(m66592, pipenum);
891 finish = 1;
892 }
893
894 /* read fifo */
895 if (req->req.buf) {
896 if (size == 0)
897 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
898 else
899 m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
900 }
901
902 if ((ep->pipenum != 0) && finish)
903 transfer_complete(ep, req, 0);
904}
905
906static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
907{
908 u16 check;
909 u16 pipenum;
910 struct m66592_ep *ep;
911 struct m66592_request *req;
912
913 if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
914 m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
915 m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
916 M66592_CFIFOSEL);
917
918 ep = &m66592->ep[0];
919 req = list_entry(ep->queue.next, struct m66592_request, queue);
920 irq_packet_read(ep, req);
921 } else {
922 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
923 check = 1 << pipenum;
924 if ((status & check) && (enb & check)) {
925 m66592_write(m66592, ~check, M66592_BRDYSTS);
926 ep = m66592->pipenum2ep[pipenum];
927 req = list_entry(ep->queue.next,
928 struct m66592_request, queue);
929 if (ep->desc->bEndpointAddress & USB_DIR_IN)
930 irq_packet_write(ep, req);
931 else
932 irq_packet_read(ep, req);
933 }
934 }
935 }
936}
937
938static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
939{
940 u16 tmp;
941 u16 check;
942 u16 pipenum;
943 struct m66592_ep *ep;
944 struct m66592_request *req;
945
946 if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
947 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
948
949 ep = &m66592->ep[0];
950 req = list_entry(ep->queue.next, struct m66592_request, queue);
951 irq_ep0_write(ep, req);
952 } else {
953 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
954 check = 1 << pipenum;
955 if ((status & check) && (enb & check)) {
956 m66592_write(m66592, ~check, M66592_BEMPSTS);
957 tmp = control_reg_get(m66592, pipenum);
958 if ((tmp & M66592_INBUFM) == 0) {
959 disable_irq_empty(m66592, pipenum);
960 pipe_irq_disable(m66592, pipenum);
961 pipe_stop(m66592, pipenum);
962 ep = m66592->pipenum2ep[pipenum];
963 req = list_entry(ep->queue.next,
964 struct m66592_request,
965 queue);
966 if (!list_empty(&ep->queue))
967 transfer_complete(ep, req, 0);
968 }
969 }
970 }
971 }
972}
973
974static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
975__releases(m66592->lock)
976__acquires(m66592->lock)
977{
978 struct m66592_ep *ep;
979 u16 pid;
980 u16 status = 0;
981 u16 w_index = le16_to_cpu(ctrl->wIndex);
982
983 switch (ctrl->bRequestType & USB_RECIP_MASK) {
984 case USB_RECIP_DEVICE:
985 status = 1 << USB_DEVICE_SELF_POWERED;
986 break;
987 case USB_RECIP_INTERFACE:
988 status = 0;
989 break;
990 case USB_RECIP_ENDPOINT:
991 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
992 pid = control_reg_get_pid(m66592, ep->pipenum);
993 if (pid == M66592_PID_STALL)
994 status = 1 << USB_ENDPOINT_HALT;
995 else
996 status = 0;
997 break;
998 default:
999 pipe_stall(m66592, 0);
1000 return; /* exit */
1001 }
1002
1003 m66592->ep0_data = cpu_to_le16(status);
1004 m66592->ep0_req->buf = &m66592->ep0_data;
1005 m66592->ep0_req->length = 2;
1006 /* AV: what happens if we get called again before that gets through? */
1007 spin_unlock(&m66592->lock);
1008 m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
1009 spin_lock(&m66592->lock);
1010}
1011
1012static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1013{
1014 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1015 case USB_RECIP_DEVICE:
1016 control_end(m66592, 1);
1017 break;
1018 case USB_RECIP_INTERFACE:
1019 control_end(m66592, 1);
1020 break;
1021 case USB_RECIP_ENDPOINT: {
1022 struct m66592_ep *ep;
1023 struct m66592_request *req;
1024 u16 w_index = le16_to_cpu(ctrl->wIndex);
1025
1026 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1027 pipe_stop(m66592, ep->pipenum);
1028 control_reg_sqclr(m66592, ep->pipenum);
1029
1030 control_end(m66592, 1);
1031
1032 req = list_entry(ep->queue.next,
1033 struct m66592_request, queue);
1034 if (ep->busy) {
1035 ep->busy = 0;
1036 if (list_empty(&ep->queue))
1037 break;
1038 start_packet(ep, req);
1039 } else if (!list_empty(&ep->queue))
1040 pipe_start(m66592, ep->pipenum);
1041 }
1042 break;
1043 default:
1044 pipe_stall(m66592, 0);
1045 break;
1046 }
1047}
1048
1049static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1050{
1051
1052 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1053 case USB_RECIP_DEVICE:
1054 control_end(m66592, 1);
1055 break;
1056 case USB_RECIP_INTERFACE:
1057 control_end(m66592, 1);
1058 break;
1059 case USB_RECIP_ENDPOINT: {
1060 struct m66592_ep *ep;
1061 u16 w_index = le16_to_cpu(ctrl->wIndex);
1062
1063 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1064 pipe_stall(m66592, ep->pipenum);
1065
1066 control_end(m66592, 1);
1067 }
1068 break;
1069 default:
1070 pipe_stall(m66592, 0);
1071 break;
1072 }
1073}
1074
1075/* if return value is true, call class driver's setup() */
1076static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1077{
1078 u16 *p = (u16 *)ctrl;
1079 unsigned long offset = M66592_USBREQ;
1080 int i, ret = 0;
1081
1082 /* read fifo */
1083 m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
1084
1085 for (i = 0; i < 4; i++)
1086 p[i] = m66592_read(m66592, offset + i*2);
1087
1088 /* check request */
1089 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1090 switch (ctrl->bRequest) {
1091 case USB_REQ_GET_STATUS:
1092 get_status(m66592, ctrl);
1093 break;
1094 case USB_REQ_CLEAR_FEATURE:
1095 clear_feature(m66592, ctrl);
1096 break;
1097 case USB_REQ_SET_FEATURE:
1098 set_feature(m66592, ctrl);
1099 break;
1100 default:
1101 ret = 1;
1102 break;
1103 }
1104 } else
1105 ret = 1;
1106 return ret;
1107}
1108
1109static void m66592_update_usb_speed(struct m66592 *m66592)
1110{
1111 u16 speed = get_usb_speed(m66592);
1112
1113 switch (speed) {
1114 case M66592_HSMODE:
1115 m66592->gadget.speed = USB_SPEED_HIGH;
1116 break;
1117 case M66592_FSMODE:
1118 m66592->gadget.speed = USB_SPEED_FULL;
1119 break;
1120 default:
1121 m66592->gadget.speed = USB_SPEED_UNKNOWN;
1122 pr_err("USB speed unknown\n");
1123 }
1124}
1125
1126static void irq_device_state(struct m66592 *m66592)
1127{
1128 u16 dvsq;
1129
1130 dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
1131 m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
1132
1133 if (dvsq == M66592_DS_DFLT) { /* bus reset */
1134 m66592->driver->disconnect(&m66592->gadget);
1135 m66592_update_usb_speed(m66592);
1136 }
1137 if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
1138 m66592_update_usb_speed(m66592);
1139 if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
1140 && m66592->gadget.speed == USB_SPEED_UNKNOWN)
1141 m66592_update_usb_speed(m66592);
1142
1143 m66592->old_dvsq = dvsq;
1144}
1145
1146static void irq_control_stage(struct m66592 *m66592)
1147__releases(m66592->lock)
1148__acquires(m66592->lock)
1149{
1150 struct usb_ctrlrequest ctrl;
1151 u16 ctsq;
1152
1153 ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
1154 m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
1155
1156 switch (ctsq) {
1157 case M66592_CS_IDST: {
1158 struct m66592_ep *ep;
1159 struct m66592_request *req;
1160 ep = &m66592->ep[0];
1161 req = list_entry(ep->queue.next, struct m66592_request, queue);
1162 transfer_complete(ep, req, 0);
1163 }
1164 break;
1165
1166 case M66592_CS_RDDS:
1167 case M66592_CS_WRDS:
1168 case M66592_CS_WRND:
1169 if (setup_packet(m66592, &ctrl)) {
1170 spin_unlock(&m66592->lock);
1171 if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
1172 pipe_stall(m66592, 0);
1173 spin_lock(&m66592->lock);
1174 }
1175 break;
1176 case M66592_CS_RDSS:
1177 case M66592_CS_WRSS:
1178 control_end(m66592, 0);
1179 break;
1180 default:
1181 pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
1182 break;
1183 }
1184}
1185
1186static irqreturn_t m66592_irq(int irq, void *_m66592)
1187{
1188 struct m66592 *m66592 = _m66592;
1189 u16 intsts0;
1190 u16 intenb0;
1191 u16 brdysts, nrdysts, bempsts;
1192 u16 brdyenb, nrdyenb, bempenb;
1193 u16 savepipe;
1194 u16 mask0;
1195
1196 spin_lock(&m66592->lock);
1197
1198 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1199 intenb0 = m66592_read(m66592, M66592_INTENB0);
1200
1201 if (m66592->pdata->on_chip && !intsts0 && !intenb0) {
1202 /*
1203 * When USB clock stops, it cannot read register. Even if a
1204 * clock stops, the interrupt occurs. So this driver turn on
1205 * a clock by this timing and do re-reading of register.
1206 */
1207 m66592_start_xclock(m66592);
1208 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1209 intenb0 = m66592_read(m66592, M66592_INTENB0);
1210 }
1211
1212 savepipe = m66592_read(m66592, M66592_CFIFOSEL);
1213
1214 mask0 = intsts0 & intenb0;
1215 if (mask0) {
1216 brdysts = m66592_read(m66592, M66592_BRDYSTS);
1217 nrdysts = m66592_read(m66592, M66592_NRDYSTS);
1218 bempsts = m66592_read(m66592, M66592_BEMPSTS);
1219 brdyenb = m66592_read(m66592, M66592_BRDYENB);
1220 nrdyenb = m66592_read(m66592, M66592_NRDYENB);
1221 bempenb = m66592_read(m66592, M66592_BEMPENB);
1222
1223 if (mask0 & M66592_VBINT) {
1224 m66592_write(m66592, 0xffff & ~M66592_VBINT,
1225 M66592_INTSTS0);
1226 m66592_start_xclock(m66592);
1227
1228 /* start vbus sampling */
1229 m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
1230 & M66592_VBSTS;
1231 m66592->scount = M66592_MAX_SAMPLING;
1232
1233 mod_timer(&m66592->timer,
1234 jiffies + msecs_to_jiffies(50));
1235 }
1236 if (intsts0 & M66592_DVSQ)
1237 irq_device_state(m66592);
1238
1239 if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
1240 && (brdysts & brdyenb)) {
1241 irq_pipe_ready(m66592, brdysts, brdyenb);
1242 }
1243 if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
1244 && (bempsts & bempenb)) {
1245 irq_pipe_empty(m66592, bempsts, bempenb);
1246 }
1247
1248 if (intsts0 & M66592_CTRT)
1249 irq_control_stage(m66592);
1250 }
1251
1252 m66592_write(m66592, savepipe, M66592_CFIFOSEL);
1253
1254 spin_unlock(&m66592->lock);
1255 return IRQ_HANDLED;
1256}
1257
1258static void m66592_timer(unsigned long _m66592)
1259{
1260 struct m66592 *m66592 = (struct m66592 *)_m66592;
1261 unsigned long flags;
1262 u16 tmp;
1263
1264 spin_lock_irqsave(&m66592->lock, flags);
1265 tmp = m66592_read(m66592, M66592_SYSCFG);
1266 if (!(tmp & M66592_RCKE)) {
1267 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
1268 udelay(10);
1269 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
1270 }
1271 if (m66592->scount > 0) {
1272 tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
1273 if (tmp == m66592->old_vbus) {
1274 m66592->scount--;
1275 if (m66592->scount == 0) {
1276 if (tmp == M66592_VBSTS)
1277 m66592_usb_connect(m66592);
1278 else
1279 m66592_usb_disconnect(m66592);
1280 } else {
1281 mod_timer(&m66592->timer,
1282 jiffies + msecs_to_jiffies(50));
1283 }
1284 } else {
1285 m66592->scount = M66592_MAX_SAMPLING;
1286 m66592->old_vbus = tmp;
1287 mod_timer(&m66592->timer,
1288 jiffies + msecs_to_jiffies(50));
1289 }
1290 }
1291 spin_unlock_irqrestore(&m66592->lock, flags);
1292}
1293
1294/*-------------------------------------------------------------------------*/
1295static int m66592_enable(struct usb_ep *_ep,
1296 const struct usb_endpoint_descriptor *desc)
1297{
1298 struct m66592_ep *ep;
1299
1300 ep = container_of(_ep, struct m66592_ep, ep);
1301 return alloc_pipe_config(ep, desc);
1302}
1303
1304static int m66592_disable(struct usb_ep *_ep)
1305{
1306 struct m66592_ep *ep;
1307 struct m66592_request *req;
1308 unsigned long flags;
1309
1310 ep = container_of(_ep, struct m66592_ep, ep);
1311 BUG_ON(!ep);
1312
1313 while (!list_empty(&ep->queue)) {
1314 req = list_entry(ep->queue.next, struct m66592_request, queue);
1315 spin_lock_irqsave(&ep->m66592->lock, flags);
1316 transfer_complete(ep, req, -ECONNRESET);
1317 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1318 }
1319
1320 pipe_irq_disable(ep->m66592, ep->pipenum);
1321 return free_pipe_config(ep);
1322}
1323
1324static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
1325 gfp_t gfp_flags)
1326{
1327 struct m66592_request *req;
1328
1329 req = kzalloc(sizeof(struct m66592_request), gfp_flags);
1330 if (!req)
1331 return NULL;
1332
1333 INIT_LIST_HEAD(&req->queue);
1334
1335 return &req->req;
1336}
1337
1338static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
1339{
1340 struct m66592_request *req;
1341
1342 req = container_of(_req, struct m66592_request, req);
1343 kfree(req);
1344}
1345
1346static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
1347 gfp_t gfp_flags)
1348{
1349 struct m66592_ep *ep;
1350 struct m66592_request *req;
1351 unsigned long flags;
1352 int request = 0;
1353
1354 ep = container_of(_ep, struct m66592_ep, ep);
1355 req = container_of(_req, struct m66592_request, req);
1356
1357 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
1358 return -ESHUTDOWN;
1359
1360 spin_lock_irqsave(&ep->m66592->lock, flags);
1361
1362 if (list_empty(&ep->queue))
1363 request = 1;
1364
1365 list_add_tail(&req->queue, &ep->queue);
1366 req->req.actual = 0;
1367 req->req.status = -EINPROGRESS;
1368
1369 if (ep->desc == NULL) /* control */
1370 start_ep0(ep, req);
1371 else {
1372 if (request && !ep->busy)
1373 start_packet(ep, req);
1374 }
1375
1376 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1377
1378 return 0;
1379}
1380
1381static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1382{
1383 struct m66592_ep *ep;
1384 struct m66592_request *req;
1385 unsigned long flags;
1386
1387 ep = container_of(_ep, struct m66592_ep, ep);
1388 req = container_of(_req, struct m66592_request, req);
1389
1390 spin_lock_irqsave(&ep->m66592->lock, flags);
1391 if (!list_empty(&ep->queue))
1392 transfer_complete(ep, req, -ECONNRESET);
1393 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1394
1395 return 0;
1396}
1397
1398static int m66592_set_halt(struct usb_ep *_ep, int value)
1399{
1400 struct m66592_ep *ep;
1401 struct m66592_request *req;
1402 unsigned long flags;
1403 int ret = 0;
1404
1405 ep = container_of(_ep, struct m66592_ep, ep);
1406 req = list_entry(ep->queue.next, struct m66592_request, queue);
1407
1408 spin_lock_irqsave(&ep->m66592->lock, flags);
1409 if (!list_empty(&ep->queue)) {
1410 ret = -EAGAIN;
1411 goto out;
1412 }
1413 if (value) {
1414 ep->busy = 1;
1415 pipe_stall(ep->m66592, ep->pipenum);
1416 } else {
1417 ep->busy = 0;
1418 pipe_stop(ep->m66592, ep->pipenum);
1419 }
1420
1421out:
1422 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1423 return ret;
1424}
1425
1426static void m66592_fifo_flush(struct usb_ep *_ep)
1427{
1428 struct m66592_ep *ep;
1429 unsigned long flags;
1430
1431 ep = container_of(_ep, struct m66592_ep, ep);
1432 spin_lock_irqsave(&ep->m66592->lock, flags);
1433 if (list_empty(&ep->queue) && !ep->busy) {
1434 pipe_stop(ep->m66592, ep->pipenum);
1435 m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
1436 }
1437 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1438}
1439
1440static struct usb_ep_ops m66592_ep_ops = {
1441 .enable = m66592_enable,
1442 .disable = m66592_disable,
1443
1444 .alloc_request = m66592_alloc_request,
1445 .free_request = m66592_free_request,
1446
1447 .queue = m66592_queue,
1448 .dequeue = m66592_dequeue,
1449
1450 .set_halt = m66592_set_halt,
1451 .fifo_flush = m66592_fifo_flush,
1452};
1453
1454/*-------------------------------------------------------------------------*/
1455static struct m66592 *the_controller;
1456
1457int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1458{
1459 struct m66592 *m66592 = the_controller;
1460 int retval;
1461
1462 if (!driver
1463 || driver->speed != USB_SPEED_HIGH
1464 || !driver->bind
1465 || !driver->setup)
1466 return -EINVAL;
1467 if (!m66592)
1468 return -ENODEV;
1469 if (m66592->driver)
1470 return -EBUSY;
1471
1472 /* hook up the driver */
1473 driver->driver.bus = NULL;
1474 m66592->driver = driver;
1475 m66592->gadget.dev.driver = &driver->driver;
1476
1477 retval = device_add(&m66592->gadget.dev);
1478 if (retval) {
1479 pr_err("device_add error (%d)\n", retval);
1480 goto error;
1481 }
1482
1483 retval = driver->bind (&m66592->gadget);
1484 if (retval) {
1485 pr_err("bind to driver error (%d)\n", retval);
1486 device_del(&m66592->gadget.dev);
1487 goto error;
1488 }
1489
1490 m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1491 if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
1492 m66592_start_xclock(m66592);
1493 /* start vbus sampling */
1494 m66592->old_vbus = m66592_read(m66592,
1495 M66592_INTSTS0) & M66592_VBSTS;
1496 m66592->scount = M66592_MAX_SAMPLING;
1497 mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
1498 }
1499
1500 return 0;
1501
1502error:
1503 m66592->driver = NULL;
1504 m66592->gadget.dev.driver = NULL;
1505
1506 return retval;
1507}
1508EXPORT_SYMBOL(usb_gadget_register_driver);
1509
1510int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1511{
1512 struct m66592 *m66592 = the_controller;
1513 unsigned long flags;
1514
1515 if (driver != m66592->driver || !driver->unbind)
1516 return -EINVAL;
1517
1518 spin_lock_irqsave(&m66592->lock, flags);
1519 if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
1520 m66592_usb_disconnect(m66592);
1521 spin_unlock_irqrestore(&m66592->lock, flags);
1522
1523 m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1524
1525 driver->unbind(&m66592->gadget);
1526 m66592->gadget.dev.driver = NULL;
1527
1528 init_controller(m66592);
1529 disable_controller(m66592);
1530
1531 device_del(&m66592->gadget.dev);
1532 m66592->driver = NULL;
1533 return 0;
1534}
1535EXPORT_SYMBOL(usb_gadget_unregister_driver);
1536
1537/*-------------------------------------------------------------------------*/
1538static int m66592_get_frame(struct usb_gadget *_gadget)
1539{
1540 struct m66592 *m66592 = gadget_to_m66592(_gadget);
1541 return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
1542}
1543
1544static struct usb_gadget_ops m66592_gadget_ops = {
1545 .get_frame = m66592_get_frame,
1546};
1547
1548static int __exit m66592_remove(struct platform_device *pdev)
1549{
1550 struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
1551
1552 del_timer_sync(&m66592->timer);
1553 iounmap(m66592->reg);
1554 free_irq(platform_get_irq(pdev, 0), m66592);
1555 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1556#ifdef CONFIG_HAVE_CLK
1557 if (m66592->pdata->on_chip) {
1558 clk_disable(m66592->clk);
1559 clk_put(m66592->clk);
1560 }
1561#endif
1562 kfree(m66592);
1563 return 0;
1564}
1565
1566static void nop_completion(struct usb_ep *ep, struct usb_request *r)
1567{
1568}
1569
1570static int __init m66592_probe(struct platform_device *pdev)
1571{
1572 struct resource *res, *ires;
1573 void __iomem *reg = NULL;
1574 struct m66592 *m66592 = NULL;
1575#ifdef CONFIG_HAVE_CLK
1576 char clk_name[8];
1577#endif
1578 int ret = 0;
1579 int i;
1580
1581 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1582 if (!res) {
1583 ret = -ENODEV;
1584 pr_err("platform_get_resource error.\n");
1585 goto clean_up;
1586 }
1587
1588 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1589 if (!ires) {
1590 ret = -ENODEV;
1591 dev_err(&pdev->dev,
1592 "platform_get_resource IORESOURCE_IRQ error.\n");
1593 goto clean_up;
1594 }
1595
1596 reg = ioremap(res->start, resource_size(res));
1597 if (reg == NULL) {
1598 ret = -ENOMEM;
1599 pr_err("ioremap error.\n");
1600 goto clean_up;
1601 }
1602
1603 if (pdev->dev.platform_data == NULL) {
1604 dev_err(&pdev->dev, "no platform data\n");
1605 ret = -ENODEV;
1606 goto clean_up;
1607 }
1608
1609 /* initialize ucd */
1610 m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
1611 if (m66592 == NULL) {
1612 pr_err("kzalloc error\n");
1613 goto clean_up;
1614 }
1615
1616 m66592->pdata = pdev->dev.platform_data;
1617 m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
1618
1619 spin_lock_init(&m66592->lock);
1620 dev_set_drvdata(&pdev->dev, m66592);
1621
1622 m66592->gadget.ops = &m66592_gadget_ops;
1623 device_initialize(&m66592->gadget.dev);
1624 dev_set_name(&m66592->gadget.dev, "gadget");
1625 m66592->gadget.is_dualspeed = 1;
1626 m66592->gadget.dev.parent = &pdev->dev;
1627 m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
1628 m66592->gadget.dev.release = pdev->dev.release;
1629 m66592->gadget.name = udc_name;
1630
1631 init_timer(&m66592->timer);
1632 m66592->timer.function = m66592_timer;
1633 m66592->timer.data = (unsigned long)m66592;
1634 m66592->reg = reg;
1635
1636 ret = request_irq(ires->start, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
1637 udc_name, m66592);
1638 if (ret < 0) {
1639 pr_err("request_irq error (%d)\n", ret);
1640 goto clean_up;
1641 }
1642
1643#ifdef CONFIG_HAVE_CLK
1644 if (m66592->pdata->on_chip) {
1645 snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
1646 m66592->clk = clk_get(&pdev->dev, clk_name);
1647 if (IS_ERR(m66592->clk)) {
1648 dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
1649 clk_name);
1650 ret = PTR_ERR(m66592->clk);
1651 goto clean_up2;
1652 }
1653 clk_enable(m66592->clk);
1654 }
1655#endif
1656 INIT_LIST_HEAD(&m66592->gadget.ep_list);
1657 m66592->gadget.ep0 = &m66592->ep[0].ep;
1658 INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
1659 for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
1660 struct m66592_ep *ep = &m66592->ep[i];
1661
1662 if (i != 0) {
1663 INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
1664 list_add_tail(&m66592->ep[i].ep.ep_list,
1665 &m66592->gadget.ep_list);
1666 }
1667 ep->m66592 = m66592;
1668 INIT_LIST_HEAD(&ep->queue);
1669 ep->ep.name = m66592_ep_name[i];
1670 ep->ep.ops = &m66592_ep_ops;
1671 ep->ep.maxpacket = 512;
1672 }
1673 m66592->ep[0].ep.maxpacket = 64;
1674 m66592->ep[0].pipenum = 0;
1675 m66592->ep[0].fifoaddr = M66592_CFIFO;
1676 m66592->ep[0].fifosel = M66592_CFIFOSEL;
1677 m66592->ep[0].fifoctr = M66592_CFIFOCTR;
1678 m66592->ep[0].fifotrn = 0;
1679 m66592->ep[0].pipectr = get_pipectr_addr(0);
1680 m66592->pipenum2ep[0] = &m66592->ep[0];
1681 m66592->epaddr2ep[0] = &m66592->ep[0];
1682
1683 the_controller = m66592;
1684
1685 m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
1686 if (m66592->ep0_req == NULL)
1687 goto clean_up3;
1688 m66592->ep0_req->complete = nop_completion;
1689
1690 init_controller(m66592);
1691
1692 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1693 return 0;
1694
1695clean_up3:
1696#ifdef CONFIG_HAVE_CLK
1697 if (m66592->pdata->on_chip) {
1698 clk_disable(m66592->clk);
1699 clk_put(m66592->clk);
1700 }
1701clean_up2:
1702#endif
1703 free_irq(ires->start, m66592);
1704clean_up:
1705 if (m66592) {
1706 if (m66592->ep0_req)
1707 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1708 kfree(m66592);
1709 }
1710 if (reg)
1711 iounmap(reg);
1712
1713 return ret;
1714}
1715
1716/*-------------------------------------------------------------------------*/
1717static struct platform_driver m66592_driver = {
1718 .remove = __exit_p(m66592_remove),
1719 .driver = {
1720 .name = (char *) udc_name,
1721 .owner = THIS_MODULE,
1722 },
1723};
1724
1725static int __init m66592_udc_init(void)
1726{
1727 return platform_driver_probe(&m66592_driver, m66592_probe);
1728}
1729module_init(m66592_udc_init);
1730
1731static void __exit m66592_udc_cleanup(void)
1732{
1733 platform_driver_unregister(&m66592_driver);
1734}
1735module_exit(m66592_udc_cleanup);