tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

kernel / drivers / net / wireless / rt2x00 / rt2800lib.c
at 17431928194b36a0f88082df875e2e036da7fddf 2745 lines 93 kB view raw
1/* 2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 3 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 4 5 Based on the original rt2800pci.c and rt2800usb.c. 6 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com> 7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 13 <http://rt2x00.serialmonkey.com> 14 15 This program is free software; you can redistribute it and/or modify 16 it under the terms of the GNU General Public License as published by 17 the Free Software Foundation; either version 2 of the License, or 18 (at your option) any later version. 19 20 This program is distributed in the hope that it will be useful, 21 but WITHOUT ANY WARRANTY; without even the implied warranty of 22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 GNU General Public License for more details. 24 25 You should have received a copy of the GNU General Public License 26 along with this program; if not, write to the 27 Free Software Foundation, Inc., 28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 */ 30 31/* 32 Module: rt2800lib 33 Abstract: rt2800 generic device routines. 34 */ 35 36#include <linux/kernel.h> 37#include <linux/module.h> 38#include <linux/slab.h> 39 40#include "rt2x00.h" 41#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE) 42#include "rt2x00usb.h" 43#endif 44#include "rt2800lib.h" 45#include "rt2800.h" 46#include "rt2800usb.h" 47 48MODULE_AUTHOR("Bartlomiej Zolnierkiewicz"); 49MODULE_DESCRIPTION("rt2800 library"); 50MODULE_LICENSE("GPL"); 51 52/* 53 * Register access. 54 * All access to the CSR registers will go through the methods 55 * rt2800_register_read and rt2800_register_write. 56 * BBP and RF register require indirect register access, 57 * and use the CSR registers BBPCSR and RFCSR to achieve this. 58 * These indirect registers work with busy bits, 59 * and we will try maximal REGISTER_BUSY_COUNT times to access 60 * the register while taking a REGISTER_BUSY_DELAY us delay 61 * between each attampt. When the busy bit is still set at that time, 62 * the access attempt is considered to have failed, 63 * and we will print an error. 64 * The _lock versions must be used if you already hold the csr_mutex 65 */ 66#define WAIT_FOR_BBP(__dev, __reg) \ 67 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 68#define WAIT_FOR_RFCSR(__dev, __reg) \ 69 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 70#define WAIT_FOR_RF(__dev, __reg) \ 71 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 72#define WAIT_FOR_MCU(__dev, __reg) \ 73 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 74 H2M_MAILBOX_CSR_OWNER, (__reg)) 75 76static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 77{ 78 /* check for rt2872 on SoC */ 79 if (!rt2x00_is_soc(rt2x00dev) || 80 !rt2x00_rt(rt2x00dev, RT2872)) 81 return false; 82 83 /* we know for sure that these rf chipsets are used on rt305x boards */ 84 if (rt2x00_rf(rt2x00dev, RF3020) || 85 rt2x00_rf(rt2x00dev, RF3021) || 86 rt2x00_rf(rt2x00dev, RF3022)) 87 return true; 88 89 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n"); 90 return false; 91} 92 93static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 94 const unsigned int word, const u8 value) 95{ 96 u32 reg; 97 98 mutex_lock(&rt2x00dev->csr_mutex); 99 100 /* 101 * Wait until the BBP becomes available, afterwards we 102 * can safely write the new data into the register. 103 */ 104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { 105 reg = 0; 106 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value); 107 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word); 108 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1); 109 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0); 110 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) 111 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1); 112 113 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 114 } 115 116 mutex_unlock(&rt2x00dev->csr_mutex); 117} 118 119static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, 120 const unsigned int word, u8 *value) 121{ 122 u32 reg; 123 124 mutex_lock(&rt2x00dev->csr_mutex); 125 126 /* 127 * Wait until the BBP becomes available, afterwards we 128 * can safely write the read request into the register. 129 * After the data has been written, we wait until hardware 130 * returns the correct value, if at any time the register 131 * doesn't become available in time, reg will be 0xffffffff 132 * which means we return 0xff to the caller. 133 */ 134 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { 135 reg = 0; 136 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word); 137 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1); 138 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1); 139 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) 140 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1); 141 142 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 143 144 WAIT_FOR_BBP(rt2x00dev, &reg); 145 } 146 147 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 148 149 mutex_unlock(&rt2x00dev->csr_mutex); 150} 151 152static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 153 const unsigned int word, const u8 value) 154{ 155 u32 reg; 156 157 mutex_lock(&rt2x00dev->csr_mutex); 158 159 /* 160 * Wait until the RFCSR becomes available, afterwards we 161 * can safely write the new data into the register. 162 */ 163 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) { 164 reg = 0; 165 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value); 166 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word); 167 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1); 168 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1); 169 170 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 171 } 172 173 mutex_unlock(&rt2x00dev->csr_mutex); 174} 175 176static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 177 const unsigned int word, u8 *value) 178{ 179 u32 reg; 180 181 mutex_lock(&rt2x00dev->csr_mutex); 182 183 /* 184 * Wait until the RFCSR becomes available, afterwards we 185 * can safely write the read request into the register. 186 * After the data has been written, we wait until hardware 187 * returns the correct value, if at any time the register 188 * doesn't become available in time, reg will be 0xffffffff 189 * which means we return 0xff to the caller. 190 */ 191 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) { 192 reg = 0; 193 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word); 194 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0); 195 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1); 196 197 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 198 199 WAIT_FOR_RFCSR(rt2x00dev, &reg); 200 } 201 202 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 203 204 mutex_unlock(&rt2x00dev->csr_mutex); 205} 206 207static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 208 const unsigned int word, const u32 value) 209{ 210 u32 reg; 211 212 mutex_lock(&rt2x00dev->csr_mutex); 213 214 /* 215 * Wait until the RF becomes available, afterwards we 216 * can safely write the new data into the register. 217 */ 218 if (WAIT_FOR_RF(rt2x00dev, &reg)) { 219 reg = 0; 220 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value); 221 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0); 222 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0); 223 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1); 224 225 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 226 rt2x00_rf_write(rt2x00dev, word, value); 227 } 228 229 mutex_unlock(&rt2x00dev->csr_mutex); 230} 231 232void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 233 const u8 command, const u8 token, 234 const u8 arg0, const u8 arg1) 235{ 236 u32 reg; 237 238 /* 239 * SOC devices don't support MCU requests. 240 */ 241 if (rt2x00_is_soc(rt2x00dev)) 242 return; 243 244 mutex_lock(&rt2x00dev->csr_mutex); 245 246 /* 247 * Wait until the MCU becomes available, afterwards we 248 * can safely write the new data into the register. 249 */ 250 if (WAIT_FOR_MCU(rt2x00dev, &reg)) { 251 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1); 252 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token); 253 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0); 254 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1); 255 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 256 257 reg = 0; 258 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command); 259 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 260 } 261 262 mutex_unlock(&rt2x00dev->csr_mutex); 263} 264EXPORT_SYMBOL_GPL(rt2800_mcu_request); 265 266int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 267{ 268 unsigned int i; 269 u32 reg; 270 271 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 272 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 273 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 274 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 275 return 0; 276 277 msleep(1); 278 } 279 280 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n"); 281 return -EACCES; 282} 283EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 284 285void rt2800_write_txwi(struct sk_buff *skb, struct txentry_desc *txdesc) 286{ 287 __le32 *txwi = (__le32 *)(skb->data - TXWI_DESC_SIZE); 288 u32 word; 289 290 /* 291 * Initialize TX Info descriptor 292 */ 293 rt2x00_desc_read(txwi, 0, &word); 294 rt2x00_set_field32(&word, TXWI_W0_FRAG, 295 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 296 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0); 297 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 298 rt2x00_set_field32(&word, TXWI_W0_TS, 299 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 300 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 301 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 302 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density); 303 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop); 304 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs); 305 rt2x00_set_field32(&word, TXWI_W0_BW, 306 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 307 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 308 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 309 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc); 310 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 311 rt2x00_desc_write(txwi, 0, word); 312 313 rt2x00_desc_read(txwi, 1, &word); 314 rt2x00_set_field32(&word, TXWI_W1_ACK, 315 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 316 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 317 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 318 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size); 319 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 320 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 321 txdesc->key_idx : 0xff); 322 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 323 txdesc->length); 324 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1); 325 rt2x00_desc_write(txwi, 1, word); 326 327 /* 328 * Always write 0 to IV/EIV fields, hardware will insert the IV 329 * from the IVEIV register when TXD_W3_WIV is set to 0. 330 * When TXD_W3_WIV is set to 1 it will use the IV data 331 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 332 * crypto entry in the registers should be used to encrypt the frame. 333 */ 334 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */); 335 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */); 336} 337EXPORT_SYMBOL_GPL(rt2800_write_txwi); 338 339void rt2800_process_rxwi(struct sk_buff *skb, struct rxdone_entry_desc *rxdesc) 340{ 341 __le32 *rxwi = (__le32 *) skb->data; 342 u32 word; 343 344 rt2x00_desc_read(rxwi, 0, &word); 345 346 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 347 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 348 349 rt2x00_desc_read(rxwi, 1, &word); 350 351 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 352 rxdesc->flags |= RX_FLAG_SHORT_GI; 353 354 if (rt2x00_get_field32(word, RXWI_W1_BW)) 355 rxdesc->flags |= RX_FLAG_40MHZ; 356 357 /* 358 * Detect RX rate, always use MCS as signal type. 359 */ 360 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 361 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 362 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 363 364 /* 365 * Mask of 0x8 bit to remove the short preamble flag. 366 */ 367 if (rxdesc->rate_mode == RATE_MODE_CCK) 368 rxdesc->signal &= ~0x8; 369 370 rt2x00_desc_read(rxwi, 2, &word); 371 372 rxdesc->rssi = 373 (rt2x00_get_field32(word, RXWI_W2_RSSI0) + 374 rt2x00_get_field32(word, RXWI_W2_RSSI1)) / 2; 375 376 /* 377 * Remove RXWI descriptor from start of buffer. 378 */ 379 skb_pull(skb, RXWI_DESC_SIZE); 380} 381EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 382 383#ifdef CONFIG_RT2X00_LIB_DEBUGFS 384const struct rt2x00debug rt2800_rt2x00debug = { 385 .owner = THIS_MODULE, 386 .csr = { 387 .read = rt2800_register_read, 388 .write = rt2800_register_write, 389 .flags = RT2X00DEBUGFS_OFFSET, 390 .word_base = CSR_REG_BASE, 391 .word_size = sizeof(u32), 392 .word_count = CSR_REG_SIZE / sizeof(u32), 393 }, 394 .eeprom = { 395 .read = rt2x00_eeprom_read, 396 .write = rt2x00_eeprom_write, 397 .word_base = EEPROM_BASE, 398 .word_size = sizeof(u16), 399 .word_count = EEPROM_SIZE / sizeof(u16), 400 }, 401 .bbp = { 402 .read = rt2800_bbp_read, 403 .write = rt2800_bbp_write, 404 .word_base = BBP_BASE, 405 .word_size = sizeof(u8), 406 .word_count = BBP_SIZE / sizeof(u8), 407 }, 408 .rf = { 409 .read = rt2x00_rf_read, 410 .write = rt2800_rf_write, 411 .word_base = RF_BASE, 412 .word_size = sizeof(u32), 413 .word_count = RF_SIZE / sizeof(u32), 414 }, 415}; 416EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 417#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 418 419int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 420{ 421 u32 reg; 422 423 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg); 424 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2); 425} 426EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 427 428#ifdef CONFIG_RT2X00_LIB_LEDS 429static void rt2800_brightness_set(struct led_classdev *led_cdev, 430 enum led_brightness brightness) 431{ 432 struct rt2x00_led *led = 433 container_of(led_cdev, struct rt2x00_led, led_dev); 434 unsigned int enabled = brightness != LED_OFF; 435 unsigned int bg_mode = 436 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); 437 unsigned int polarity = 438 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 439 EEPROM_FREQ_LED_POLARITY); 440 unsigned int ledmode = 441 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 442 EEPROM_FREQ_LED_MODE); 443 444 if (led->type == LED_TYPE_RADIO) { 445 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 446 enabled ? 0x20 : 0); 447 } else if (led->type == LED_TYPE_ASSOC) { 448 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 449 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 450 } else if (led->type == LED_TYPE_QUALITY) { 451 /* 452 * The brightness is divided into 6 levels (0 - 5), 453 * The specs tell us the following levels: 454 * 0, 1 ,3, 7, 15, 31 455 * to determine the level in a simple way we can simply 456 * work with bitshifting: 457 * (1 << level) - 1 458 */ 459 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 460 (1 << brightness / (LED_FULL / 6)) - 1, 461 polarity); 462 } 463} 464 465static int rt2800_blink_set(struct led_classdev *led_cdev, 466 unsigned long *delay_on, unsigned long *delay_off) 467{ 468 struct rt2x00_led *led = 469 container_of(led_cdev, struct rt2x00_led, led_dev); 470 u32 reg; 471 472 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg); 473 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on); 474 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off); 475 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 476 477 return 0; 478} 479 480static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 481 struct rt2x00_led *led, enum led_type type) 482{ 483 led->rt2x00dev = rt2x00dev; 484 led->type = type; 485 led->led_dev.brightness_set = rt2800_brightness_set; 486 led->led_dev.blink_set = rt2800_blink_set; 487 led->flags = LED_INITIALIZED; 488} 489#endif /* CONFIG_RT2X00_LIB_LEDS */ 490 491/* 492 * Configuration handlers. 493 */ 494static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev, 495 struct rt2x00lib_crypto *crypto, 496 struct ieee80211_key_conf *key) 497{ 498 struct mac_wcid_entry wcid_entry; 499 struct mac_iveiv_entry iveiv_entry; 500 u32 offset; 501 u32 reg; 502 503 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 504 505 rt2800_register_read(rt2x00dev, offset, &reg); 506 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 507 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 508 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 509 (crypto->cmd == SET_KEY) * crypto->cipher); 510 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, 511 (crypto->cmd == SET_KEY) * crypto->bssidx); 512 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 513 rt2800_register_write(rt2x00dev, offset, reg); 514 515 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 516 517 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 518 if ((crypto->cipher == CIPHER_TKIP) || 519 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 520 (crypto->cipher == CIPHER_AES)) 521 iveiv_entry.iv[3] |= 0x20; 522 iveiv_entry.iv[3] |= key->keyidx << 6; 523 rt2800_register_multiwrite(rt2x00dev, offset, 524 &iveiv_entry, sizeof(iveiv_entry)); 525 526 offset = MAC_WCID_ENTRY(key->hw_key_idx); 527 528 memset(&wcid_entry, 0, sizeof(wcid_entry)); 529 if (crypto->cmd == SET_KEY) 530 memcpy(&wcid_entry, crypto->address, ETH_ALEN); 531 rt2800_register_multiwrite(rt2x00dev, offset, 532 &wcid_entry, sizeof(wcid_entry)); 533} 534 535int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 536 struct rt2x00lib_crypto *crypto, 537 struct ieee80211_key_conf *key) 538{ 539 struct hw_key_entry key_entry; 540 struct rt2x00_field32 field; 541 u32 offset; 542 u32 reg; 543 544 if (crypto->cmd == SET_KEY) { 545 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 546 547 memcpy(key_entry.key, crypto->key, 548 sizeof(key_entry.key)); 549 memcpy(key_entry.tx_mic, crypto->tx_mic, 550 sizeof(key_entry.tx_mic)); 551 memcpy(key_entry.rx_mic, crypto->rx_mic, 552 sizeof(key_entry.rx_mic)); 553 554 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 555 rt2800_register_multiwrite(rt2x00dev, offset, 556 &key_entry, sizeof(key_entry)); 557 } 558 559 /* 560 * The cipher types are stored over multiple registers 561 * starting with SHARED_KEY_MODE_BASE each word will have 562 * 32 bits and contains the cipher types for 2 bssidx each. 563 * Using the correct defines correctly will cause overhead, 564 * so just calculate the correct offset. 565 */ 566 field.bit_offset = 4 * (key->hw_key_idx % 8); 567 field.bit_mask = 0x7 << field.bit_offset; 568 569 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 570 571 rt2800_register_read(rt2x00dev, offset, &reg); 572 rt2x00_set_field32(&reg, field, 573 (crypto->cmd == SET_KEY) * crypto->cipher); 574 rt2800_register_write(rt2x00dev, offset, reg); 575 576 /* 577 * Update WCID information 578 */ 579 rt2800_config_wcid_attr(rt2x00dev, crypto, key); 580 581 return 0; 582} 583EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 584 585int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 586 struct rt2x00lib_crypto *crypto, 587 struct ieee80211_key_conf *key) 588{ 589 struct hw_key_entry key_entry; 590 u32 offset; 591 592 if (crypto->cmd == SET_KEY) { 593 /* 594 * 1 pairwise key is possible per AID, this means that the AID 595 * equals our hw_key_idx. Make sure the WCID starts _after_ the 596 * last possible shared key entry. 597 */ 598 if (crypto->aid > (256 - 32)) 599 return -ENOSPC; 600 601 key->hw_key_idx = 32 + crypto->aid; 602 603 memcpy(key_entry.key, crypto->key, 604 sizeof(key_entry.key)); 605 memcpy(key_entry.tx_mic, crypto->tx_mic, 606 sizeof(key_entry.tx_mic)); 607 memcpy(key_entry.rx_mic, crypto->rx_mic, 608 sizeof(key_entry.rx_mic)); 609 610 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 611 rt2800_register_multiwrite(rt2x00dev, offset, 612 &key_entry, sizeof(key_entry)); 613 } 614 615 /* 616 * Update WCID information 617 */ 618 rt2800_config_wcid_attr(rt2x00dev, crypto, key); 619 620 return 0; 621} 622EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 623 624void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 625 const unsigned int filter_flags) 626{ 627 u32 reg; 628 629 /* 630 * Start configuration steps. 631 * Note that the version error will always be dropped 632 * and broadcast frames will always be accepted since 633 * there is no filter for it at this time. 634 */ 635 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg); 636 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR, 637 !(filter_flags & FIF_FCSFAIL)); 638 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR, 639 !(filter_flags & FIF_PLCPFAIL)); 640 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME, 641 !(filter_flags & FIF_PROMISC_IN_BSS)); 642 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 643 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1); 644 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST, 645 !(filter_flags & FIF_ALLMULTI)); 646 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0); 647 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1); 648 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK, 649 !(filter_flags & FIF_CONTROL)); 650 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END, 651 !(filter_flags & FIF_CONTROL)); 652 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK, 653 !(filter_flags & FIF_CONTROL)); 654 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS, 655 !(filter_flags & FIF_CONTROL)); 656 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS, 657 !(filter_flags & FIF_CONTROL)); 658 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL, 659 !(filter_flags & FIF_PSPOLL)); 660 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1); 661 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0); 662 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL, 663 !(filter_flags & FIF_CONTROL)); 664 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 665} 666EXPORT_SYMBOL_GPL(rt2800_config_filter); 667 668void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 669 struct rt2x00intf_conf *conf, const unsigned int flags) 670{ 671 unsigned int beacon_base; 672 u32 reg; 673 674 if (flags & CONFIG_UPDATE_TYPE) { 675 /* 676 * Clear current synchronisation setup. 677 * For the Beacon base registers we only need to clear 678 * the first byte since that byte contains the VALID and OWNER 679 * bits which (when set to 0) will invalidate the entire beacon. 680 */ 681 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); 682 rt2800_register_write(rt2x00dev, beacon_base, 0); 683 684 /* 685 * Enable synchronisation. 686 */ 687 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 688 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); 689 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync); 690 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 691 (conf->sync == TSF_SYNC_BEACON)); 692 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 693 } 694 695 if (flags & CONFIG_UPDATE_MAC) { 696 reg = le32_to_cpu(conf->mac[1]); 697 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 698 conf->mac[1] = cpu_to_le32(reg); 699 700 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 701 conf->mac, sizeof(conf->mac)); 702 } 703 704 if (flags & CONFIG_UPDATE_BSSID) { 705 reg = le32_to_cpu(conf->bssid[1]); 706 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0); 707 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 708 conf->bssid[1] = cpu_to_le32(reg); 709 710 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 711 conf->bssid, sizeof(conf->bssid)); 712 } 713} 714EXPORT_SYMBOL_GPL(rt2800_config_intf); 715 716void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp) 717{ 718 u32 reg; 719 720 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); 721 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 722 !!erp->short_preamble); 723 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 724 !!erp->short_preamble); 725 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 726 727 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 728 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 729 erp->cts_protection ? 2 : 0); 730 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 731 732 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 733 erp->basic_rates); 734 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 735 736 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg); 737 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); 738 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 739 740 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg); 741 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs); 742 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 743 744 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 745 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 746 erp->beacon_int * 16); 747 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 748} 749EXPORT_SYMBOL_GPL(rt2800_config_erp); 750 751void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 752{ 753 u8 r1; 754 u8 r3; 755 756 rt2800_bbp_read(rt2x00dev, 1, &r1); 757 rt2800_bbp_read(rt2x00dev, 3, &r3); 758 759 /* 760 * Configure the TX antenna. 761 */ 762 switch ((int)ant->tx) { 763 case 1: 764 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 765 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) 766 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 767 break; 768 case 2: 769 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 770 break; 771 case 3: 772 /* Do nothing */ 773 break; 774 } 775 776 /* 777 * Configure the RX antenna. 778 */ 779 switch ((int)ant->rx) { 780 case 1: 781 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 782 break; 783 case 2: 784 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 785 break; 786 case 3: 787 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 788 break; 789 } 790 791 rt2800_bbp_write(rt2x00dev, 3, r3); 792 rt2800_bbp_write(rt2x00dev, 1, r1); 793} 794EXPORT_SYMBOL_GPL(rt2800_config_ant); 795 796static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 797 struct rt2x00lib_conf *libconf) 798{ 799 u16 eeprom; 800 short lna_gain; 801 802 if (libconf->rf.channel <= 14) { 803 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); 804 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 805 } else if (libconf->rf.channel <= 64) { 806 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); 807 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 808 } else if (libconf->rf.channel <= 128) { 809 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); 810 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1); 811 } else { 812 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); 813 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2); 814 } 815 816 rt2x00dev->lna_gain = lna_gain; 817} 818 819static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 820 struct ieee80211_conf *conf, 821 struct rf_channel *rf, 822 struct channel_info *info) 823{ 824 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 825 826 if (rt2x00dev->default_ant.tx == 1) 827 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 828 829 if (rt2x00dev->default_ant.rx == 1) { 830 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 831 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 832 } else if (rt2x00dev->default_ant.rx == 2) 833 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 834 835 if (rf->channel > 14) { 836 /* 837 * When TX power is below 0, we should increase it by 7 to 838 * make it a positive value (Minumum value is -7). 839 * However this means that values between 0 and 7 have 840 * double meaning, and we should set a 7DBm boost flag. 841 */ 842 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 843 (info->tx_power1 >= 0)); 844 845 if (info->tx_power1 < 0) 846 info->tx_power1 += 7; 847 848 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, 849 TXPOWER_A_TO_DEV(info->tx_power1)); 850 851 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 852 (info->tx_power2 >= 0)); 853 854 if (info->tx_power2 < 0) 855 info->tx_power2 += 7; 856 857 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, 858 TXPOWER_A_TO_DEV(info->tx_power2)); 859 } else { 860 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, 861 TXPOWER_G_TO_DEV(info->tx_power1)); 862 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, 863 TXPOWER_G_TO_DEV(info->tx_power2)); 864 } 865 866 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 867 868 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 869 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 870 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 871 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 872 873 udelay(200); 874 875 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 876 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 877 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 878 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 879 880 udelay(200); 881 882 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 883 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 884 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 885 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 886} 887 888static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 889 struct ieee80211_conf *conf, 890 struct rf_channel *rf, 891 struct channel_info *info) 892{ 893 u8 rfcsr; 894 895 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 896 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 897 898 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 899 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 900 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 901 902 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 903 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 904 TXPOWER_G_TO_DEV(info->tx_power1)); 905 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 906 907 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); 908 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 909 TXPOWER_G_TO_DEV(info->tx_power2)); 910 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 911 912 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); 913 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 914 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 915 916 rt2800_rfcsr_write(rt2x00dev, 24, 917 rt2x00dev->calibration[conf_is_ht40(conf)]); 918 919 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 920 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 921 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 922} 923 924static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 925 struct ieee80211_conf *conf, 926 struct rf_channel *rf, 927 struct channel_info *info) 928{ 929 u32 reg; 930 unsigned int tx_pin; 931 u8 bbp; 932 933 if (rt2x00_rf(rt2x00dev, RF2020) || 934 rt2x00_rf(rt2x00dev, RF3020) || 935 rt2x00_rf(rt2x00dev, RF3021) || 936 rt2x00_rf(rt2x00dev, RF3022)) 937 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 938 else 939 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 940 941 /* 942 * Change BBP settings 943 */ 944 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 945 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 946 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 947 rt2800_bbp_write(rt2x00dev, 86, 0); 948 949 if (rf->channel <= 14) { 950 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { 951 rt2800_bbp_write(rt2x00dev, 82, 0x62); 952 rt2800_bbp_write(rt2x00dev, 75, 0x46); 953 } else { 954 rt2800_bbp_write(rt2x00dev, 82, 0x84); 955 rt2800_bbp_write(rt2x00dev, 75, 0x50); 956 } 957 } else { 958 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 959 960 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) 961 rt2800_bbp_write(rt2x00dev, 75, 0x46); 962 else 963 rt2800_bbp_write(rt2x00dev, 75, 0x50); 964 } 965 966 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg); 967 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 968 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14); 969 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14); 970 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 971 972 tx_pin = 0; 973 974 /* Turn on unused PA or LNA when not using 1T or 1R */ 975 if (rt2x00dev->default_ant.tx != 1) { 976 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 977 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 978 } 979 980 /* Turn on unused PA or LNA when not using 1T or 1R */ 981 if (rt2x00dev->default_ant.rx != 1) { 982 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 983 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 984 } 985 986 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 987 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 988 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 989 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 990 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14); 991 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14); 992 993 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 994 995 rt2800_bbp_read(rt2x00dev, 4, &bbp); 996 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 997 rt2800_bbp_write(rt2x00dev, 4, bbp); 998 999 rt2800_bbp_read(rt2x00dev, 3, &bbp); 1000 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 1001 rt2800_bbp_write(rt2x00dev, 3, bbp); 1002 1003 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 1004 if (conf_is_ht40(conf)) { 1005 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 1006 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 1007 rt2800_bbp_write(rt2x00dev, 73, 0x16); 1008 } else { 1009 rt2800_bbp_write(rt2x00dev, 69, 0x16); 1010 rt2800_bbp_write(rt2x00dev, 70, 0x08); 1011 rt2800_bbp_write(rt2x00dev, 73, 0x11); 1012 } 1013 } 1014 1015 msleep(1); 1016} 1017 1018static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 1019 const int txpower) 1020{ 1021 u32 reg; 1022 u32 value = TXPOWER_G_TO_DEV(txpower); 1023 u8 r1; 1024 1025 rt2800_bbp_read(rt2x00dev, 1, &r1); 1026 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0); 1027 rt2800_bbp_write(rt2x00dev, 1, r1); 1028 1029 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg); 1030 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value); 1031 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value); 1032 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value); 1033 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value); 1034 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value); 1035 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value); 1036 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value); 1037 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value); 1038 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg); 1039 1040 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg); 1041 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value); 1042 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value); 1043 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value); 1044 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value); 1045 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value); 1046 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value); 1047 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value); 1048 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value); 1049 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg); 1050 1051 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg); 1052 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value); 1053 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value); 1054 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value); 1055 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value); 1056 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value); 1057 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value); 1058 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value); 1059 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value); 1060 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg); 1061 1062 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg); 1063 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value); 1064 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value); 1065 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value); 1066 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value); 1067 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value); 1068 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value); 1069 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value); 1070 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value); 1071 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg); 1072 1073 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg); 1074 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value); 1075 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value); 1076 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value); 1077 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value); 1078 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg); 1079} 1080 1081static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 1082 struct rt2x00lib_conf *libconf) 1083{ 1084 u32 reg; 1085 1086 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg); 1087 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 1088 libconf->conf->short_frame_max_tx_count); 1089 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 1090 libconf->conf->long_frame_max_tx_count); 1091 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 1092} 1093 1094static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 1095 struct rt2x00lib_conf *libconf) 1096{ 1097 enum dev_state state = 1098 (libconf->conf->flags & IEEE80211_CONF_PS) ? 1099 STATE_SLEEP : STATE_AWAKE; 1100 u32 reg; 1101 1102 if (state == STATE_SLEEP) { 1103 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 1104 1105 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg); 1106 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 1107 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 1108 libconf->conf->listen_interval - 1); 1109 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1); 1110 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 1111 1112 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 1113 } else { 1114 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg); 1115 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 1116 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 1117 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0); 1118 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 1119 1120 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 1121 } 1122} 1123 1124void rt2800_config(struct rt2x00_dev *rt2x00dev, 1125 struct rt2x00lib_conf *libconf, 1126 const unsigned int flags) 1127{ 1128 /* Always recalculate LNA gain before changing configuration */ 1129 rt2800_config_lna_gain(rt2x00dev, libconf); 1130 1131 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) 1132 rt2800_config_channel(rt2x00dev, libconf->conf, 1133 &libconf->rf, &libconf->channel); 1134 if (flags & IEEE80211_CONF_CHANGE_POWER) 1135 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level); 1136 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 1137 rt2800_config_retry_limit(rt2x00dev, libconf); 1138 if (flags & IEEE80211_CONF_CHANGE_PS) 1139 rt2800_config_ps(rt2x00dev, libconf); 1140} 1141EXPORT_SYMBOL_GPL(rt2800_config); 1142 1143/* 1144 * Link tuning 1145 */ 1146void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 1147{ 1148 u32 reg; 1149 1150 /* 1151 * Update FCS error count from register. 1152 */ 1153 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg); 1154 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 1155} 1156EXPORT_SYMBOL_GPL(rt2800_link_stats); 1157 1158static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 1159{ 1160 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { 1161 if (rt2x00_rt(rt2x00dev, RT3070) || 1162 rt2x00_rt(rt2x00dev, RT3071) || 1163 rt2x00_rt(rt2x00dev, RT3090) || 1164 rt2x00_rt(rt2x00dev, RT3390)) 1165 return 0x1c + (2 * rt2x00dev->lna_gain); 1166 else 1167 return 0x2e + rt2x00dev->lna_gain; 1168 } 1169 1170 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 1171 return 0x32 + (rt2x00dev->lna_gain * 5) / 3; 1172 else 1173 return 0x3a + (rt2x00dev->lna_gain * 5) / 3; 1174} 1175 1176static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 1177 struct link_qual *qual, u8 vgc_level) 1178{ 1179 if (qual->vgc_level != vgc_level) { 1180 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 1181 qual->vgc_level = vgc_level; 1182 qual->vgc_level_reg = vgc_level; 1183 } 1184} 1185 1186void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 1187{ 1188 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 1189} 1190EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 1191 1192void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 1193 const u32 count) 1194{ 1195 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 1196 return; 1197 1198 /* 1199 * When RSSI is better then -80 increase VGC level with 0x10 1200 */ 1201 rt2800_set_vgc(rt2x00dev, qual, 1202 rt2800_get_default_vgc(rt2x00dev) + 1203 ((qual->rssi > -80) * 0x10)); 1204} 1205EXPORT_SYMBOL_GPL(rt2800_link_tuner); 1206 1207/* 1208 * Initialization functions. 1209 */ 1210int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 1211{ 1212 u32 reg; 1213 u16 eeprom; 1214 unsigned int i; 1215 1216 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 1217 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 1218 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 1219 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 1220 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 1221 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 1222 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 1223 1224 if (rt2x00_is_usb(rt2x00dev)) { 1225 /* 1226 * Wait until BBP and RF are ready. 1227 */ 1228 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1229 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); 1230 if (reg && reg != ~0) 1231 break; 1232 msleep(1); 1233 } 1234 1235 if (i == REGISTER_BUSY_COUNT) { 1236 ERROR(rt2x00dev, "Unstable hardware.\n"); 1237 return -EBUSY; 1238 } 1239 1240 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 1241 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 1242 reg & ~0x00002000); 1243 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) { 1244 /* 1245 * Reset DMA indexes 1246 */ 1247 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 1248 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 1249 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 1250 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 1251 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1); 1252 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 1253 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 1254 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 1255 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 1256 1257 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 1258 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 1259 1260 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 1261 } 1262 1263 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 1264 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 1265 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1); 1266 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 1267 1268 if (rt2x00_is_usb(rt2x00dev)) { 1269 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000); 1270#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE) 1271 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, 1272 USB_MODE_RESET, REGISTER_TIMEOUT); 1273#endif 1274 } 1275 1276 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 1277 1278 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg); 1279 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */ 1280 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */ 1281 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */ 1282 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */ 1283 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg); 1284 1285 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg); 1286 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */ 1287 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */ 1288 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */ 1289 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */ 1290 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg); 1291 1292 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 1293 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 1294 1295 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 1296 1297 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 1298 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0); 1299 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0); 1300 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0); 1301 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0); 1302 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 1303 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 1304 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1305 1306 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 1307 1308 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg); 1309 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9); 1310 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 1311 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 1312 1313 if (rt2x00_rt(rt2x00dev, RT3071) || 1314 rt2x00_rt(rt2x00dev, RT3090) || 1315 rt2x00_rt(rt2x00dev, RT3390)) { 1316 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 1317 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 1318 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 1319 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 1320 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 1321 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 1322 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST)) 1323 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 1324 0x0000002c); 1325 else 1326 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 1327 0x0000000f); 1328 } else { 1329 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 1330 } 1331 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg); 1332 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 1333 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 1334 1335 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 1336 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 1337 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 1338 } else { 1339 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 1340 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 1341 } 1342 } else { 1343 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 1344 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 1345 } 1346 1347 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg); 1348 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 1349 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0); 1350 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 1351 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0); 1352 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0); 1353 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1); 1354 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0); 1355 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0); 1356 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 1357 1358 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg); 1359 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 1360 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 1361 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 1362 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 1363 1364 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg); 1365 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 1366 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 1367 rt2x00_rt(rt2x00dev, RT2883) || 1368 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) 1369 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2); 1370 else 1371 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1); 1372 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0); 1373 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0); 1374 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1375 1376 rt2800_register_read(rt2x00dev, LED_CFG, &reg); 1377 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70); 1378 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30); 1379 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3); 1380 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3); 1381 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3); 1382 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3); 1383 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1); 1384 rt2800_register_write(rt2x00dev, LED_CFG, reg); 1385 1386 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 1387 1388 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg); 1389 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); 1390 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31); 1391 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000); 1392 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 1393 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0); 1394 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 1395 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 1396 1397 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); 1398 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1); 1399 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 1400 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0); 1401 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0); 1402 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1); 1403 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 1404 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 1405 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 1406 1407 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg); 1408 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3); 1409 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0); 1410 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1); 1411 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1412 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1413 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1414 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1415 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1416 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1417 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1); 1418 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 1419 1420 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 1421 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3); 1422 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0); 1423 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1); 1424 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1425 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1426 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1427 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1428 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1429 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1430 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1); 1431 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 1432 1433 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg); 1434 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 1435 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0); 1436 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1); 1437 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1438 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1439 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1440 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1441 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1442 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1443 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0); 1444 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1445 1446 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg); 1447 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 1448 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1449 !rt2x00_is_usb(rt2x00dev)); 1450 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1); 1451 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1452 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1453 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1454 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1455 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1456 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1457 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0); 1458 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1459 1460 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg); 1461 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 1462 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0); 1463 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1); 1464 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1465 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1466 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1467 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1468 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1469 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1470 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0); 1471 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1472 1473 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg); 1474 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 1475 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0); 1476 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1); 1477 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1478 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1479 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1480 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1481 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1482 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1483 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0); 1484 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 1485 1486 if (rt2x00_is_usb(rt2x00dev)) { 1487 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 1488 1489 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 1490 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 1491 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 1492 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 1493 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 1494 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 1495 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 1496 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 1497 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 1498 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 1499 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 1500 } 1501 1502 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f); 1503 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002); 1504 1505 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg); 1506 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); 1507 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, 1508 IEEE80211_MAX_RTS_THRESHOLD); 1509 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0); 1510 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 1511 1512 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 1513 1514 /* 1515 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 1516 * time should be set to 16. However, the original Ralink driver uses 1517 * 16 for both and indeed using a value of 10 for CCK SIFS results in 1518 * connection problems with 11g + CTS protection. Hence, use the same 1519 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 1520 */ 1521 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg); 1522 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 1523 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 1524 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 1525 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314); 1526 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 1527 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 1528 1529 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 1530 1531 /* 1532 * ASIC will keep garbage value after boot, clear encryption keys. 1533 */ 1534 for (i = 0; i < 4; i++) 1535 rt2800_register_write(rt2x00dev, 1536 SHARED_KEY_MODE_ENTRY(i), 0); 1537 1538 for (i = 0; i < 256; i++) { 1539 u32 wcid[2] = { 0xffffffff, 0x00ffffff }; 1540 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i), 1541 wcid, sizeof(wcid)); 1542 1543 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1); 1544 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 1545 } 1546 1547 /* 1548 * Clear all beacons 1549 * For the Beacon base registers we only need to clear 1550 * the first byte since that byte contains the VALID and OWNER 1551 * bits which (when set to 0) will invalidate the entire beacon. 1552 */ 1553 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0); 1554 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0); 1555 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0); 1556 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0); 1557 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0); 1558 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0); 1559 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0); 1560 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0); 1561 1562 if (rt2x00_is_usb(rt2x00dev)) { 1563 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg); 1564 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30); 1565 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg); 1566 } 1567 1568 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg); 1569 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0); 1570 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0); 1571 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1); 1572 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2); 1573 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3); 1574 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4); 1575 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5); 1576 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6); 1577 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 1578 1579 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg); 1580 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8); 1581 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8); 1582 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9); 1583 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10); 1584 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11); 1585 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12); 1586 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13); 1587 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14); 1588 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 1589 1590 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg); 1591 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8); 1592 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8); 1593 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9); 1594 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10); 1595 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11); 1596 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12); 1597 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13); 1598 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14); 1599 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 1600 1601 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg); 1602 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0); 1603 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0); 1604 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1); 1605 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2); 1606 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 1607 1608 /* 1609 * We must clear the error counters. 1610 * These registers are cleared on read, 1611 * so we may pass a useless variable to store the value. 1612 */ 1613 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg); 1614 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg); 1615 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg); 1616 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg); 1617 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg); 1618 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg); 1619 1620 return 0; 1621} 1622EXPORT_SYMBOL_GPL(rt2800_init_registers); 1623 1624static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 1625{ 1626 unsigned int i; 1627 u32 reg; 1628 1629 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1630 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg); 1631 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 1632 return 0; 1633 1634 udelay(REGISTER_BUSY_DELAY); 1635 } 1636 1637 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n"); 1638 return -EACCES; 1639} 1640 1641static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 1642{ 1643 unsigned int i; 1644 u8 value; 1645 1646 /* 1647 * BBP was enabled after firmware was loaded, 1648 * but we need to reactivate it now. 1649 */ 1650 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 1651 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 1652 msleep(1); 1653 1654 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1655 rt2800_bbp_read(rt2x00dev, 0, &value); 1656 if ((value != 0xff) && (value != 0x00)) 1657 return 0; 1658 udelay(REGISTER_BUSY_DELAY); 1659 } 1660 1661 ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); 1662 return -EACCES; 1663} 1664 1665int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 1666{ 1667 unsigned int i; 1668 u16 eeprom; 1669 u8 reg_id; 1670 u8 value; 1671 1672 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) || 1673 rt2800_wait_bbp_ready(rt2x00dev))) 1674 return -EACCES; 1675 1676 if (rt2800_is_305x_soc(rt2x00dev)) 1677 rt2800_bbp_write(rt2x00dev, 31, 0x08); 1678 1679 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 1680 rt2800_bbp_write(rt2x00dev, 66, 0x38); 1681 1682 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 1683 rt2800_bbp_write(rt2x00dev, 69, 0x16); 1684 rt2800_bbp_write(rt2x00dev, 73, 0x12); 1685 } else { 1686 rt2800_bbp_write(rt2x00dev, 69, 0x12); 1687 rt2800_bbp_write(rt2x00dev, 73, 0x10); 1688 } 1689 1690 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 1691 1692 if (rt2x00_rt(rt2x00dev, RT3070) || 1693 rt2x00_rt(rt2x00dev, RT3071) || 1694 rt2x00_rt(rt2x00dev, RT3090) || 1695 rt2x00_rt(rt2x00dev, RT3390)) { 1696 rt2800_bbp_write(rt2x00dev, 79, 0x13); 1697 rt2800_bbp_write(rt2x00dev, 80, 0x05); 1698 rt2800_bbp_write(rt2x00dev, 81, 0x33); 1699 } else if (rt2800_is_305x_soc(rt2x00dev)) { 1700 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 1701 rt2800_bbp_write(rt2x00dev, 80, 0x08); 1702 } else { 1703 rt2800_bbp_write(rt2x00dev, 81, 0x37); 1704 } 1705 1706 rt2800_bbp_write(rt2x00dev, 82, 0x62); 1707 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 1708 1709 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) || 1710 rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D)) 1711 rt2800_bbp_write(rt2x00dev, 84, 0x19); 1712 else 1713 rt2800_bbp_write(rt2x00dev, 84, 0x99); 1714 1715 rt2800_bbp_write(rt2x00dev, 86, 0x00); 1716 rt2800_bbp_write(rt2x00dev, 91, 0x04); 1717 rt2800_bbp_write(rt2x00dev, 92, 0x00); 1718 1719 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 1720 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 1721 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || 1722 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || 1723 rt2800_is_305x_soc(rt2x00dev)) 1724 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 1725 else 1726 rt2800_bbp_write(rt2x00dev, 103, 0x00); 1727 1728 if (rt2800_is_305x_soc(rt2x00dev)) 1729 rt2800_bbp_write(rt2x00dev, 105, 0x01); 1730 else 1731 rt2800_bbp_write(rt2x00dev, 105, 0x05); 1732 rt2800_bbp_write(rt2x00dev, 106, 0x35); 1733 1734 if (rt2x00_rt(rt2x00dev, RT3071) || 1735 rt2x00_rt(rt2x00dev, RT3090) || 1736 rt2x00_rt(rt2x00dev, RT3390)) { 1737 rt2800_bbp_read(rt2x00dev, 138, &value); 1738 1739 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 1740 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) 1741 value |= 0x20; 1742 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) 1743 value &= ~0x02; 1744 1745 rt2800_bbp_write(rt2x00dev, 138, value); 1746 } 1747 1748 1749 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 1750 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 1751 1752 if (eeprom != 0xffff && eeprom != 0x0000) { 1753 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 1754 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 1755 rt2800_bbp_write(rt2x00dev, reg_id, value); 1756 } 1757 } 1758 1759 return 0; 1760} 1761EXPORT_SYMBOL_GPL(rt2800_init_bbp); 1762 1763static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, 1764 bool bw40, u8 rfcsr24, u8 filter_target) 1765{ 1766 unsigned int i; 1767 u8 bbp; 1768 u8 rfcsr; 1769 u8 passband; 1770 u8 stopband; 1771 u8 overtuned = 0; 1772 1773 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 1774 1775 rt2800_bbp_read(rt2x00dev, 4, &bbp); 1776 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 1777 rt2800_bbp_write(rt2x00dev, 4, bbp); 1778 1779 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 1780 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 1781 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 1782 1783 /* 1784 * Set power & frequency of passband test tone 1785 */ 1786 rt2800_bbp_write(rt2x00dev, 24, 0); 1787 1788 for (i = 0; i < 100; i++) { 1789 rt2800_bbp_write(rt2x00dev, 25, 0x90); 1790 msleep(1); 1791 1792 rt2800_bbp_read(rt2x00dev, 55, &passband); 1793 if (passband) 1794 break; 1795 } 1796 1797 /* 1798 * Set power & frequency of stopband test tone 1799 */ 1800 rt2800_bbp_write(rt2x00dev, 24, 0x06); 1801 1802 for (i = 0; i < 100; i++) { 1803 rt2800_bbp_write(rt2x00dev, 25, 0x90); 1804 msleep(1); 1805 1806 rt2800_bbp_read(rt2x00dev, 55, &stopband); 1807 1808 if ((passband - stopband) <= filter_target) { 1809 rfcsr24++; 1810 overtuned += ((passband - stopband) == filter_target); 1811 } else 1812 break; 1813 1814 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 1815 } 1816 1817 rfcsr24 -= !!overtuned; 1818 1819 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 1820 return rfcsr24; 1821} 1822 1823int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 1824{ 1825 u8 rfcsr; 1826 u8 bbp; 1827 u32 reg; 1828 u16 eeprom; 1829 1830 if (!rt2x00_rt(rt2x00dev, RT3070) && 1831 !rt2x00_rt(rt2x00dev, RT3071) && 1832 !rt2x00_rt(rt2x00dev, RT3090) && 1833 !rt2x00_rt(rt2x00dev, RT3390) && 1834 !rt2800_is_305x_soc(rt2x00dev)) 1835 return 0; 1836 1837 /* 1838 * Init RF calibration. 1839 */ 1840 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 1841 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 1842 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 1843 msleep(1); 1844 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 1845 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 1846 1847 if (rt2x00_rt(rt2x00dev, RT3070) || 1848 rt2x00_rt(rt2x00dev, RT3071) || 1849 rt2x00_rt(rt2x00dev, RT3090)) { 1850 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1851 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1852 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 1853 rt2800_rfcsr_write(rt2x00dev, 7, 0x70); 1854 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 1855 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 1856 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 1857 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 1858 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 1859 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 1860 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 1861 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 1862 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 1863 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 1864 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 1865 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 1866 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 1867 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 1868 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 1869 } else if (rt2x00_rt(rt2x00dev, RT3390)) { 1870 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 1871 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 1872 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 1873 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 1874 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1875 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 1876 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 1877 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 1878 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 1879 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 1880 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 1881 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 1882 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 1883 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 1884 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 1885 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 1886 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 1887 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 1888 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 1889 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 1890 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 1891 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 1892 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 1893 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 1894 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 1895 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 1896 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 1897 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 1898 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 1899 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 1900 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 1901 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 1902 } else if (rt2800_is_305x_soc(rt2x00dev)) { 1903 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 1904 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 1905 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 1906 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 1907 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1908 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1909 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 1910 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 1911 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 1912 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 1913 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 1914 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 1915 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 1916 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 1917 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 1918 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 1919 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 1920 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 1921 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 1922 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 1923 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 1924 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 1925 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 1926 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 1927 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 1928 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 1929 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 1930 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 1931 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 1932 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 1933 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 1934 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 1935 return 0; 1936 } 1937 1938 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 1939 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); 1940 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1); 1941 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3); 1942 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 1943 } else if (rt2x00_rt(rt2x00dev, RT3071) || 1944 rt2x00_rt(rt2x00dev, RT3090)) { 1945 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 1946 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 1947 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 1948 1949 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 1950 1951 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); 1952 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1); 1953 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 1954 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 1955 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 1956 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST)) 1957 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3); 1958 else 1959 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0); 1960 } 1961 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 1962 } else if (rt2x00_rt(rt2x00dev, RT3390)) { 1963 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg); 1964 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0); 1965 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 1966 } 1967 1968 /* 1969 * Set RX Filter calibration for 20MHz and 40MHz 1970 */ 1971 if (rt2x00_rt(rt2x00dev, RT3070)) { 1972 rt2x00dev->calibration[0] = 1973 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16); 1974 rt2x00dev->calibration[1] = 1975 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); 1976 } else if (rt2x00_rt(rt2x00dev, RT3071) || 1977 rt2x00_rt(rt2x00dev, RT3090) || 1978 rt2x00_rt(rt2x00dev, RT3390)) { 1979 rt2x00dev->calibration[0] = 1980 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13); 1981 rt2x00dev->calibration[1] = 1982 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15); 1983 } 1984 1985 /* 1986 * Set back to initial state 1987 */ 1988 rt2800_bbp_write(rt2x00dev, 24, 0); 1989 1990 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 1991 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 1992 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 1993 1994 /* 1995 * set BBP back to BW20 1996 */ 1997 rt2800_bbp_read(rt2x00dev, 4, &bbp); 1998 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 1999 rt2800_bbp_write(rt2x00dev, 4, bbp); 2000 2001 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 2002 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 2003 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 2004 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 2005 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 2006 2007 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg); 2008 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1); 2009 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 2010 2011 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 2012 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 2013 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 2014 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 2015 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 2016 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 2017 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) 2018 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 2019 } 2020 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom); 2021 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1) 2022 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 2023 rt2x00_get_field16(eeprom, 2024 EEPROM_TXMIXER_GAIN_BG_VAL)); 2025 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2026 2027 if (rt2x00_rt(rt2x00dev, RT3090)) { 2028 rt2800_bbp_read(rt2x00dev, 138, &bbp); 2029 2030 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 2031 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) 2032 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 2033 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) 2034 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 2035 2036 rt2800_bbp_write(rt2x00dev, 138, bbp); 2037 } 2038 2039 if (rt2x00_rt(rt2x00dev, RT3071) || 2040 rt2x00_rt(rt2x00dev, RT3090) || 2041 rt2x00_rt(rt2x00dev, RT3390)) { 2042 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2043 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2044 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2045 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2046 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2047 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2048 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2049 2050 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr); 2051 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 2052 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 2053 2054 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr); 2055 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 2056 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 2057 2058 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr); 2059 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 2060 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 2061 } 2062 2063 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) { 2064 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr); 2065 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 2066 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E)) 2067 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 2068 else 2069 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 2070 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 2071 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 2072 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 2073 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 2074 } 2075 2076 return 0; 2077} 2078EXPORT_SYMBOL_GPL(rt2800_init_rfcsr); 2079 2080int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 2081{ 2082 u32 reg; 2083 2084 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg); 2085 2086 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 2087} 2088EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 2089 2090static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 2091{ 2092 u32 reg; 2093 2094 mutex_lock(&rt2x00dev->csr_mutex); 2095 2096 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg); 2097 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i); 2098 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0); 2099 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1); 2100 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg); 2101 2102 /* Wait until the EEPROM has been loaded */ 2103 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg); 2104 2105 /* Apparently the data is read from end to start */ 2106 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, 2107 (u32 *)&rt2x00dev->eeprom[i]); 2108 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, 2109 (u32 *)&rt2x00dev->eeprom[i + 2]); 2110 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, 2111 (u32 *)&rt2x00dev->eeprom[i + 4]); 2112 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, 2113 (u32 *)&rt2x00dev->eeprom[i + 6]); 2114 2115 mutex_unlock(&rt2x00dev->csr_mutex); 2116} 2117 2118void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 2119{ 2120 unsigned int i; 2121 2122 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 2123 rt2800_efuse_read(rt2x00dev, i); 2124} 2125EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 2126 2127int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 2128{ 2129 u16 word; 2130 u8 *mac; 2131 u8 default_lna_gain; 2132 2133 /* 2134 * Start validation of the data that has been read. 2135 */ 2136 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 2137 if (!is_valid_ether_addr(mac)) { 2138 random_ether_addr(mac); 2139 EEPROM(rt2x00dev, "MAC: %pM\n", mac); 2140 } 2141 2142 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); 2143 if (word == 0xffff) { 2144 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2); 2145 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1); 2146 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820); 2147 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); 2148 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); 2149 } else if (rt2x00_rt(rt2x00dev, RT2860) || 2150 rt2x00_rt(rt2x00dev, RT2870) || 2151 rt2x00_rt(rt2x00dev, RT2872)) { 2152 /* 2153 * There is a max of 2 RX streams for RT28x0 series 2154 */ 2155 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2) 2156 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2); 2157 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); 2158 } 2159 2160 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); 2161 if (word == 0xffff) { 2162 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0); 2163 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0); 2164 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0); 2165 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0); 2166 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); 2167 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0); 2168 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0); 2169 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0); 2170 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0); 2171 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0); 2172 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); 2173 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); 2174 } 2175 2176 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); 2177 if ((word & 0x00ff) == 0x00ff) { 2178 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 2179 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 2180 LED_MODE_TXRX_ACTIVITY); 2181 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 2182 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 2183 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555); 2184 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221); 2185 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8); 2186 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); 2187 } 2188 2189 /* 2190 * During the LNA validation we are going to use 2191 * lna0 as correct value. Note that EEPROM_LNA 2192 * is never validated. 2193 */ 2194 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word); 2195 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 2196 2197 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word); 2198 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 2199 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 2200 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 2201 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 2202 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 2203 2204 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word); 2205 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 2206 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 2207 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 2208 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 2209 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 2210 default_lna_gain); 2211 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 2212 2213 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word); 2214 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 2215 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 2216 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 2217 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 2218 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 2219 2220 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word); 2221 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 2222 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 2223 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 2224 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 2225 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 2226 default_lna_gain); 2227 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 2228 2229 return 0; 2230} 2231EXPORT_SYMBOL_GPL(rt2800_validate_eeprom); 2232 2233int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 2234{ 2235 u32 reg; 2236 u16 value; 2237 u16 eeprom; 2238 2239 /* 2240 * Read EEPROM word for configuration. 2241 */ 2242 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 2243 2244 /* 2245 * Identify RF chipset. 2246 */ 2247 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 2248 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); 2249 2250 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), 2251 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); 2252 2253 if (!rt2x00_rt(rt2x00dev, RT2860) && 2254 !rt2x00_rt(rt2x00dev, RT2870) && 2255 !rt2x00_rt(rt2x00dev, RT2872) && 2256 !rt2x00_rt(rt2x00dev, RT2883) && 2257 !rt2x00_rt(rt2x00dev, RT3070) && 2258 !rt2x00_rt(rt2x00dev, RT3071) && 2259 !rt2x00_rt(rt2x00dev, RT3090) && 2260 !rt2x00_rt(rt2x00dev, RT3390) && 2261 !rt2x00_rt(rt2x00dev, RT3572)) { 2262 ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); 2263 return -ENODEV; 2264 } 2265 2266 if (!rt2x00_rf(rt2x00dev, RF2820) && 2267 !rt2x00_rf(rt2x00dev, RF2850) && 2268 !rt2x00_rf(rt2x00dev, RF2720) && 2269 !rt2x00_rf(rt2x00dev, RF2750) && 2270 !rt2x00_rf(rt2x00dev, RF3020) && 2271 !rt2x00_rf(rt2x00dev, RF2020) && 2272 !rt2x00_rf(rt2x00dev, RF3021) && 2273 !rt2x00_rf(rt2x00dev, RF3022) && 2274 !rt2x00_rf(rt2x00dev, RF3052)) { 2275 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 2276 return -ENODEV; 2277 } 2278 2279 /* 2280 * Identify default antenna configuration. 2281 */ 2282 rt2x00dev->default_ant.tx = 2283 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH); 2284 rt2x00dev->default_ant.rx = 2285 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH); 2286 2287 /* 2288 * Read frequency offset and RF programming sequence. 2289 */ 2290 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 2291 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 2292 2293 /* 2294 * Read external LNA informations. 2295 */ 2296 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 2297 2298 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) 2299 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); 2300 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) 2301 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); 2302 2303 /* 2304 * Detect if this device has an hardware controlled radio. 2305 */ 2306 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO)) 2307 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); 2308 2309 /* 2310 * Store led settings, for correct led behaviour. 2311 */ 2312#ifdef CONFIG_RT2X00_LIB_LEDS 2313 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 2314 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 2315 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 2316 2317 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg); 2318#endif /* CONFIG_RT2X00_LIB_LEDS */ 2319 2320 return 0; 2321} 2322EXPORT_SYMBOL_GPL(rt2800_init_eeprom); 2323 2324/* 2325 * RF value list for rt28xx 2326 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 2327 */ 2328static const struct rf_channel rf_vals[] = { 2329 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 2330 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 2331 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 2332 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 2333 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 2334 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 2335 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 2336 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 2337 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 2338 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 2339 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 2340 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 2341 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 2342 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 2343 2344 /* 802.11 UNI / HyperLan 2 */ 2345 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 2346 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 2347 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 2348 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 2349 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 2350 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 2351 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 2352 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 2353 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 2354 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 2355 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 2356 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 2357 2358 /* 802.11 HyperLan 2 */ 2359 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 2360 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 2361 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 2362 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 2363 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 2364 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 2365 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 2366 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 2367 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 2368 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 2369 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 2370 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 2371 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 2372 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 2373 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 2374 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 2375 2376 /* 802.11 UNII */ 2377 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 2378 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 2379 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 2380 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 2381 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 2382 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 2383 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 2384 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 2385 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 2386 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 2387 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 2388 2389 /* 802.11 Japan */ 2390 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 2391 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 2392 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 2393 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 2394 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 2395 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 2396 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 2397}; 2398 2399/* 2400 * RF value list for rt3xxx 2401 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052) 2402 */ 2403static const struct rf_channel rf_vals_3x[] = { 2404 {1, 241, 2, 2 }, 2405 {2, 241, 2, 7 }, 2406 {3, 242, 2, 2 }, 2407 {4, 242, 2, 7 }, 2408 {5, 243, 2, 2 }, 2409 {6, 243, 2, 7 }, 2410 {7, 244, 2, 2 }, 2411 {8, 244, 2, 7 }, 2412 {9, 245, 2, 2 }, 2413 {10, 245, 2, 7 }, 2414 {11, 246, 2, 2 }, 2415 {12, 246, 2, 7 }, 2416 {13, 247, 2, 2 }, 2417 {14, 248, 2, 4 }, 2418 2419 /* 802.11 UNI / HyperLan 2 */ 2420 {36, 0x56, 0, 4}, 2421 {38, 0x56, 0, 6}, 2422 {40, 0x56, 0, 8}, 2423 {44, 0x57, 0, 0}, 2424 {46, 0x57, 0, 2}, 2425 {48, 0x57, 0, 4}, 2426 {52, 0x57, 0, 8}, 2427 {54, 0x57, 0, 10}, 2428 {56, 0x58, 0, 0}, 2429 {60, 0x58, 0, 4}, 2430 {62, 0x58, 0, 6}, 2431 {64, 0x58, 0, 8}, 2432 2433 /* 802.11 HyperLan 2 */ 2434 {100, 0x5b, 0, 8}, 2435 {102, 0x5b, 0, 10}, 2436 {104, 0x5c, 0, 0}, 2437 {108, 0x5c, 0, 4}, 2438 {110, 0x5c, 0, 6}, 2439 {112, 0x5c, 0, 8}, 2440 {116, 0x5d, 0, 0}, 2441 {118, 0x5d, 0, 2}, 2442 {120, 0x5d, 0, 4}, 2443 {124, 0x5d, 0, 8}, 2444 {126, 0x5d, 0, 10}, 2445 {128, 0x5e, 0, 0}, 2446 {132, 0x5e, 0, 4}, 2447 {134, 0x5e, 0, 6}, 2448 {136, 0x5e, 0, 8}, 2449 {140, 0x5f, 0, 0}, 2450 2451 /* 802.11 UNII */ 2452 {149, 0x5f, 0, 9}, 2453 {151, 0x5f, 0, 11}, 2454 {153, 0x60, 0, 1}, 2455 {157, 0x60, 0, 5}, 2456 {159, 0x60, 0, 7}, 2457 {161, 0x60, 0, 9}, 2458 {165, 0x61, 0, 1}, 2459 {167, 0x61, 0, 3}, 2460 {169, 0x61, 0, 5}, 2461 {171, 0x61, 0, 7}, 2462 {173, 0x61, 0, 9}, 2463}; 2464 2465int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 2466{ 2467 struct hw_mode_spec *spec = &rt2x00dev->spec; 2468 struct channel_info *info; 2469 char *tx_power1; 2470 char *tx_power2; 2471 unsigned int i; 2472 u16 eeprom; 2473 2474 /* 2475 * Disable powersaving as default on PCI devices. 2476 */ 2477 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) 2478 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 2479 2480 /* 2481 * Initialize all hw fields. 2482 */ 2483 rt2x00dev->hw->flags = 2484 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2485 IEEE80211_HW_SIGNAL_DBM | 2486 IEEE80211_HW_SUPPORTS_PS | 2487 IEEE80211_HW_PS_NULLFUNC_STACK; 2488 2489 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 2490 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 2491 rt2x00_eeprom_addr(rt2x00dev, 2492 EEPROM_MAC_ADDR_0)); 2493 2494 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 2495 2496 /* 2497 * Initialize hw_mode information. 2498 */ 2499 spec->supported_bands = SUPPORT_BAND_2GHZ; 2500 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 2501 2502 if (rt2x00_rf(rt2x00dev, RF2820) || 2503 rt2x00_rf(rt2x00dev, RF2720)) { 2504 spec->num_channels = 14; 2505 spec->channels = rf_vals; 2506 } else if (rt2x00_rf(rt2x00dev, RF2850) || 2507 rt2x00_rf(rt2x00dev, RF2750)) { 2508 spec->supported_bands |= SUPPORT_BAND_5GHZ; 2509 spec->num_channels = ARRAY_SIZE(rf_vals); 2510 spec->channels = rf_vals; 2511 } else if (rt2x00_rf(rt2x00dev, RF3020) || 2512 rt2x00_rf(rt2x00dev, RF2020) || 2513 rt2x00_rf(rt2x00dev, RF3021) || 2514 rt2x00_rf(rt2x00dev, RF3022)) { 2515 spec->num_channels = 14; 2516 spec->channels = rf_vals_3x; 2517 } else if (rt2x00_rf(rt2x00dev, RF3052)) { 2518 spec->supported_bands |= SUPPORT_BAND_5GHZ; 2519 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 2520 spec->channels = rf_vals_3x; 2521 } 2522 2523 /* 2524 * Initialize HT information. 2525 */ 2526 if (!rt2x00_rf(rt2x00dev, RF2020)) 2527 spec->ht.ht_supported = true; 2528 else 2529 spec->ht.ht_supported = false; 2530 2531 /* 2532 * Don't set IEEE80211_HT_CAP_SUP_WIDTH_20_40 for now as it causes 2533 * reception problems with HT40 capable 11n APs 2534 */ 2535 spec->ht.cap = 2536 IEEE80211_HT_CAP_GRN_FLD | 2537 IEEE80211_HT_CAP_SGI_20 | 2538 IEEE80211_HT_CAP_SGI_40 | 2539 IEEE80211_HT_CAP_TX_STBC | 2540 IEEE80211_HT_CAP_RX_STBC; 2541 spec->ht.ampdu_factor = 3; 2542 spec->ht.ampdu_density = 4; 2543 spec->ht.mcs.tx_params = 2544 IEEE80211_HT_MCS_TX_DEFINED | 2545 IEEE80211_HT_MCS_TX_RX_DIFF | 2546 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) << 2547 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 2548 2549 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) { 2550 case 3: 2551 spec->ht.mcs.rx_mask[2] = 0xff; 2552 case 2: 2553 spec->ht.mcs.rx_mask[1] = 0xff; 2554 case 1: 2555 spec->ht.mcs.rx_mask[0] = 0xff; 2556 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 2557 break; 2558 } 2559 2560 /* 2561 * Create channel information array 2562 */ 2563 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); 2564 if (!info) 2565 return -ENOMEM; 2566 2567 spec->channels_info = info; 2568 2569 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 2570 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 2571 2572 for (i = 0; i < 14; i++) { 2573 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]); 2574 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]); 2575 } 2576 2577 if (spec->num_channels > 14) { 2578 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1); 2579 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2); 2580 2581 for (i = 14; i < spec->num_channels; i++) { 2582 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]); 2583 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]); 2584 } 2585 } 2586 2587 return 0; 2588} 2589EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode); 2590 2591/* 2592 * IEEE80211 stack callback functions. 2593 */ 2594static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, 2595 u32 *iv32, u16 *iv16) 2596{ 2597 struct rt2x00_dev *rt2x00dev = hw->priv; 2598 struct mac_iveiv_entry iveiv_entry; 2599 u32 offset; 2600 2601 offset = MAC_IVEIV_ENTRY(hw_key_idx); 2602 rt2800_register_multiread(rt2x00dev, offset, 2603 &iveiv_entry, sizeof(iveiv_entry)); 2604 2605 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16)); 2606 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32)); 2607} 2608 2609static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 2610{ 2611 struct rt2x00_dev *rt2x00dev = hw->priv; 2612 u32 reg; 2613 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 2614 2615 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg); 2616 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value); 2617 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 2618 2619 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg); 2620 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled); 2621 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 2622 2623 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 2624 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled); 2625 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 2626 2627 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg); 2628 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled); 2629 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 2630 2631 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg); 2632 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled); 2633 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 2634 2635 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg); 2636 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled); 2637 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 2638 2639 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg); 2640 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled); 2641 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 2642 2643 return 0; 2644} 2645 2646static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, 2647 const struct ieee80211_tx_queue_params *params) 2648{ 2649 struct rt2x00_dev *rt2x00dev = hw->priv; 2650 struct data_queue *queue; 2651 struct rt2x00_field32 field; 2652 int retval; 2653 u32 reg; 2654 u32 offset; 2655 2656 /* 2657 * First pass the configuration through rt2x00lib, that will 2658 * update the queue settings and validate the input. After that 2659 * we are free to update the registers based on the value 2660 * in the queue parameter. 2661 */ 2662 retval = rt2x00mac_conf_tx(hw, queue_idx, params); 2663 if (retval) 2664 return retval; 2665 2666 /* 2667 * We only need to perform additional register initialization 2668 * for WMM queues/ 2669 */ 2670 if (queue_idx >= 4) 2671 return 0; 2672 2673 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 2674 2675 /* Update WMM TXOP register */ 2676 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 2677 field.bit_offset = (queue_idx & 1) * 16; 2678 field.bit_mask = 0xffff << field.bit_offset; 2679 2680 rt2800_register_read(rt2x00dev, offset, &reg); 2681 rt2x00_set_field32(&reg, field, queue->txop); 2682 rt2800_register_write(rt2x00dev, offset, reg); 2683 2684 /* Update WMM registers */ 2685 field.bit_offset = queue_idx * 4; 2686 field.bit_mask = 0xf << field.bit_offset; 2687 2688 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg); 2689 rt2x00_set_field32(&reg, field, queue->aifs); 2690 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 2691 2692 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg); 2693 rt2x00_set_field32(&reg, field, queue->cw_min); 2694 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 2695 2696 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg); 2697 rt2x00_set_field32(&reg, field, queue->cw_max); 2698 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 2699 2700 /* Update EDCA registers */ 2701 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 2702 2703 rt2800_register_read(rt2x00dev, offset, &reg); 2704 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop); 2705 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs); 2706 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min); 2707 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max); 2708 rt2800_register_write(rt2x00dev, offset, reg); 2709 2710 return 0; 2711} 2712 2713static u64 rt2800_get_tsf(struct ieee80211_hw *hw) 2714{ 2715 struct rt2x00_dev *rt2x00dev = hw->priv; 2716 u64 tsf; 2717 u32 reg; 2718 2719 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg); 2720 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 2721 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg); 2722 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 2723 2724 return tsf; 2725} 2726 2727const struct ieee80211_ops rt2800_mac80211_ops = { 2728 .tx = rt2x00mac_tx, 2729 .start = rt2x00mac_start, 2730 .stop = rt2x00mac_stop, 2731 .add_interface = rt2x00mac_add_interface, 2732 .remove_interface = rt2x00mac_remove_interface, 2733 .config = rt2x00mac_config, 2734 .configure_filter = rt2x00mac_configure_filter, 2735 .set_tim = rt2x00mac_set_tim, 2736 .set_key = rt2x00mac_set_key, 2737 .get_stats = rt2x00mac_get_stats, 2738 .get_tkip_seq = rt2800_get_tkip_seq, 2739 .set_rts_threshold = rt2800_set_rts_threshold, 2740 .bss_info_changed = rt2x00mac_bss_info_changed, 2741 .conf_tx = rt2800_conf_tx, 2742 .get_tsf = rt2800_get_tsf, 2743 .rfkill_poll = rt2x00mac_rfkill_poll, 2744}; 2745EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);