tjh.dev
Linux kernel mirror (for testing)
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1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
31#include <linux/types.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/aer.h>
35
36#include "ixgbe_type.h"
37#include "ixgbe_common.h"
38#include "ixgbe_dcb.h"
39#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
40#define IXGBE_FCOE
41#include "ixgbe_fcoe.h"
42#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
43#ifdef CONFIG_IXGBE_DCA
44#include <linux/dca.h>
45#endif
46
47#define PFX "ixgbe: "
48#define DPRINTK(nlevel, klevel, fmt, args...) \
49 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
50 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
51 __func__ , ## args)))
52
53/* TX/RX descriptor defines */
54#define IXGBE_DEFAULT_TXD 512
55#define IXGBE_MAX_TXD 4096
56#define IXGBE_MIN_TXD 64
57
58#define IXGBE_DEFAULT_RXD 512
59#define IXGBE_MAX_RXD 4096
60#define IXGBE_MIN_RXD 64
61
62/* flow control */
63#define IXGBE_DEFAULT_FCRTL 0x10000
64#define IXGBE_MIN_FCRTL 0x40
65#define IXGBE_MAX_FCRTL 0x7FF80
66#define IXGBE_DEFAULT_FCRTH 0x20000
67#define IXGBE_MIN_FCRTH 0x600
68#define IXGBE_MAX_FCRTH 0x7FFF0
69#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
70#define IXGBE_MIN_FCPAUSE 0
71#define IXGBE_MAX_FCPAUSE 0xFFFF
72
73/* Supported Rx Buffer Sizes */
74#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
75#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
76#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
77#define IXGBE_RXBUFFER_2048 2048
78#define IXGBE_RXBUFFER_4096 4096
79#define IXGBE_RXBUFFER_8192 8192
80#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
81
82#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
83
84#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
85
86/* How many Rx Buffers do we bundle into one write to the hardware ? */
87#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
88
89#define IXGBE_TX_FLAGS_CSUM (u32)(1)
90#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
91#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
92#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
93#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
94#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
95#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
96#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
97#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
98
99#define IXGBE_MAX_RSC_INT_RATE 162760
100
101#define IXGBE_MAX_VF_MC_ENTRIES 30
102#define IXGBE_MAX_VF_FUNCTIONS 64
103#define IXGBE_MAX_VFTA_ENTRIES 128
104#define MAX_EMULATION_MAC_ADDRS 16
105#define VMDQ_P(p) ((p) + adapter->num_vfs)
106
107struct vf_data_storage {
108 unsigned char vf_mac_addresses[ETH_ALEN];
109 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
110 u16 num_vf_mc_hashes;
111 u16 default_vf_vlan_id;
112 u16 vlans_enabled;
113 bool clear_to_send;
114 bool pf_set_mac;
115 int rar;
116 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
117 u16 pf_qos;
118};
119
120/* wrapper around a pointer to a socket buffer,
121 * so a DMA handle can be stored along with the buffer */
122struct ixgbe_tx_buffer {
123 struct sk_buff *skb;
124 dma_addr_t dma;
125 unsigned long time_stamp;
126 u16 length;
127 u16 next_to_watch;
128 u16 mapped_as_page;
129};
130
131struct ixgbe_rx_buffer {
132 struct sk_buff *skb;
133 dma_addr_t dma;
134 struct page *page;
135 dma_addr_t page_dma;
136 unsigned int page_offset;
137};
138
139struct ixgbe_queue_stats {
140 u64 packets;
141 u64 bytes;
142};
143
144struct ixgbe_ring {
145 void *desc; /* descriptor ring memory */
146 union {
147 struct ixgbe_tx_buffer *tx_buffer_info;
148 struct ixgbe_rx_buffer *rx_buffer_info;
149 };
150 u8 atr_sample_rate;
151 u8 atr_count;
152 u16 count; /* amount of descriptors */
153 u16 rx_buf_len;
154 u16 next_to_use;
155 u16 next_to_clean;
156
157 u8 queue_index; /* needed for multiqueue queue management */
158
159#define IXGBE_RING_RX_PS_ENABLED (u8)(1)
160 u8 flags; /* per ring feature flags */
161 u16 head;
162 u16 tail;
163
164 unsigned int total_bytes;
165 unsigned int total_packets;
166
167#ifdef CONFIG_IXGBE_DCA
168 /* cpu for tx queue */
169 int cpu;
170#endif
171
172 u16 work_limit; /* max work per interrupt */
173 u16 reg_idx; /* holds the special value that gets
174 * the hardware register offset
175 * associated with this ring, which is
176 * different for DCB and RSS modes
177 */
178
179 struct ixgbe_queue_stats stats;
180 unsigned long reinit_state;
181 int numa_node;
182 u64 rsc_count; /* stat for coalesced packets */
183 u64 rsc_flush; /* stats for flushed packets */
184 u32 restart_queue; /* track tx queue restarts */
185 u32 non_eop_descs; /* track hardware descriptor chaining */
186
187 unsigned int size; /* length in bytes */
188 dma_addr_t dma; /* phys. address of descriptor ring */
189} ____cacheline_internodealigned_in_smp;
190
191enum ixgbe_ring_f_enum {
192 RING_F_NONE = 0,
193 RING_F_DCB,
194 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
195 RING_F_RSS,
196 RING_F_FDIR,
197#ifdef IXGBE_FCOE
198 RING_F_FCOE,
199#endif /* IXGBE_FCOE */
200
201 RING_F_ARRAY_SIZE /* must be last in enum set */
202};
203
204#define IXGBE_MAX_DCB_INDICES 8
205#define IXGBE_MAX_RSS_INDICES 16
206#define IXGBE_MAX_VMDQ_INDICES 64
207#define IXGBE_MAX_FDIR_INDICES 64
208#ifdef IXGBE_FCOE
209#define IXGBE_MAX_FCOE_INDICES 8
210#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
211#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
212#else
213#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
214#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
215#endif /* IXGBE_FCOE */
216struct ixgbe_ring_feature {
217 int indices;
218 int mask;
219} ____cacheline_internodealigned_in_smp;
220
221
222#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
223 ? 8 : 1)
224#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
225
226/* MAX_MSIX_Q_VECTORS of these are allocated,
227 * but we only use one per queue-specific vector.
228 */
229struct ixgbe_q_vector {
230 struct ixgbe_adapter *adapter;
231 unsigned int v_idx; /* index of q_vector within array, also used for
232 * finding the bit in EICR and friends that
233 * represents the vector for this ring */
234 struct napi_struct napi;
235 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
236 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
237 u8 rxr_count; /* Rx ring count assigned to this vector */
238 u8 txr_count; /* Tx ring count assigned to this vector */
239 u8 tx_itr;
240 u8 rx_itr;
241 u32 eitr;
242};
243
244/* Helper macros to switch between ints/sec and what the register uses.
245 * And yes, it's the same math going both ways. The lowest value
246 * supported by all of the ixgbe hardware is 8.
247 */
248#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
249 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
250#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
251
252#define IXGBE_DESC_UNUSED(R) \
253 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
254 (R)->next_to_clean - (R)->next_to_use - 1)
255
256#define IXGBE_RX_DESC_ADV(R, i) \
257 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
258#define IXGBE_TX_DESC_ADV(R, i) \
259 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
260#define IXGBE_TX_CTXTDESC_ADV(R, i) \
261 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
262
263#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
264#ifdef IXGBE_FCOE
265/* Use 3K as the baby jumbo frame size for FCoE */
266#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
267#endif /* IXGBE_FCOE */
268
269#define OTHER_VECTOR 1
270#define NON_Q_VECTORS (OTHER_VECTOR)
271
272#define MAX_MSIX_VECTORS_82599 64
273#define MAX_MSIX_Q_VECTORS_82599 64
274#define MAX_MSIX_VECTORS_82598 18
275#define MAX_MSIX_Q_VECTORS_82598 16
276
277#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
278#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
279
280#define MIN_MSIX_Q_VECTORS 2
281#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
282
283/* board specific private data structure */
284struct ixgbe_adapter {
285 struct timer_list watchdog_timer;
286 struct vlan_group *vlgrp;
287 u16 bd_number;
288 struct work_struct reset_task;
289 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
290 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
291 struct ixgbe_dcb_config dcb_cfg;
292 struct ixgbe_dcb_config temp_dcb_cfg;
293 u8 dcb_set_bitmap;
294 enum ixgbe_fc_mode last_lfc_mode;
295
296 /* Interrupt Throttle Rate */
297 u32 rx_itr_setting;
298 u32 tx_itr_setting;
299 u16 eitr_low;
300 u16 eitr_high;
301
302 /* TX */
303 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
304 int num_tx_queues;
305 u32 tx_timeout_count;
306 bool detect_tx_hung;
307
308 u64 restart_queue;
309 u64 lsc_int;
310
311 /* RX */
312 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
313 int num_rx_queues;
314 int num_rx_pools; /* == num_rx_queues in 82598 */
315 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
316 u64 hw_csum_rx_error;
317 u64 hw_rx_no_dma_resources;
318 u64 non_eop_descs;
319 int num_msix_vectors;
320 int max_msix_q_vectors; /* true count of q_vectors for device */
321 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
322 struct msix_entry *msix_entries;
323
324 u32 alloc_rx_page_failed;
325 u32 alloc_rx_buff_failed;
326
327 /* Some features need tri-state capability,
328 * thus the additional *_CAPABLE flags.
329 */
330 u32 flags;
331#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
332#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
333#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
334#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
335#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
336#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
337#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
338#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
339#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
340#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
341#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
342#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
343#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
344#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
345#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
346#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
347#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
348#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
349#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
350#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
351#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
352#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
353#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
354#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
355#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
356#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
357#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
358#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
359
360 u32 flags2;
361#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
362#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
363#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
364/* default to trying for four seconds */
365#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
366
367 /* OS defined structs */
368 struct net_device *netdev;
369 struct pci_dev *pdev;
370
371 u32 test_icr;
372 struct ixgbe_ring test_tx_ring;
373 struct ixgbe_ring test_rx_ring;
374
375 /* structs defined in ixgbe_hw.h */
376 struct ixgbe_hw hw;
377 u16 msg_enable;
378 struct ixgbe_hw_stats stats;
379
380 /* Interrupt Throttle Rate */
381 u32 rx_eitr_param;
382 u32 tx_eitr_param;
383
384 unsigned long state;
385 u64 tx_busy;
386 unsigned int tx_ring_count;
387 unsigned int rx_ring_count;
388
389 u32 link_speed;
390 bool link_up;
391 unsigned long link_check_timeout;
392
393 struct work_struct watchdog_task;
394 struct work_struct sfp_task;
395 struct timer_list sfp_timer;
396 struct work_struct multispeed_fiber_task;
397 struct work_struct sfp_config_module_task;
398 u32 fdir_pballoc;
399 u32 atr_sample_rate;
400 spinlock_t fdir_perfect_lock;
401 struct work_struct fdir_reinit_task;
402#ifdef IXGBE_FCOE
403 struct ixgbe_fcoe fcoe;
404#endif /* IXGBE_FCOE */
405 u64 rsc_total_count;
406 u64 rsc_total_flush;
407 u32 wol;
408 u16 eeprom_version;
409
410 int node;
411 struct work_struct check_overtemp_task;
412 u32 interrupt_event;
413
414 /* SR-IOV */
415 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
416 unsigned int num_vfs;
417 struct vf_data_storage *vfinfo;
418};
419
420enum ixbge_state_t {
421 __IXGBE_TESTING,
422 __IXGBE_RESETTING,
423 __IXGBE_DOWN,
424 __IXGBE_FDIR_INIT_DONE,
425 __IXGBE_SFP_MODULE_NOT_FOUND
426};
427
428enum ixgbe_boards {
429 board_82598,
430 board_82599,
431};
432
433extern struct ixgbe_info ixgbe_82598_info;
434extern struct ixgbe_info ixgbe_82599_info;
435#ifdef CONFIG_IXGBE_DCB
436extern const struct dcbnl_rtnl_ops dcbnl_ops;
437extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
438 struct ixgbe_dcb_config *dst_dcb_cfg,
439 int tc_max);
440#endif
441
442extern char ixgbe_driver_name[];
443extern const char ixgbe_driver_version[];
444
445extern int ixgbe_up(struct ixgbe_adapter *adapter);
446extern void ixgbe_down(struct ixgbe_adapter *adapter);
447extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
448extern void ixgbe_reset(struct ixgbe_adapter *adapter);
449extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
450extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
451extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
452extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
453extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
454extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
455extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
456extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
457extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
458extern int ethtool_ioctl(struct ifreq *ifr);
459extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
460extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
461extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
462extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
463 struct ixgbe_atr_input *input,
464 u8 queue);
465extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
466 struct ixgbe_atr_input *input,
467 struct ixgbe_atr_input_masks *input_masks,
468 u16 soft_id, u8 queue);
469extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
470 u16 vlan_id);
471extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
472 u32 src_addr);
473extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
474 u32 dst_addr);
475extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
476 u16 src_port);
477extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
478 u16 dst_port);
479extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
480 u16 flex_byte);
481extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
482 u8 l4type);
483extern void ixgbe_set_rx_mode(struct net_device *netdev);
484#ifdef IXGBE_FCOE
485extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
486extern int ixgbe_fso(struct ixgbe_adapter *adapter,
487 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
488 u32 tx_flags, u8 *hdr_len);
489extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
490extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
491 union ixgbe_adv_rx_desc *rx_desc,
492 struct sk_buff *skb);
493extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
494 struct scatterlist *sgl, unsigned int sgc);
495extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
496extern int ixgbe_fcoe_enable(struct net_device *netdev);
497extern int ixgbe_fcoe_disable(struct net_device *netdev);
498#ifdef CONFIG_IXGBE_DCB
499extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
500extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
501#endif /* CONFIG_IXGBE_DCB */
502extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
503#endif /* IXGBE_FCOE */
504
505#endif /* _IXGBE_H_ */