tjh.dev
Linux kernel mirror (for testing)
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1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _IGB_H_
32#define _IGB_H_
33
34#include "e1000_mac.h"
35#include "e1000_82575.h"
36
37#include <linux/clocksource.h>
38#include <linux/timecompare.h>
39#include <linux/net_tstamp.h>
40
41struct igb_adapter;
42
43/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
44#define IGB_START_ITR 648
45
46/* TX/RX descriptor defines */
47#define IGB_DEFAULT_TXD 256
48#define IGB_MIN_TXD 80
49#define IGB_MAX_TXD 4096
50
51#define IGB_DEFAULT_RXD 256
52#define IGB_MIN_RXD 80
53#define IGB_MAX_RXD 4096
54
55#define IGB_DEFAULT_ITR 3 /* dynamic */
56#define IGB_MAX_ITR_USECS 10000
57#define IGB_MIN_ITR_USECS 10
58#define NON_Q_VECTORS 1
59#define MAX_Q_VECTORS 8
60
61/* Transmit and receive queues */
62#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
63 (hw->mac.type > e1000_82575 ? 8 : 4))
64#define IGB_ABS_MAX_TX_QUEUES 8
65#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
66
67#define IGB_MAX_VF_MC_ENTRIES 30
68#define IGB_MAX_VF_FUNCTIONS 8
69#define IGB_MAX_VFTA_ENTRIES 128
70
71struct vf_data_storage {
72 unsigned char vf_mac_addresses[ETH_ALEN];
73 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
74 u16 num_vf_mc_hashes;
75 u16 vlans_enabled;
76 u32 flags;
77 unsigned long last_nack;
78 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
79 u16 pf_qos;
80};
81
82#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
83#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
84#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
85#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
86
87/* RX descriptor control thresholds.
88 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
89 * descriptors available in its onboard memory.
90 * Setting this to 0 disables RX descriptor prefetch.
91 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
92 * available in host memory.
93 * If PTHRESH is 0, this should also be 0.
94 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
95 * descriptors until either it has this many to write back, or the
96 * ITR timer expires.
97 */
98#define IGB_RX_PTHRESH 8
99#define IGB_RX_HTHRESH 8
100#define IGB_RX_WTHRESH 1
101#define IGB_TX_PTHRESH 8
102#define IGB_TX_HTHRESH 1
103#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
104 adapter->msix_entries) ? 1 : 16)
105
106/* this is the size past which hardware will drop packets when setting LPE=0 */
107#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
108
109/* Supported Rx Buffer Sizes */
110#define IGB_RXBUFFER_64 64 /* Used for packet split */
111#define IGB_RXBUFFER_128 128 /* Used for packet split */
112#define IGB_RXBUFFER_1024 1024
113#define IGB_RXBUFFER_2048 2048
114#define IGB_RXBUFFER_16384 16384
115
116#define MAX_STD_JUMBO_FRAME_SIZE 9234
117
118/* How many Tx Descriptors do we need to call netif_wake_queue ? */
119#define IGB_TX_QUEUE_WAKE 16
120/* How many Rx Buffers do we bundle into one write to the hardware ? */
121#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
122
123#define AUTO_ALL_MODES 0
124#define IGB_EEPROM_APME 0x0400
125
126#ifndef IGB_MASTER_SLAVE
127/* Switch to override PHY master/slave setting */
128#define IGB_MASTER_SLAVE e1000_ms_hw_default
129#endif
130
131#define IGB_MNG_VLAN_NONE -1
132
133/* wrapper around a pointer to a socket buffer,
134 * so a DMA handle can be stored along with the buffer */
135struct igb_buffer {
136 struct sk_buff *skb;
137 dma_addr_t dma;
138 union {
139 /* TX */
140 struct {
141 unsigned long time_stamp;
142 u16 length;
143 u16 next_to_watch;
144 unsigned int bytecount;
145 u16 gso_segs;
146 union skb_shared_tx shtx;
147 u8 mapped_as_page;
148 };
149 /* RX */
150 struct {
151 struct page *page;
152 dma_addr_t page_dma;
153 u16 page_offset;
154 };
155 };
156};
157
158struct igb_tx_queue_stats {
159 u64 packets;
160 u64 bytes;
161 u64 restart_queue;
162};
163
164struct igb_rx_queue_stats {
165 u64 packets;
166 u64 bytes;
167 u64 drops;
168 u64 csum_err;
169 u64 alloc_failed;
170};
171
172struct igb_q_vector {
173 struct igb_adapter *adapter; /* backlink */
174 struct igb_ring *rx_ring;
175 struct igb_ring *tx_ring;
176 struct napi_struct napi;
177
178 u32 eims_value;
179 u16 cpu;
180
181 u16 itr_val;
182 u8 set_itr;
183 void __iomem *itr_register;
184
185 char name[IFNAMSIZ + 9];
186};
187
188struct igb_ring {
189 struct igb_q_vector *q_vector; /* backlink to q_vector */
190 struct net_device *netdev; /* back pointer to net_device */
191 struct device *dev; /* device pointer for dma mapping */
192 dma_addr_t dma; /* phys address of the ring */
193 void *desc; /* descriptor ring memory */
194 unsigned int size; /* length of desc. ring in bytes */
195 u16 count; /* number of desc. in the ring */
196 u16 next_to_use;
197 u16 next_to_clean;
198 u8 queue_index;
199 u8 reg_idx;
200 void __iomem *head;
201 void __iomem *tail;
202 struct igb_buffer *buffer_info; /* array of buffer info structs */
203
204 unsigned int total_bytes;
205 unsigned int total_packets;
206
207 u32 flags;
208
209 union {
210 /* TX */
211 struct {
212 struct igb_tx_queue_stats tx_stats;
213 bool detect_tx_hung;
214 };
215 /* RX */
216 struct {
217 struct igb_rx_queue_stats rx_stats;
218 u32 rx_buffer_len;
219 };
220 };
221};
222
223#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
224#define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
225
226#define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
227
228#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)
229
230#define E1000_RX_DESC_ADV(R, i) \
231 (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
232#define E1000_TX_DESC_ADV(R, i) \
233 (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
234#define E1000_TX_CTXTDESC_ADV(R, i) \
235 (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
236
237/* igb_desc_unused - calculate if we have unused descriptors */
238static inline int igb_desc_unused(struct igb_ring *ring)
239{
240 if (ring->next_to_clean > ring->next_to_use)
241 return ring->next_to_clean - ring->next_to_use - 1;
242
243 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
244}
245
246/* board specific private data structure */
247struct igb_adapter {
248 struct timer_list watchdog_timer;
249 struct timer_list phy_info_timer;
250 struct vlan_group *vlgrp;
251 u16 mng_vlan_id;
252 u32 bd_number;
253 u32 wol;
254 u32 en_mng_pt;
255 u16 link_speed;
256 u16 link_duplex;
257
258 /* Interrupt Throttle Rate */
259 u32 rx_itr_setting;
260 u32 tx_itr_setting;
261 u16 tx_itr;
262 u16 rx_itr;
263
264 struct work_struct reset_task;
265 struct work_struct watchdog_task;
266 bool fc_autoneg;
267 u8 tx_timeout_factor;
268 struct timer_list blink_timer;
269 unsigned long led_status;
270
271 /* TX */
272 struct igb_ring *tx_ring[16];
273 u32 tx_timeout_count;
274
275 /* RX */
276 struct igb_ring *rx_ring[16];
277 int num_tx_queues;
278 int num_rx_queues;
279
280 u32 max_frame_size;
281 u32 min_frame_size;
282
283 /* OS defined structs */
284 struct net_device *netdev;
285 struct pci_dev *pdev;
286 struct cyclecounter cycles;
287 struct timecounter clock;
288 struct timecompare compare;
289 struct hwtstamp_config hwtstamp_config;
290
291 /* structs defined in e1000_hw.h */
292 struct e1000_hw hw;
293 struct e1000_hw_stats stats;
294 struct e1000_phy_info phy_info;
295 struct e1000_phy_stats phy_stats;
296
297 u32 test_icr;
298 struct igb_ring test_tx_ring;
299 struct igb_ring test_rx_ring;
300
301 int msg_enable;
302
303 unsigned int num_q_vectors;
304 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
305 struct msix_entry *msix_entries;
306 u32 eims_enable_mask;
307 u32 eims_other;
308
309 /* to not mess up cache alignment, always add to the bottom */
310 unsigned long state;
311 unsigned int flags;
312 u32 eeprom_wol;
313
314 struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
315 u16 tx_ring_count;
316 u16 rx_ring_count;
317 unsigned int vfs_allocated_count;
318 struct vf_data_storage *vf_data;
319 u32 rss_queues;
320};
321
322#define IGB_FLAG_HAS_MSI (1 << 0)
323#define IGB_FLAG_DCA_ENABLED (1 << 1)
324#define IGB_FLAG_QUAD_PORT_A (1 << 2)
325#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
326
327#define IGB_82576_TSYNC_SHIFT 19
328#define IGB_82580_TSYNC_SHIFT 24
329#define IGB_TS_HDR_LEN 16
330enum e1000_state_t {
331 __IGB_TESTING,
332 __IGB_RESETTING,
333 __IGB_DOWN
334};
335
336enum igb_boards {
337 board_82575,
338};
339
340extern char igb_driver_name[];
341extern char igb_driver_version[];
342
343extern int igb_up(struct igb_adapter *);
344extern void igb_down(struct igb_adapter *);
345extern void igb_reinit_locked(struct igb_adapter *);
346extern void igb_reset(struct igb_adapter *);
347extern int igb_set_spd_dplx(struct igb_adapter *, u16);
348extern int igb_setup_tx_resources(struct igb_ring *);
349extern int igb_setup_rx_resources(struct igb_ring *);
350extern void igb_free_tx_resources(struct igb_ring *);
351extern void igb_free_rx_resources(struct igb_ring *);
352extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
353extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
354extern void igb_setup_tctl(struct igb_adapter *);
355extern void igb_setup_rctl(struct igb_adapter *);
356extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *);
357extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
358 struct igb_buffer *);
359extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
360extern void igb_update_stats(struct igb_adapter *);
361extern bool igb_has_link(struct igb_adapter *adapter);
362extern void igb_set_ethtool_ops(struct net_device *);
363extern void igb_power_up_link(struct igb_adapter *);
364
365static inline s32 igb_reset_phy(struct e1000_hw *hw)
366{
367 if (hw->phy.ops.reset)
368 return hw->phy.ops.reset(hw);
369
370 return 0;
371}
372
373static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
374{
375 if (hw->phy.ops.read_reg)
376 return hw->phy.ops.read_reg(hw, offset, data);
377
378 return 0;
379}
380
381static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
382{
383 if (hw->phy.ops.write_reg)
384 return hw->phy.ops.write_reg(hw, offset, data);
385
386 return 0;
387}
388
389static inline s32 igb_get_phy_info(struct e1000_hw *hw)
390{
391 if (hw->phy.ops.get_phy_info)
392 return hw->phy.ops.get_phy_info(hw);
393
394 return 0;
395}
396
397#endif /* _IGB_H_ */