tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __R100D_H__
29#define __R100D_H__
30
31#define CP_PACKET0 0x00000000
32#define PACKET0_BASE_INDEX_SHIFT 0
33#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
34#define PACKET0_COUNT_SHIFT 16
35#define PACKET0_COUNT_MASK (0x3fff << 16)
36#define CP_PACKET1 0x40000000
37#define CP_PACKET2 0x80000000
38#define PACKET2_PAD_SHIFT 0
39#define PACKET2_PAD_MASK (0x3fffffff << 0)
40#define CP_PACKET3 0xC0000000
41#define PACKET3_IT_OPCODE_SHIFT 8
42#define PACKET3_IT_OPCODE_MASK (0xff << 8)
43#define PACKET3_COUNT_SHIFT 16
44#define PACKET3_COUNT_MASK (0x3fff << 16)
45/* PACKET3 op code */
46#define PACKET3_NOP 0x10
47#define PACKET3_3D_DRAW_VBUF 0x28
48#define PACKET3_3D_DRAW_IMMD 0x29
49#define PACKET3_3D_DRAW_INDX 0x2A
50#define PACKET3_3D_LOAD_VBPNTR 0x2F
51#define PACKET3_INDX_BUFFER 0x33
52#define PACKET3_3D_DRAW_VBUF_2 0x34
53#define PACKET3_3D_DRAW_IMMD_2 0x35
54#define PACKET3_3D_DRAW_INDX_2 0x36
55#define PACKET3_BITBLT_MULTI 0x9B
56
57#define PACKET0(reg, n) (CP_PACKET0 | \
58 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
59 REG_SET(PACKET0_COUNT, (n)))
60#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
61#define PACKET3(op, n) (CP_PACKET3 | \
62 REG_SET(PACKET3_IT_OPCODE, (op)) | \
63 REG_SET(PACKET3_COUNT, (n)))
64
65#define PACKET_TYPE0 0
66#define PACKET_TYPE1 1
67#define PACKET_TYPE2 2
68#define PACKET_TYPE3 3
69
70#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
71#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
72#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
73#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
74#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
75
76/* Registers */
77#define R_0000F0_RBBM_SOFT_RESET 0x0000F0
78#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)
79#define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1)
80#define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE
81#define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1)
82#define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1)
83#define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD
84#define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2)
85#define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1)
86#define C_0000F0_SOFT_RESET_SE 0xFFFFFFFB
87#define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3)
88#define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1)
89#define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7
90#define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4)
91#define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1)
92#define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF
93#define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5)
94#define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1)
95#define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF
96#define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6)
97#define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1)
98#define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF
99#define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7)
100#define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1)
101#define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F
102#define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8)
103#define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1)
104#define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF
105#define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9)
106#define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1)
107#define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF
108#define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10)
109#define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1)
110#define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF
111#define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11)
112#define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1)
113#define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF
114#define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12)
115#define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1)
116#define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF
117#define R_000030_BUS_CNTL 0x000030
118#define S_000030_BUS_DBL_RESYNC(x) (((x) & 0x1) << 0)
119#define G_000030_BUS_DBL_RESYNC(x) (((x) >> 0) & 0x1)
120#define C_000030_BUS_DBL_RESYNC 0xFFFFFFFE
121#define S_000030_BUS_MSTR_RESET(x) (((x) & 0x1) << 1)
122#define G_000030_BUS_MSTR_RESET(x) (((x) >> 1) & 0x1)
123#define C_000030_BUS_MSTR_RESET 0xFFFFFFFD
124#define S_000030_BUS_FLUSH_BUF(x) (((x) & 0x1) << 2)
125#define G_000030_BUS_FLUSH_BUF(x) (((x) >> 2) & 0x1)
126#define C_000030_BUS_FLUSH_BUF 0xFFFFFFFB
127#define S_000030_BUS_STOP_REQ_DIS(x) (((x) & 0x1) << 3)
128#define G_000030_BUS_STOP_REQ_DIS(x) (((x) >> 3) & 0x1)
129#define C_000030_BUS_STOP_REQ_DIS 0xFFFFFFF7
130#define S_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 4)
131#define G_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) >> 4) & 0x1)
132#define C_000030_BUS_PM4_READ_COMBINE_EN 0xFFFFFFEF
133#define S_000030_BUS_WRT_COMBINE_EN(x) (((x) & 0x1) << 5)
134#define G_000030_BUS_WRT_COMBINE_EN(x) (((x) >> 5) & 0x1)
135#define C_000030_BUS_WRT_COMBINE_EN 0xFFFFFFDF
136#define S_000030_BUS_MASTER_DIS(x) (((x) & 0x1) << 6)
137#define G_000030_BUS_MASTER_DIS(x) (((x) >> 6) & 0x1)
138#define C_000030_BUS_MASTER_DIS 0xFFFFFFBF
139#define S_000030_BIOS_ROM_WRT_EN(x) (((x) & 0x1) << 7)
140#define G_000030_BIOS_ROM_WRT_EN(x) (((x) >> 7) & 0x1)
141#define C_000030_BIOS_ROM_WRT_EN 0xFFFFFF7F
142#define S_000030_BM_DAC_CRIPPLE(x) (((x) & 0x1) << 8)
143#define G_000030_BM_DAC_CRIPPLE(x) (((x) >> 8) & 0x1)
144#define C_000030_BM_DAC_CRIPPLE 0xFFFFFEFF
145#define S_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 9)
146#define G_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) >> 9) & 0x1)
147#define C_000030_BUS_NON_PM4_READ_COMBINE_EN 0xFFFFFDFF
148#define S_000030_BUS_XFERD_DISCARD_EN(x) (((x) & 0x1) << 10)
149#define G_000030_BUS_XFERD_DISCARD_EN(x) (((x) >> 10) & 0x1)
150#define C_000030_BUS_XFERD_DISCARD_EN 0xFFFFFBFF
151#define S_000030_BUS_SGL_READ_DISABLE(x) (((x) & 0x1) << 11)
152#define G_000030_BUS_SGL_READ_DISABLE(x) (((x) >> 11) & 0x1)
153#define C_000030_BUS_SGL_READ_DISABLE 0xFFFFF7FF
154#define S_000030_BIOS_DIS_ROM(x) (((x) & 0x1) << 12)
155#define G_000030_BIOS_DIS_ROM(x) (((x) >> 12) & 0x1)
156#define C_000030_BIOS_DIS_ROM 0xFFFFEFFF
157#define S_000030_BUS_PCI_READ_RETRY_EN(x) (((x) & 0x1) << 13)
158#define G_000030_BUS_PCI_READ_RETRY_EN(x) (((x) >> 13) & 0x1)
159#define C_000030_BUS_PCI_READ_RETRY_EN 0xFFFFDFFF
160#define S_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) & 0x1) << 14)
161#define G_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) >> 14) & 0x1)
162#define C_000030_BUS_AGP_AD_STEPPING_EN 0xFFFFBFFF
163#define S_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) & 0x1) << 15)
164#define G_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) >> 15) & 0x1)
165#define C_000030_BUS_PCI_WRT_RETRY_EN 0xFFFF7FFF
166#define S_000030_BUS_RETRY_WS(x) (((x) & 0xF) << 16)
167#define G_000030_BUS_RETRY_WS(x) (((x) >> 16) & 0xF)
168#define C_000030_BUS_RETRY_WS 0xFFF0FFFF
169#define S_000030_BUS_MSTR_RD_MULT(x) (((x) & 0x1) << 20)
170#define G_000030_BUS_MSTR_RD_MULT(x) (((x) >> 20) & 0x1)
171#define C_000030_BUS_MSTR_RD_MULT 0xFFEFFFFF
172#define S_000030_BUS_MSTR_RD_LINE(x) (((x) & 0x1) << 21)
173#define G_000030_BUS_MSTR_RD_LINE(x) (((x) >> 21) & 0x1)
174#define C_000030_BUS_MSTR_RD_LINE 0xFFDFFFFF
175#define S_000030_BUS_SUSPEND(x) (((x) & 0x1) << 22)
176#define G_000030_BUS_SUSPEND(x) (((x) >> 22) & 0x1)
177#define C_000030_BUS_SUSPEND 0xFFBFFFFF
178#define S_000030_LAT_16X(x) (((x) & 0x1) << 23)
179#define G_000030_LAT_16X(x) (((x) >> 23) & 0x1)
180#define C_000030_LAT_16X 0xFF7FFFFF
181#define S_000030_BUS_RD_DISCARD_EN(x) (((x) & 0x1) << 24)
182#define G_000030_BUS_RD_DISCARD_EN(x) (((x) >> 24) & 0x1)
183#define C_000030_BUS_RD_DISCARD_EN 0xFEFFFFFF
184#define S_000030_ENFRCWRDY(x) (((x) & 0x1) << 25)
185#define G_000030_ENFRCWRDY(x) (((x) >> 25) & 0x1)
186#define C_000030_ENFRCWRDY 0xFDFFFFFF
187#define S_000030_BUS_MSTR_WS(x) (((x) & 0x1) << 26)
188#define G_000030_BUS_MSTR_WS(x) (((x) >> 26) & 0x1)
189#define C_000030_BUS_MSTR_WS 0xFBFFFFFF
190#define S_000030_BUS_PARKING_DIS(x) (((x) & 0x1) << 27)
191#define G_000030_BUS_PARKING_DIS(x) (((x) >> 27) & 0x1)
192#define C_000030_BUS_PARKING_DIS 0xF7FFFFFF
193#define S_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) & 0x1) << 28)
194#define G_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) >> 28) & 0x1)
195#define C_000030_BUS_MSTR_DISCONNECT_EN 0xEFFFFFFF
196#define S_000030_SERR_EN(x) (((x) & 0x1) << 29)
197#define G_000030_SERR_EN(x) (((x) >> 29) & 0x1)
198#define C_000030_SERR_EN 0xDFFFFFFF
199#define S_000030_BUS_READ_BURST(x) (((x) & 0x1) << 30)
200#define G_000030_BUS_READ_BURST(x) (((x) >> 30) & 0x1)
201#define C_000030_BUS_READ_BURST 0xBFFFFFFF
202#define S_000030_BUS_RDY_READ_DLY(x) (((x) & 0x1) << 31)
203#define G_000030_BUS_RDY_READ_DLY(x) (((x) >> 31) & 0x1)
204#define C_000030_BUS_RDY_READ_DLY 0x7FFFFFFF
205#define R_000040_GEN_INT_CNTL 0x000040
206#define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0)
207#define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1)
208#define C_000040_CRTC_VBLANK 0xFFFFFFFE
209#define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1)
210#define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1)
211#define C_000040_CRTC_VLINE 0xFFFFFFFD
212#define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2)
213#define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1)
214#define C_000040_CRTC_VSYNC 0xFFFFFFFB
215#define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3)
216#define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1)
217#define C_000040_SNAPSHOT 0xFFFFFFF7
218#define S_000040_FP_DETECT(x) (((x) & 0x1) << 4)
219#define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1)
220#define C_000040_FP_DETECT 0xFFFFFFEF
221#define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5)
222#define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1)
223#define C_000040_CRTC2_VLINE 0xFFFFFFDF
224#define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12)
225#define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1)
226#define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF
227#define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6)
228#define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1)
229#define C_000040_CRTC2_VSYNC 0xFFFFFFBF
230#define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7)
231#define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1)
232#define C_000040_SNAPSHOT2 0xFFFFFF7F
233#define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9)
234#define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1)
235#define C_000040_CRTC2_VBLANK 0xFFFFFDFF
236#define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10)
237#define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1)
238#define C_000040_FP2_DETECT 0xFFFFFBFF
239#define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11)
240#define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1)
241#define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF
242#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)
243#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)
244#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF
245#define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14)
246#define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1)
247#define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF
248#define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15)
249#define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1)
250#define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF
251#define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17)
252#define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1)
253#define C_000040_I2C_INT_EN 0xFFFDFFFF
254#define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19)
255#define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1)
256#define C_000040_GUI_IDLE 0xFFF7FFFF
257#define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24)
258#define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1)
259#define C_000040_VIPH_INT_EN 0xFEFFFFFF
260#define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25)
261#define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1)
262#define C_000040_SW_INT_EN 0xFDFFFFFF
263#define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27)
264#define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1)
265#define C_000040_GEYSERVILLE 0xF7FFFFFF
266#define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28)
267#define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1)
268#define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF
269#define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29)
270#define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1)
271#define C_000040_DVI_I2C_INT 0xDFFFFFFF
272#define S_000040_GUIDMA(x) (((x) & 0x1) << 30)
273#define G_000040_GUIDMA(x) (((x) >> 30) & 0x1)
274#define C_000040_GUIDMA 0xBFFFFFFF
275#define S_000040_VIDDMA(x) (((x) & 0x1) << 31)
276#define G_000040_VIDDMA(x) (((x) >> 31) & 0x1)
277#define C_000040_VIDDMA 0x7FFFFFFF
278#define R_000044_GEN_INT_STATUS 0x000044
279#define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0)
280#define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1)
281#define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE
282#define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0)
283#define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1)
284#define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE
285#define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1)
286#define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1)
287#define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD
288#define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1)
289#define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1)
290#define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD
291#define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2)
292#define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1)
293#define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB
294#define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2)
295#define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1)
296#define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB
297#define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3)
298#define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1)
299#define C_000044_SNAPSHOT_STAT 0xFFFFFFF7
300#define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3)
301#define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1)
302#define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7
303#define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4)
304#define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1)
305#define C_000044_FP_DETECT_STAT 0xFFFFFFEF
306#define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4)
307#define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1)
308#define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF
309#define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5)
310#define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1)
311#define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF
312#define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5)
313#define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1)
314#define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF
315#define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6)
316#define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1)
317#define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF
318#define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6)
319#define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1)
320#define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF
321#define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7)
322#define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1)
323#define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F
324#define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7)
325#define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1)
326#define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F
327#define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8)
328#define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1)
329#define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF
330#define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9)
331#define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1)
332#define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF
333#define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9)
334#define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1)
335#define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF
336#define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10)
337#define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1)
338#define C_000044_FP2_DETECT_STAT 0xFFFFFBFF
339#define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10)
340#define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1)
341#define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF
342#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11)
343#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1)
344#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF
345#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11)
346#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1)
347#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF
348#define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12)
349#define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1)
350#define C_000044_DMA_VIPH0_INT 0xFFFFEFFF
351#define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12)
352#define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1)
353#define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF
354#define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13)
355#define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1)
356#define C_000044_DMA_VIPH1_INT 0xFFFFDFFF
357#define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13)
358#define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1)
359#define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF
360#define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14)
361#define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1)
362#define C_000044_DMA_VIPH2_INT 0xFFFFBFFF
363#define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14)
364#define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1)
365#define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF
366#define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15)
367#define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1)
368#define C_000044_DMA_VIPH3_INT 0xFFFF7FFF
369#define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15)
370#define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1)
371#define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF
372#define S_000044_I2C_INT(x) (((x) & 0x1) << 17)
373#define G_000044_I2C_INT(x) (((x) >> 17) & 0x1)
374#define C_000044_I2C_INT 0xFFFDFFFF
375#define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17)
376#define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1)
377#define C_000044_I2C_INT_AK 0xFFFDFFFF
378#define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19)
379#define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1)
380#define C_000044_GUI_IDLE_STAT 0xFFF7FFFF
381#define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19)
382#define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1)
383#define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF
384#define S_000044_VIPH_INT(x) (((x) & 0x1) << 24)
385#define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1)
386#define C_000044_VIPH_INT 0xFEFFFFFF
387#define S_000044_SW_INT(x) (((x) & 0x1) << 25)
388#define G_000044_SW_INT(x) (((x) >> 25) & 0x1)
389#define C_000044_SW_INT 0xFDFFFFFF
390#define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25)
391#define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1)
392#define C_000044_SW_INT_AK 0xFDFFFFFF
393#define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26)
394#define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1)
395#define C_000044_SW_INT_SET 0xFBFFFFFF
396#define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27)
397#define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1)
398#define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF
399#define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27)
400#define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1)
401#define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF
402#define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28)
403#define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1)
404#define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF
405#define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28)
406#define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1)
407#define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF
408#define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29)
409#define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1)
410#define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF
411#define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29)
412#define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1)
413#define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF
414#define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30)
415#define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1)
416#define C_000044_GUIDMA_STAT 0xBFFFFFFF
417#define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30)
418#define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1)
419#define C_000044_GUIDMA_AK 0xBFFFFFFF
420#define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31)
421#define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1)
422#define C_000044_VIDDMA_STAT 0x7FFFFFFF
423#define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31)
424#define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1)
425#define C_000044_VIDDMA_AK 0x7FFFFFFF
426#define R_000050_CRTC_GEN_CNTL 0x000050
427#define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0)
428#define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1)
429#define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE
430#define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1)
431#define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1)
432#define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD
433#define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4)
434#define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1)
435#define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF
436#define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8)
437#define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF)
438#define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF
439#define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15)
440#define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1)
441#define C_000050_CRTC_ICON_EN 0xFFFF7FFF
442#define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16)
443#define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1)
444#define C_000050_CRTC_CUR_EN 0xFFFEFFFF
445#define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17)
446#define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3)
447#define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF
448#define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20)
449#define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7)
450#define C_000050_CRTC_CUR_MODE 0xFF8FFFFF
451#define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24)
452#define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1)
453#define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF
454#define S_000050_CRTC_EN(x) (((x) & 0x1) << 25)
455#define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1)
456#define C_000050_CRTC_EN 0xFDFFFFFF
457#define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26)
458#define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1)
459#define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF
460#define R_000054_CRTC_EXT_CNTL 0x000054
461#define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0)
462#define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1)
463#define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE
464#define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1)
465#define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3)
466#define C_000054_VGA_BLINK_RATE 0xFFFFFFF9
467#define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3)
468#define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1)
469#define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7
470#define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4)
471#define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1)
472#define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF
473#define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5)
474#define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1)
475#define C_000054_VGA_TEXT_132 0xFFFFFFDF
476#define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6)
477#define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1)
478#define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF
479#define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8)
480#define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1)
481#define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF
482#define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9)
483#define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1)
484#define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF
485#define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10)
486#define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1)
487#define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF
488#define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11)
489#define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1)
490#define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF
491#define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12)
492#define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1)
493#define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF
494#define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13)
495#define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1)
496#define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF
497#define S_000054_CRT_ON(x) (((x) & 0x1) << 15)
498#define G_000054_CRT_ON(x) (((x) >> 15) & 0x1)
499#define C_000054_CRT_ON 0xFFFF7FFF
500#define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17)
501#define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1)
502#define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF
503#define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18)
504#define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1)
505#define C_000054_VGA_PACK_DIS 0xFFFBFFFF
506#define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19)
507#define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1)
508#define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF
509#define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24)
510#define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F)
511#define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF
512#define R_000148_MC_FB_LOCATION 0x000148
513#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)
514#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
515#define C_000148_MC_FB_START 0xFFFF0000
516#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
517#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
518#define C_000148_MC_FB_TOP 0x0000FFFF
519#define R_00014C_MC_AGP_LOCATION 0x00014C
520#define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
521#define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
522#define C_00014C_MC_AGP_START 0xFFFF0000
523#define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
524#define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
525#define C_00014C_MC_AGP_TOP 0x0000FFFF
526#define R_000170_AGP_BASE 0x000170
527#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
528#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
529#define C_000170_AGP_BASE_ADDR 0x00000000
530#define R_00023C_DISPLAY_BASE_ADDR 0x00023C
531#define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
532#define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
533#define C_00023C_DISPLAY_BASE_ADDR 0x00000000
534#define R_000260_CUR_OFFSET 0x000260
535#define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0)
536#define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF)
537#define C_000260_CUR_OFFSET 0xF8000000
538#define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31)
539#define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1)
540#define C_000260_CUR_LOCK 0x7FFFFFFF
541#define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C
542#define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
543#define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
544#define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000
545#define R_000360_CUR2_OFFSET 0x000360
546#define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0)
547#define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF)
548#define C_000360_CUR2_OFFSET 0xF8000000
549#define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31)
550#define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1)
551#define C_000360_CUR2_LOCK 0x7FFFFFFF
552#define R_0003C2_GENMO_WT 0x0003C0
553#define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0)
554#define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1)
555#define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE
556#define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1)
557#define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1)
558#define C_0003C2_VGA_RAM_EN 0xFD
559#define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2)
560#define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3)
561#define C_0003C2_VGA_CKSEL 0xF3
562#define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5)
563#define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1)
564#define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF
565#define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6)
566#define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1)
567#define C_0003C2_VGA_HSYNC_POL 0xBF
568#define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7)
569#define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1)
570#define C_0003C2_VGA_VSYNC_POL 0x7F
571#define R_0003F8_CRTC2_GEN_CNTL 0x0003F8
572#define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0)
573#define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1)
574#define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE
575#define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1)
576#define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1)
577#define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD
578#define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4)
579#define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1)
580#define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF
581#define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5)
582#define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1)
583#define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF
584#define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6)
585#define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1)
586#define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF
587#define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7)
588#define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1)
589#define C_0003F8_CRT2_ON 0xFFFFFF7F
590#define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8)
591#define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF)
592#define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF
593#define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15)
594#define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1)
595#define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF
596#define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16)
597#define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1)
598#define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF
599#define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20)
600#define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7)
601#define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF
602#define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23)
603#define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1)
604#define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF
605#define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25)
606#define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1)
607#define C_0003F8_CRTC2_EN 0xFDFFFFFF
608#define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26)
609#define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1)
610#define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF
611#define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27)
612#define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1)
613#define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF
614#define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28)
615#define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1)
616#define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF
617#define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29)
618#define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1)
619#define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF
620#define R_000420_OV0_SCALE_CNTL 0x000420
621#define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1)
622#define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1)
623#define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD
624#define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2)
625#define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1)
626#define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB
627#define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3)
628#define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1)
629#define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7
630#define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4)
631#define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1)
632#define C_000420_OV0_SIGNED_UV 0xFFFFFFEF
633#define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5)
634#define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7)
635#define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F
636#define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8)
637#define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF)
638#define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF
639#define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12)
640#define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1)
641#define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF
642#define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14)
643#define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1)
644#define C_000420_OV0_CRTC_SEL 0xFFFFBFFF
645#define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16)
646#define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F)
647#define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF
648#define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24)
649#define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1)
650#define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF
651#define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26)
652#define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1)
653#define C_000420_OV0_BANDWIDTH 0xFBFFFFFF
654#define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28)
655#define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1)
656#define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF
657#define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29)
658#define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1)
659#define C_000420_OV0_INT_EMU 0xDFFFFFFF
660#define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30)
661#define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1)
662#define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF
663#define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31)
664#define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1)
665#define C_000420_OV0_SOFT_RESET 0x7FFFFFFF
666#define R_00070C_CP_RB_RPTR_ADDR 0x00070C
667#define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0)
668#define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3)
669#define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC
670#define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2)
671#define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF)
672#define C_00070C_RB_RPTR_ADDR 0x00000003
673#define R_000740_CP_CSQ_CNTL 0x000740
674#define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0)
675#define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF)
676#define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00
677#define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8)
678#define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF)
679#define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF
680#define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28)
681#define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF)
682#define C_000740_CSQ_MODE 0x0FFFFFFF
683#define R_000770_SCRATCH_UMSK 0x000770
684#define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0)
685#define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F)
686#define C_000770_SCRATCH_UMSK 0xFFFFFFC0
687#define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16)
688#define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3)
689#define C_000770_SCRATCH_SWAP 0xFFFCFFFF
690#define R_000774_SCRATCH_ADDR 0x000774
691#define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5)
692#define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF)
693#define C_000774_SCRATCH_ADDR 0x0000001F
694#define R_0007C0_CP_STAT 0x0007C0
695#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
696#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
697#define C_0007C0_MRU_BUSY 0xFFFFFFFE
698#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
699#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
700#define C_0007C0_MWU_BUSY 0xFFFFFFFD
701#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
702#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
703#define C_0007C0_RSIU_BUSY 0xFFFFFFFB
704#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
705#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
706#define C_0007C0_RCIU_BUSY 0xFFFFFFF7
707#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
708#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
709#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
710#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
711#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
712#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
713#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
714#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
715#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
716#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
717#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
718#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
719#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
720#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
721#define C_0007C0_CSI_BUSY 0xFFFFDFFF
722#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
723#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
724#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
725#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
726#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
727#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
728#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
729#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
730#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
731#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
732#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
733#define C_0007C0_CP_BUSY 0x7FFFFFFF
734#define R_000E40_RBBM_STATUS 0x000E40
735#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
736#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
737#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
738#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
739#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
740#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
741#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
742#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
743#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
744#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
745#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
746#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
747#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
748#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
749#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
750#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
751#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
752#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
753#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
754#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
755#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
756#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
757#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
758#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
759#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
760#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
761#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
762#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
763#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
764#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
765#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
766#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
767#define C_000E40_E2_BUSY 0xFFFDFFFF
768#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
769#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
770#define C_000E40_RB2D_BUSY 0xFFFBFFFF
771#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
772#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
773#define C_000E40_RB3D_BUSY 0xFFF7FFFF
774#define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20)
775#define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1)
776#define C_000E40_SE_BUSY 0xFFEFFFFF
777#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
778#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
779#define C_000E40_RE_BUSY 0xFFDFFFFF
780#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
781#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
782#define C_000E40_TAM_BUSY 0xFFBFFFFF
783#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
784#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
785#define C_000E40_TDM_BUSY 0xFF7FFFFF
786#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
787#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
788#define C_000E40_PB_BUSY 0xFEFFFFFF
789#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
790#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
791#define C_000E40_GUI_ACTIVE 0x7FFFFFFF
792
793
794#define R_00000D_SCLK_CNTL 0x00000D
795#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0)
796#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7)
797#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8
798#define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8)
799#define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7)
800#define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF
801#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16)
802#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1)
803#define C_00000D_FORCE_CP 0xFFFEFFFF
804#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17)
805#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1)
806#define C_00000D_FORCE_HDP 0xFFFDFFFF
807#define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18)
808#define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1)
809#define C_00000D_FORCE_DISP 0xFFFBFFFF
810#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19)
811#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1)
812#define C_00000D_FORCE_TOP 0xFFF7FFFF
813#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20)
814#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1)
815#define C_00000D_FORCE_E2 0xFFEFFFFF
816#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21)
817#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1)
818#define C_00000D_FORCE_SE 0xFFDFFFFF
819#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22)
820#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1)
821#define C_00000D_FORCE_IDCT 0xFFBFFFFF
822#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23)
823#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1)
824#define C_00000D_FORCE_VIP 0xFF7FFFFF
825#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24)
826#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1)
827#define C_00000D_FORCE_RE 0xFEFFFFFF
828#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25)
829#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1)
830#define C_00000D_FORCE_PB 0xFDFFFFFF
831#define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26)
832#define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1)
833#define C_00000D_FORCE_TAM 0xFBFFFFFF
834#define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27)
835#define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1)
836#define C_00000D_FORCE_TDM 0xF7FFFFFF
837#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28)
838#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1)
839#define C_00000D_FORCE_RB 0xEFFFFFFF
840
841/* PLL regs */
842#define SCLK_CNTL 0xd
843#define FORCE_HDP (1 << 17)
844#define CLK_PWRMGT_CNTL 0x14
845#define GLOBAL_PMAN_EN (1 << 10)
846#define DISP_PM (1 << 20)
847#define PLL_PWRMGT_CNTL 0x15
848#define MPLL_TURNOFF (1 << 0)
849#define SPLL_TURNOFF (1 << 1)
850#define PPLL_TURNOFF (1 << 2)
851#define P2PLL_TURNOFF (1 << 3)
852#define TVPLL_TURNOFF (1 << 4)
853#define MOBILE_SU (1 << 16)
854#define SU_SCLK_USE_BCLK (1 << 17)
855#define SCLK_CNTL2 0x1e
856#define REDUCED_SPEED_SCLK_MODE (1 << 16)
857#define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17)
858#define MCLK_MISC 0x1f
859#define EN_MCLK_TRISTATE_IN_SUSPEND (1 << 18)
860#define SCLK_MORE_CNTL 0x35
861#define REDUCED_SPEED_SCLK_EN (1 << 16)
862#define IO_CG_VOLTAGE_DROP (1 << 17)
863#define VOLTAGE_DELAY_SEL(x) ((x) << 20)
864#define VOLTAGE_DROP_SYNC (1 << 19)
865
866/* mmreg */
867#define DISP_PWR_MAN 0xd08
868#define DISP_D3_GRPH_RST (1 << 18)
869#define DISP_D3_SUBPIC_RST (1 << 19)
870#define DISP_D3_OV0_RST (1 << 20)
871#define DISP_D1D2_GRPH_RST (1 << 21)
872#define DISP_D1D2_SUBPIC_RST (1 << 22)
873#define DISP_D1D2_OV0_RST (1 << 23)
874#define DISP_DVO_ENABLE_RST (1 << 24)
875#define TV_ENABLE_RST (1 << 25)
876#define AUTO_PWRUP_EN (1 << 26)
877
878#endif