tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53#include <linux/aer.h>
54
55#include <drm/ttm/ttm_bo_api.h>
56#include <drm/ttm/ttm_bo_driver.h>
57#include <drm/ttm/ttm_placement.h>
58#include <drm/ttm/ttm_execbuf_util.h>
59
60#include <drm/amdgpu_drm.h>
61#include <drm/drm_gem.h>
62#include <drm/drm_ioctl.h>
63#include <drm/gpu_scheduler.h>
64
65#include <kgd_kfd_interface.h>
66#include "dm_pp_interface.h"
67#include "kgd_pp_interface.h"
68
69#include "amd_shared.h"
70#include "amdgpu_mode.h"
71#include "amdgpu_ih.h"
72#include "amdgpu_irq.h"
73#include "amdgpu_ucode.h"
74#include "amdgpu_ttm.h"
75#include "amdgpu_psp.h"
76#include "amdgpu_gds.h"
77#include "amdgpu_sync.h"
78#include "amdgpu_ring.h"
79#include "amdgpu_vm.h"
80#include "amdgpu_dpm.h"
81#include "amdgpu_acp.h"
82#include "amdgpu_uvd.h"
83#include "amdgpu_vce.h"
84#include "amdgpu_vcn.h"
85#include "amdgpu_jpeg.h"
86#include "amdgpu_mn.h"
87#include "amdgpu_gmc.h"
88#include "amdgpu_gfx.h"
89#include "amdgpu_sdma.h"
90#include "amdgpu_nbio.h"
91#include "amdgpu_hdp.h"
92#include "amdgpu_dm.h"
93#include "amdgpu_virt.h"
94#include "amdgpu_csa.h"
95#include "amdgpu_gart.h"
96#include "amdgpu_debugfs.h"
97#include "amdgpu_job.h"
98#include "amdgpu_bo_list.h"
99#include "amdgpu_gem.h"
100#include "amdgpu_doorbell.h"
101#include "amdgpu_amdkfd.h"
102#include "amdgpu_smu.h"
103#include "amdgpu_discovery.h"
104#include "amdgpu_mes.h"
105#include "amdgpu_umc.h"
106#include "amdgpu_mmhub.h"
107#include "amdgpu_gfxhub.h"
108#include "amdgpu_df.h"
109#include "amdgpu_smuio.h"
110#include "amdgpu_fdinfo.h"
111#include "amdgpu_mca.h"
112
113#define MAX_GPU_INSTANCE 16
114
115struct amdgpu_gpu_instance
116{
117 struct amdgpu_device *adev;
118 int mgpu_fan_enabled;
119};
120
121struct amdgpu_mgpu_info
122{
123 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
124 struct mutex mutex;
125 uint32_t num_gpu;
126 uint32_t num_dgpu;
127 uint32_t num_apu;
128
129 /* delayed reset_func for XGMI configuration if necessary */
130 struct delayed_work delayed_reset_work;
131 bool pending_reset;
132};
133
134enum amdgpu_ss {
135 AMDGPU_SS_DRV_LOAD,
136 AMDGPU_SS_DEV_D0,
137 AMDGPU_SS_DEV_D3,
138 AMDGPU_SS_DRV_UNLOAD
139};
140
141struct amdgpu_watchdog_timer
142{
143 bool timeout_fatal_disable;
144 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
145};
146
147#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
148
149/*
150 * Modules parameters.
151 */
152extern int amdgpu_modeset;
153extern int amdgpu_vram_limit;
154extern int amdgpu_vis_vram_limit;
155extern int amdgpu_gart_size;
156extern int amdgpu_gtt_size;
157extern int amdgpu_moverate;
158extern int amdgpu_benchmarking;
159extern int amdgpu_testing;
160extern int amdgpu_audio;
161extern int amdgpu_disp_priority;
162extern int amdgpu_hw_i2c;
163extern int amdgpu_pcie_gen2;
164extern int amdgpu_msi;
165extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
166extern int amdgpu_dpm;
167extern int amdgpu_fw_load_type;
168extern int amdgpu_aspm;
169extern int amdgpu_runtime_pm;
170extern uint amdgpu_ip_block_mask;
171extern int amdgpu_bapm;
172extern int amdgpu_deep_color;
173extern int amdgpu_vm_size;
174extern int amdgpu_vm_block_size;
175extern int amdgpu_vm_fragment_size;
176extern int amdgpu_vm_fault_stop;
177extern int amdgpu_vm_debug;
178extern int amdgpu_vm_update_mode;
179extern int amdgpu_exp_hw_support;
180extern int amdgpu_dc;
181extern int amdgpu_sched_jobs;
182extern int amdgpu_sched_hw_submission;
183extern uint amdgpu_pcie_gen_cap;
184extern uint amdgpu_pcie_lane_cap;
185extern uint amdgpu_cg_mask;
186extern uint amdgpu_pg_mask;
187extern uint amdgpu_sdma_phase_quantum;
188extern char *amdgpu_disable_cu;
189extern char *amdgpu_virtual_display;
190extern uint amdgpu_pp_feature_mask;
191extern uint amdgpu_force_long_training;
192extern int amdgpu_job_hang_limit;
193extern int amdgpu_lbpw;
194extern int amdgpu_compute_multipipe;
195extern int amdgpu_gpu_recovery;
196extern int amdgpu_emu_mode;
197extern uint amdgpu_smu_memory_pool_size;
198extern int amdgpu_smu_pptable_id;
199extern uint amdgpu_dc_feature_mask;
200extern uint amdgpu_freesync_vid_mode;
201extern uint amdgpu_dc_debug_mask;
202extern uint amdgpu_dm_abm_level;
203extern int amdgpu_backlight;
204extern struct amdgpu_mgpu_info mgpu_info;
205extern int amdgpu_ras_enable;
206extern uint amdgpu_ras_mask;
207extern int amdgpu_bad_page_threshold;
208extern bool amdgpu_ignore_bad_page_threshold;
209extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
210extern int amdgpu_async_gfx_ring;
211extern int amdgpu_mcbp;
212extern int amdgpu_discovery;
213extern int amdgpu_mes;
214extern int amdgpu_noretry;
215extern int amdgpu_force_asic_type;
216extern int amdgpu_smartshift_bias;
217#ifdef CONFIG_HSA_AMD
218extern int sched_policy;
219extern bool debug_evictions;
220extern bool no_system_mem_limit;
221#else
222static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
223static const bool __maybe_unused debug_evictions; /* = false */
224static const bool __maybe_unused no_system_mem_limit;
225#endif
226
227extern int amdgpu_tmz;
228extern int amdgpu_reset_method;
229
230#ifdef CONFIG_DRM_AMDGPU_SI
231extern int amdgpu_si_support;
232#endif
233#ifdef CONFIG_DRM_AMDGPU_CIK
234extern int amdgpu_cik_support;
235#endif
236extern int amdgpu_num_kcq;
237
238#define AMDGPU_VM_MAX_NUM_CTX 4096
239#define AMDGPU_SG_THRESHOLD (256*1024*1024)
240#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
241#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
242#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
243#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
244#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
245#define AMDGPUFB_CONN_LIMIT 4
246#define AMDGPU_BIOS_NUM_SCRATCH 16
247
248#define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
249
250/* hard reset data */
251#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
252
253/* reset flags */
254#define AMDGPU_RESET_GFX (1 << 0)
255#define AMDGPU_RESET_COMPUTE (1 << 1)
256#define AMDGPU_RESET_DMA (1 << 2)
257#define AMDGPU_RESET_CP (1 << 3)
258#define AMDGPU_RESET_GRBM (1 << 4)
259#define AMDGPU_RESET_DMA1 (1 << 5)
260#define AMDGPU_RESET_RLC (1 << 6)
261#define AMDGPU_RESET_SEM (1 << 7)
262#define AMDGPU_RESET_IH (1 << 8)
263#define AMDGPU_RESET_VMC (1 << 9)
264#define AMDGPU_RESET_MC (1 << 10)
265#define AMDGPU_RESET_DISPLAY (1 << 11)
266#define AMDGPU_RESET_UVD (1 << 12)
267#define AMDGPU_RESET_VCE (1 << 13)
268#define AMDGPU_RESET_VCE1 (1 << 14)
269
270/* max cursor sizes (in pixels) */
271#define CIK_CURSOR_WIDTH 128
272#define CIK_CURSOR_HEIGHT 128
273
274/* smasrt shift bias level limits */
275#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
276#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
277
278struct amdgpu_device;
279struct amdgpu_ib;
280struct amdgpu_cs_parser;
281struct amdgpu_job;
282struct amdgpu_irq_src;
283struct amdgpu_fpriv;
284struct amdgpu_bo_va_mapping;
285struct kfd_vm_fault_info;
286struct amdgpu_hive_info;
287struct amdgpu_reset_context;
288struct amdgpu_reset_control;
289
290enum amdgpu_cp_irq {
291 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
292 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
293 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
294 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
295 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
296 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
297 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
298 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
299 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
300 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
301
302 AMDGPU_CP_IRQ_LAST
303};
304
305enum amdgpu_thermal_irq {
306 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
307 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
308
309 AMDGPU_THERMAL_IRQ_LAST
310};
311
312enum amdgpu_kiq_irq {
313 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
314 AMDGPU_CP_KIQ_IRQ_LAST
315};
316
317#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
318#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
319#define MAX_KIQ_REG_TRY 1000
320
321int amdgpu_device_ip_set_clockgating_state(void *dev,
322 enum amd_ip_block_type block_type,
323 enum amd_clockgating_state state);
324int amdgpu_device_ip_set_powergating_state(void *dev,
325 enum amd_ip_block_type block_type,
326 enum amd_powergating_state state);
327void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
328 u32 *flags);
329int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
330 enum amd_ip_block_type block_type);
331bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
332 enum amd_ip_block_type block_type);
333
334#define AMDGPU_MAX_IP_NUM 16
335
336struct amdgpu_ip_block_status {
337 bool valid;
338 bool sw;
339 bool hw;
340 bool late_initialized;
341 bool hang;
342};
343
344struct amdgpu_ip_block_version {
345 const enum amd_ip_block_type type;
346 const u32 major;
347 const u32 minor;
348 const u32 rev;
349 const struct amd_ip_funcs *funcs;
350};
351
352#define HW_REV(_Major, _Minor, _Rev) \
353 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
354
355struct amdgpu_ip_block {
356 struct amdgpu_ip_block_status status;
357 const struct amdgpu_ip_block_version *version;
358};
359
360int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
361 enum amd_ip_block_type type,
362 u32 major, u32 minor);
363
364struct amdgpu_ip_block *
365amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
366 enum amd_ip_block_type type);
367
368int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
369 const struct amdgpu_ip_block_version *ip_block_version);
370
371/*
372 * BIOS.
373 */
374bool amdgpu_get_bios(struct amdgpu_device *adev);
375bool amdgpu_read_bios(struct amdgpu_device *adev);
376
377/*
378 * Clocks
379 */
380
381#define AMDGPU_MAX_PPLL 3
382
383struct amdgpu_clock {
384 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
385 struct amdgpu_pll spll;
386 struct amdgpu_pll mpll;
387 /* 10 Khz units */
388 uint32_t default_mclk;
389 uint32_t default_sclk;
390 uint32_t default_dispclk;
391 uint32_t current_dispclk;
392 uint32_t dp_extclk;
393 uint32_t max_pixel_clock;
394};
395
396/* sub-allocation manager, it has to be protected by another lock.
397 * By conception this is an helper for other part of the driver
398 * like the indirect buffer or semaphore, which both have their
399 * locking.
400 *
401 * Principe is simple, we keep a list of sub allocation in offset
402 * order (first entry has offset == 0, last entry has the highest
403 * offset).
404 *
405 * When allocating new object we first check if there is room at
406 * the end total_size - (last_object_offset + last_object_size) >=
407 * alloc_size. If so we allocate new object there.
408 *
409 * When there is not enough room at the end, we start waiting for
410 * each sub object until we reach object_offset+object_size >=
411 * alloc_size, this object then become the sub object we return.
412 *
413 * Alignment can't be bigger than page size.
414 *
415 * Hole are not considered for allocation to keep things simple.
416 * Assumption is that there won't be hole (all object on same
417 * alignment).
418 */
419
420#define AMDGPU_SA_NUM_FENCE_LISTS 32
421
422struct amdgpu_sa_manager {
423 wait_queue_head_t wq;
424 struct amdgpu_bo *bo;
425 struct list_head *hole;
426 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
427 struct list_head olist;
428 unsigned size;
429 uint64_t gpu_addr;
430 void *cpu_ptr;
431 uint32_t domain;
432 uint32_t align;
433};
434
435/* sub-allocation buffer */
436struct amdgpu_sa_bo {
437 struct list_head olist;
438 struct list_head flist;
439 struct amdgpu_sa_manager *manager;
440 unsigned soffset;
441 unsigned eoffset;
442 struct dma_fence *fence;
443};
444
445int amdgpu_fence_slab_init(void);
446void amdgpu_fence_slab_fini(void);
447
448/*
449 * IRQS.
450 */
451
452struct amdgpu_flip_work {
453 struct delayed_work flip_work;
454 struct work_struct unpin_work;
455 struct amdgpu_device *adev;
456 int crtc_id;
457 u32 target_vblank;
458 uint64_t base;
459 struct drm_pending_vblank_event *event;
460 struct amdgpu_bo *old_abo;
461 struct dma_fence *excl;
462 unsigned shared_count;
463 struct dma_fence **shared;
464 struct dma_fence_cb cb;
465 bool async;
466};
467
468
469/*
470 * CP & rings.
471 */
472
473struct amdgpu_ib {
474 struct amdgpu_sa_bo *sa_bo;
475 uint32_t length_dw;
476 uint64_t gpu_addr;
477 uint32_t *ptr;
478 uint32_t flags;
479};
480
481extern const struct drm_sched_backend_ops amdgpu_sched_ops;
482
483/*
484 * file private structure
485 */
486
487struct amdgpu_fpriv {
488 struct amdgpu_vm vm;
489 struct amdgpu_bo_va *prt_va;
490 struct amdgpu_bo_va *csa_va;
491 struct mutex bo_list_lock;
492 struct idr bo_list_handles;
493 struct amdgpu_ctx_mgr ctx_mgr;
494};
495
496int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
497
498int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
499 unsigned size,
500 enum amdgpu_ib_pool_type pool,
501 struct amdgpu_ib *ib);
502void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
503 struct dma_fence *f);
504int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
505 struct amdgpu_ib *ibs, struct amdgpu_job *job,
506 struct dma_fence **f);
507int amdgpu_ib_pool_init(struct amdgpu_device *adev);
508void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
509int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
510
511/*
512 * CS.
513 */
514struct amdgpu_cs_chunk {
515 uint32_t chunk_id;
516 uint32_t length_dw;
517 void *kdata;
518};
519
520struct amdgpu_cs_post_dep {
521 struct drm_syncobj *syncobj;
522 struct dma_fence_chain *chain;
523 u64 point;
524};
525
526struct amdgpu_cs_parser {
527 struct amdgpu_device *adev;
528 struct drm_file *filp;
529 struct amdgpu_ctx *ctx;
530
531 /* chunks */
532 unsigned nchunks;
533 struct amdgpu_cs_chunk *chunks;
534
535 /* scheduler job object */
536 struct amdgpu_job *job;
537 struct drm_sched_entity *entity;
538
539 /* buffer objects */
540 struct ww_acquire_ctx ticket;
541 struct amdgpu_bo_list *bo_list;
542 struct amdgpu_mn *mn;
543 struct amdgpu_bo_list_entry vm_pd;
544 struct list_head validated;
545 struct dma_fence *fence;
546 uint64_t bytes_moved_threshold;
547 uint64_t bytes_moved_vis_threshold;
548 uint64_t bytes_moved;
549 uint64_t bytes_moved_vis;
550
551 /* user fence */
552 struct amdgpu_bo_list_entry uf_entry;
553
554 unsigned num_post_deps;
555 struct amdgpu_cs_post_dep *post_deps;
556};
557
558static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
559 uint32_t ib_idx, int idx)
560{
561 return p->job->ibs[ib_idx].ptr[idx];
562}
563
564static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
565 uint32_t ib_idx, int idx,
566 uint32_t value)
567{
568 p->job->ibs[ib_idx].ptr[idx] = value;
569}
570
571/*
572 * Writeback
573 */
574#define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
575
576struct amdgpu_wb {
577 struct amdgpu_bo *wb_obj;
578 volatile uint32_t *wb;
579 uint64_t gpu_addr;
580 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
581 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
582};
583
584int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
585void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
586
587/*
588 * Benchmarking
589 */
590void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
591
592
593/*
594 * Testing
595 */
596void amdgpu_test_moves(struct amdgpu_device *adev);
597
598/*
599 * ASIC specific register table accessible by UMD
600 */
601struct amdgpu_allowed_register_entry {
602 uint32_t reg_offset;
603 bool grbm_indexed;
604};
605
606enum amd_reset_method {
607 AMD_RESET_METHOD_NONE = -1,
608 AMD_RESET_METHOD_LEGACY = 0,
609 AMD_RESET_METHOD_MODE0,
610 AMD_RESET_METHOD_MODE1,
611 AMD_RESET_METHOD_MODE2,
612 AMD_RESET_METHOD_BACO,
613 AMD_RESET_METHOD_PCI,
614};
615
616struct amdgpu_video_codec_info {
617 u32 codec_type;
618 u32 max_width;
619 u32 max_height;
620 u32 max_pixels_per_frame;
621 u32 max_level;
622};
623
624#define codec_info_build(type, width, height, level) \
625 .codec_type = type,\
626 .max_width = width,\
627 .max_height = height,\
628 .max_pixels_per_frame = height * width,\
629 .max_level = level,
630
631struct amdgpu_video_codecs {
632 const u32 codec_count;
633 const struct amdgpu_video_codec_info *codec_array;
634};
635
636/*
637 * ASIC specific functions.
638 */
639struct amdgpu_asic_funcs {
640 bool (*read_disabled_bios)(struct amdgpu_device *adev);
641 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
642 u8 *bios, u32 length_bytes);
643 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
644 u32 sh_num, u32 reg_offset, u32 *value);
645 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
646 int (*reset)(struct amdgpu_device *adev);
647 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
648 /* get the reference clock */
649 u32 (*get_xclk)(struct amdgpu_device *adev);
650 /* MM block clocks */
651 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
652 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
653 /* static power management */
654 int (*get_pcie_lanes)(struct amdgpu_device *adev);
655 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
656 /* get config memsize register */
657 u32 (*get_config_memsize)(struct amdgpu_device *adev);
658 /* flush hdp write queue */
659 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
660 /* invalidate hdp read cache */
661 void (*invalidate_hdp)(struct amdgpu_device *adev,
662 struct amdgpu_ring *ring);
663 /* check if the asic needs a full reset of if soft reset will work */
664 bool (*need_full_reset)(struct amdgpu_device *adev);
665 /* initialize doorbell layout for specific asic*/
666 void (*init_doorbell_index)(struct amdgpu_device *adev);
667 /* PCIe bandwidth usage */
668 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
669 uint64_t *count1);
670 /* do we need to reset the asic at init time (e.g., kexec) */
671 bool (*need_reset_on_init)(struct amdgpu_device *adev);
672 /* PCIe replay counter */
673 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
674 /* device supports BACO */
675 bool (*supports_baco)(struct amdgpu_device *adev);
676 /* pre asic_init quirks */
677 void (*pre_asic_init)(struct amdgpu_device *adev);
678 /* enter/exit umd stable pstate */
679 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
680 /* query video codecs */
681 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
682 const struct amdgpu_video_codecs **codecs);
683};
684
685/*
686 * IOCTL.
687 */
688int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
689 struct drm_file *filp);
690
691int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
692int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
693 struct drm_file *filp);
694int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
695int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
696 struct drm_file *filp);
697
698/* VRAM scratch page for HDP bug, default vram page */
699struct amdgpu_vram_scratch {
700 struct amdgpu_bo *robj;
701 volatile uint32_t *ptr;
702 u64 gpu_addr;
703};
704
705/*
706 * CGS
707 */
708struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
709void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
710
711/*
712 * Core structure, functions and helpers.
713 */
714typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
715typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
716
717typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
718typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
719
720typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
721typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
722
723struct amdgpu_mmio_remap {
724 u32 reg_offset;
725 resource_size_t bus_addr;
726};
727
728/* Define the HW IP blocks will be used in driver , add more if necessary */
729enum amd_hw_ip_block_type {
730 GC_HWIP = 1,
731 HDP_HWIP,
732 SDMA0_HWIP,
733 SDMA1_HWIP,
734 SDMA2_HWIP,
735 SDMA3_HWIP,
736 SDMA4_HWIP,
737 SDMA5_HWIP,
738 SDMA6_HWIP,
739 SDMA7_HWIP,
740 MMHUB_HWIP,
741 ATHUB_HWIP,
742 NBIO_HWIP,
743 MP0_HWIP,
744 MP1_HWIP,
745 UVD_HWIP,
746 VCN_HWIP = UVD_HWIP,
747 JPEG_HWIP = VCN_HWIP,
748 VCN1_HWIP,
749 VCE_HWIP,
750 DF_HWIP,
751 DCE_HWIP,
752 OSSSYS_HWIP,
753 SMUIO_HWIP,
754 PWR_HWIP,
755 NBIF_HWIP,
756 THM_HWIP,
757 CLK_HWIP,
758 UMC_HWIP,
759 RSMU_HWIP,
760 XGMI_HWIP,
761 DCI_HWIP,
762 MAX_HWIP
763};
764
765#define HWIP_MAX_INSTANCE 10
766
767#define HW_ID_MAX 300
768#define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
769
770struct amd_powerplay {
771 void *pp_handle;
772 const struct amd_pm_funcs *pp_funcs;
773};
774
775/* polaris10 kickers */
776#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
777 ((rid == 0xE3) || \
778 (rid == 0xE4) || \
779 (rid == 0xE5) || \
780 (rid == 0xE7) || \
781 (rid == 0xEF))) || \
782 ((did == 0x6FDF) && \
783 ((rid == 0xE7) || \
784 (rid == 0xEF) || \
785 (rid == 0xFF))))
786
787#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
788 ((rid == 0xE1) || \
789 (rid == 0xF7)))
790
791/* polaris11 kickers */
792#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
793 ((rid == 0xE0) || \
794 (rid == 0xE5))) || \
795 ((did == 0x67FF) && \
796 ((rid == 0xCF) || \
797 (rid == 0xEF) || \
798 (rid == 0xFF))))
799
800#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
801 ((rid == 0xE2)))
802
803/* polaris12 kickers */
804#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
805 ((rid == 0xC0) || \
806 (rid == 0xC1) || \
807 (rid == 0xC3) || \
808 (rid == 0xC7))) || \
809 ((did == 0x6981) && \
810 ((rid == 0x00) || \
811 (rid == 0x01) || \
812 (rid == 0x10))))
813
814#define AMDGPU_RESET_MAGIC_NUM 64
815#define AMDGPU_MAX_DF_PERFMONS 4
816struct amdgpu_device {
817 struct device *dev;
818 struct pci_dev *pdev;
819 struct drm_device ddev;
820
821#ifdef CONFIG_DRM_AMD_ACP
822 struct amdgpu_acp acp;
823#endif
824 struct amdgpu_hive_info *hive;
825 /* ASIC */
826 enum amd_asic_type asic_type;
827 uint32_t family;
828 uint32_t rev_id;
829 uint32_t external_rev_id;
830 unsigned long flags;
831 unsigned long apu_flags;
832 int usec_timeout;
833 const struct amdgpu_asic_funcs *asic_funcs;
834 bool shutdown;
835 bool need_swiotlb;
836 bool accel_working;
837 struct notifier_block acpi_nb;
838 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
839 struct debugfs_blob_wrapper debugfs_vbios_blob;
840 struct debugfs_blob_wrapper debugfs_discovery_blob;
841 struct mutex srbm_mutex;
842 /* GRBM index mutex. Protects concurrent access to GRBM index */
843 struct mutex grbm_idx_mutex;
844 struct dev_pm_domain vga_pm_domain;
845 bool have_disp_power_ref;
846 bool have_atomics_support;
847
848 /* BIOS */
849 bool is_atom_fw;
850 uint8_t *bios;
851 uint32_t bios_size;
852 uint32_t bios_scratch_reg_offset;
853 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
854
855 /* Register/doorbell mmio */
856 resource_size_t rmmio_base;
857 resource_size_t rmmio_size;
858 void __iomem *rmmio;
859 /* protects concurrent MM_INDEX/DATA based register access */
860 spinlock_t mmio_idx_lock;
861 struct amdgpu_mmio_remap rmmio_remap;
862 /* protects concurrent SMC based register access */
863 spinlock_t smc_idx_lock;
864 amdgpu_rreg_t smc_rreg;
865 amdgpu_wreg_t smc_wreg;
866 /* protects concurrent PCIE register access */
867 spinlock_t pcie_idx_lock;
868 amdgpu_rreg_t pcie_rreg;
869 amdgpu_wreg_t pcie_wreg;
870 amdgpu_rreg_t pciep_rreg;
871 amdgpu_wreg_t pciep_wreg;
872 amdgpu_rreg64_t pcie_rreg64;
873 amdgpu_wreg64_t pcie_wreg64;
874 /* protects concurrent UVD register access */
875 spinlock_t uvd_ctx_idx_lock;
876 amdgpu_rreg_t uvd_ctx_rreg;
877 amdgpu_wreg_t uvd_ctx_wreg;
878 /* protects concurrent DIDT register access */
879 spinlock_t didt_idx_lock;
880 amdgpu_rreg_t didt_rreg;
881 amdgpu_wreg_t didt_wreg;
882 /* protects concurrent gc_cac register access */
883 spinlock_t gc_cac_idx_lock;
884 amdgpu_rreg_t gc_cac_rreg;
885 amdgpu_wreg_t gc_cac_wreg;
886 /* protects concurrent se_cac register access */
887 spinlock_t se_cac_idx_lock;
888 amdgpu_rreg_t se_cac_rreg;
889 amdgpu_wreg_t se_cac_wreg;
890 /* protects concurrent ENDPOINT (audio) register access */
891 spinlock_t audio_endpt_idx_lock;
892 amdgpu_block_rreg_t audio_endpt_rreg;
893 amdgpu_block_wreg_t audio_endpt_wreg;
894 struct amdgpu_doorbell doorbell;
895
896 /* clock/pll info */
897 struct amdgpu_clock clock;
898
899 /* MC */
900 struct amdgpu_gmc gmc;
901 struct amdgpu_gart gart;
902 dma_addr_t dummy_page_addr;
903 struct amdgpu_vm_manager vm_manager;
904 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
905 unsigned num_vmhubs;
906
907 /* memory management */
908 struct amdgpu_mman mman;
909 struct amdgpu_vram_scratch vram_scratch;
910 struct amdgpu_wb wb;
911 atomic64_t num_bytes_moved;
912 atomic64_t num_evictions;
913 atomic64_t num_vram_cpu_page_faults;
914 atomic_t gpu_reset_counter;
915 atomic_t vram_lost_counter;
916
917 /* data for buffer migration throttling */
918 struct {
919 spinlock_t lock;
920 s64 last_update_us;
921 s64 accum_us; /* accumulated microseconds */
922 s64 accum_us_vis; /* for visible VRAM */
923 u32 log2_max_MBps;
924 } mm_stats;
925
926 /* display */
927 bool enable_virtual_display;
928 struct amdgpu_vkms_output *amdgpu_vkms_output;
929 struct amdgpu_mode_info mode_info;
930 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
931 struct work_struct hotplug_work;
932 struct amdgpu_irq_src crtc_irq;
933 struct amdgpu_irq_src vline0_irq;
934 struct amdgpu_irq_src vupdate_irq;
935 struct amdgpu_irq_src pageflip_irq;
936 struct amdgpu_irq_src hpd_irq;
937 struct amdgpu_irq_src dmub_trace_irq;
938 struct amdgpu_irq_src dmub_outbox_irq;
939
940 /* rings */
941 u64 fence_context;
942 unsigned num_rings;
943 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
944 bool ib_pool_ready;
945 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
946 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
947
948 /* interrupts */
949 struct amdgpu_irq irq;
950
951 /* powerplay */
952 struct amd_powerplay powerplay;
953 bool pp_force_state_enabled;
954
955 /* smu */
956 struct smu_context smu;
957
958 /* dpm */
959 struct amdgpu_pm pm;
960 u32 cg_flags;
961 u32 pg_flags;
962
963 /* nbio */
964 struct amdgpu_nbio nbio;
965
966 /* hdp */
967 struct amdgpu_hdp hdp;
968
969 /* smuio */
970 struct amdgpu_smuio smuio;
971
972 /* mmhub */
973 struct amdgpu_mmhub mmhub;
974
975 /* gfxhub */
976 struct amdgpu_gfxhub gfxhub;
977
978 /* gfx */
979 struct amdgpu_gfx gfx;
980
981 /* sdma */
982 struct amdgpu_sdma sdma;
983
984 /* uvd */
985 struct amdgpu_uvd uvd;
986
987 /* vce */
988 struct amdgpu_vce vce;
989
990 /* vcn */
991 struct amdgpu_vcn vcn;
992
993 /* jpeg */
994 struct amdgpu_jpeg jpeg;
995
996 /* firmwares */
997 struct amdgpu_firmware firmware;
998
999 /* PSP */
1000 struct psp_context psp;
1001
1002 /* GDS */
1003 struct amdgpu_gds gds;
1004
1005 /* KFD */
1006 struct amdgpu_kfd_dev kfd;
1007
1008 /* UMC */
1009 struct amdgpu_umc umc;
1010
1011 /* display related functionality */
1012 struct amdgpu_display_manager dm;
1013
1014 /* mes */
1015 bool enable_mes;
1016 struct amdgpu_mes mes;
1017
1018 /* df */
1019 struct amdgpu_df df;
1020
1021 /* MCA */
1022 struct amdgpu_mca mca;
1023
1024 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1025 uint32_t harvest_ip_mask;
1026 int num_ip_blocks;
1027 struct mutex mn_lock;
1028 DECLARE_HASHTABLE(mn_hash, 7);
1029
1030 /* tracking pinned memory */
1031 atomic64_t vram_pin_size;
1032 atomic64_t visible_pin_size;
1033 atomic64_t gart_pin_size;
1034
1035 /* soc15 register offset based on ip, instance and segment */
1036 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1037
1038 /* delayed work_func for deferring clockgating during resume */
1039 struct delayed_work delayed_init_work;
1040
1041 struct amdgpu_virt virt;
1042
1043 /* link all shadow bo */
1044 struct list_head shadow_list;
1045 struct mutex shadow_list_lock;
1046
1047 /* record hw reset is performed */
1048 bool has_hw_reset;
1049 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1050
1051 /* s3/s4 mask */
1052 bool in_suspend;
1053 bool in_s3;
1054 bool in_s4;
1055 bool in_s0ix;
1056
1057 atomic_t in_gpu_reset;
1058 enum pp_mp1_state mp1_state;
1059 struct rw_semaphore reset_sem;
1060 struct amdgpu_doorbell_index doorbell_index;
1061
1062 struct mutex notifier_lock;
1063
1064 int asic_reset_res;
1065 struct work_struct xgmi_reset_work;
1066 struct list_head reset_list;
1067
1068 long gfx_timeout;
1069 long sdma_timeout;
1070 long video_timeout;
1071 long compute_timeout;
1072
1073 uint64_t unique_id;
1074 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1075
1076 /* enable runtime pm on the device */
1077 bool runpm;
1078 bool in_runpm;
1079 bool has_pr3;
1080
1081 bool pm_sysfs_en;
1082 bool ucode_sysfs_en;
1083
1084 /* Chip product information */
1085 char product_number[16];
1086 char product_name[32];
1087 char serial[20];
1088
1089 atomic_t throttling_logging_enabled;
1090 struct ratelimit_state throttling_logging_rs;
1091 uint32_t ras_hw_enabled;
1092 uint32_t ras_enabled;
1093
1094 bool no_hw_access;
1095 struct pci_saved_state *pci_state;
1096 pci_channel_state_t pci_channel_state;
1097
1098 struct amdgpu_reset_control *reset_cntl;
1099 uint32_t ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
1100};
1101
1102static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1103{
1104 return container_of(ddev, struct amdgpu_device, ddev);
1105}
1106
1107static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1108{
1109 return &adev->ddev;
1110}
1111
1112static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1113{
1114 return container_of(bdev, struct amdgpu_device, mman.bdev);
1115}
1116
1117int amdgpu_device_init(struct amdgpu_device *adev,
1118 uint32_t flags);
1119void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1120void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1121
1122int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1123
1124void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1125 void *buf, size_t size, bool write);
1126size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1127 void *buf, size_t size, bool write);
1128
1129void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1130 void *buf, size_t size, bool write);
1131uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1132 uint32_t reg, uint32_t acc_flags);
1133void amdgpu_device_wreg(struct amdgpu_device *adev,
1134 uint32_t reg, uint32_t v,
1135 uint32_t acc_flags);
1136void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1137 uint32_t reg, uint32_t v);
1138void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1139uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1140
1141u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1142 u32 pcie_index, u32 pcie_data,
1143 u32 reg_addr);
1144u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1145 u32 pcie_index, u32 pcie_data,
1146 u32 reg_addr);
1147void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1148 u32 pcie_index, u32 pcie_data,
1149 u32 reg_addr, u32 reg_data);
1150void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1151 u32 pcie_index, u32 pcie_data,
1152 u32 reg_addr, u64 reg_data);
1153
1154bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1155bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1156
1157int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1158 struct amdgpu_reset_context *reset_context);
1159
1160int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1161 struct amdgpu_reset_context *reset_context);
1162
1163int emu_soc_asic_init(struct amdgpu_device *adev);
1164
1165/*
1166 * Registers read & write functions.
1167 */
1168#define AMDGPU_REGS_NO_KIQ (1<<1)
1169#define AMDGPU_REGS_RLC (1<<2)
1170
1171#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1172#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1173
1174#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1175#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1176
1177#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1178#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1179
1180#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1181#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1182#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1183#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1184#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1185#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1186#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1187#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1188#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1189#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1190#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1191#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1192#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1193#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1194#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1195#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1196#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1197#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1198#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1199#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1200#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1201#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1202#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1203#define WREG32_P(reg, val, mask) \
1204 do { \
1205 uint32_t tmp_ = RREG32(reg); \
1206 tmp_ &= (mask); \
1207 tmp_ |= ((val) & ~(mask)); \
1208 WREG32(reg, tmp_); \
1209 } while (0)
1210#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1211#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1212#define WREG32_PLL_P(reg, val, mask) \
1213 do { \
1214 uint32_t tmp_ = RREG32_PLL(reg); \
1215 tmp_ &= (mask); \
1216 tmp_ |= ((val) & ~(mask)); \
1217 WREG32_PLL(reg, tmp_); \
1218 } while (0)
1219
1220#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1221 do { \
1222 u32 tmp = RREG32_SMC(_Reg); \
1223 tmp &= (_Mask); \
1224 tmp |= ((_Val) & ~(_Mask)); \
1225 WREG32_SMC(_Reg, tmp); \
1226 } while (0)
1227
1228#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1229
1230#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1231#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1232
1233#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1234 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1235 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1236
1237#define REG_GET_FIELD(value, reg, field) \
1238 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1239
1240#define WREG32_FIELD(reg, field, val) \
1241 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1242
1243#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1244 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1245
1246/*
1247 * BIOS helpers.
1248 */
1249#define RBIOS8(i) (adev->bios[i])
1250#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1251#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1252
1253/*
1254 * ASICs macro.
1255 */
1256#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1257#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1258#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1259#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1260#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1261#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1262#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1263#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1264#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1265#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1266#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1267#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1268#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1269#define amdgpu_asic_flush_hdp(adev, r) \
1270 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1271#define amdgpu_asic_invalidate_hdp(adev, r) \
1272 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r)))
1273#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1274#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1275#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1276#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1277#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1278#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1279#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1280#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1281 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1282#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1283
1284#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1285
1286#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
1287
1288/* Common functions */
1289bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1290bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1291int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1292 struct amdgpu_job* job);
1293void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1294int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1295bool amdgpu_device_need_post(struct amdgpu_device *adev);
1296
1297void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1298 u64 num_vis_bytes);
1299int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1300void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1301 const u32 *registers,
1302 const u32 array_size);
1303
1304int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1305bool amdgpu_device_supports_atpx(struct drm_device *dev);
1306bool amdgpu_device_supports_px(struct drm_device *dev);
1307bool amdgpu_device_supports_boco(struct drm_device *dev);
1308bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1309bool amdgpu_device_supports_baco(struct drm_device *dev);
1310bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1311 struct amdgpu_device *peer_adev);
1312int amdgpu_device_baco_enter(struct drm_device *dev);
1313int amdgpu_device_baco_exit(struct drm_device *dev);
1314
1315void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1316 struct amdgpu_ring *ring);
1317void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1318 struct amdgpu_ring *ring);
1319
1320/* atpx handler */
1321#if defined(CONFIG_VGA_SWITCHEROO)
1322void amdgpu_register_atpx_handler(void);
1323void amdgpu_unregister_atpx_handler(void);
1324bool amdgpu_has_atpx_dgpu_power_cntl(void);
1325bool amdgpu_is_atpx_hybrid(void);
1326bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1327bool amdgpu_has_atpx(void);
1328#else
1329static inline void amdgpu_register_atpx_handler(void) {}
1330static inline void amdgpu_unregister_atpx_handler(void) {}
1331static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1332static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1333static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1334static inline bool amdgpu_has_atpx(void) { return false; }
1335#endif
1336
1337#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1338void *amdgpu_atpx_get_dhandle(void);
1339#else
1340static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1341#endif
1342
1343/*
1344 * KMS
1345 */
1346extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1347extern const int amdgpu_max_kms_ioctl;
1348
1349int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1350void amdgpu_driver_unload_kms(struct drm_device *dev);
1351void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1352int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1353void amdgpu_driver_postclose_kms(struct drm_device *dev,
1354 struct drm_file *file_priv);
1355void amdgpu_driver_release_kms(struct drm_device *dev);
1356
1357int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1358int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1359int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1360u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1361int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1362void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1363long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1364 unsigned long arg);
1365int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1366 struct drm_file *filp);
1367
1368/*
1369 * functions used by amdgpu_encoder.c
1370 */
1371struct amdgpu_afmt_acr {
1372 u32 clock;
1373
1374 int n_32khz;
1375 int cts_32khz;
1376
1377 int n_44_1khz;
1378 int cts_44_1khz;
1379
1380 int n_48khz;
1381 int cts_48khz;
1382
1383};
1384
1385struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1386
1387/* amdgpu_acpi.c */
1388
1389/* ATCS Device/Driver State */
1390#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1391#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1392#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1393#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1394
1395#if defined(CONFIG_ACPI)
1396int amdgpu_acpi_init(struct amdgpu_device *adev);
1397void amdgpu_acpi_fini(struct amdgpu_device *adev);
1398bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1399bool amdgpu_acpi_is_power_shift_control_supported(void);
1400int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1401 u8 perf_req, bool advertise);
1402int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1403 u8 dev_state, bool drv_state);
1404int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1405int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1406
1407void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1408bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1409void amdgpu_acpi_detect(void);
1410#else
1411static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1412static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1413static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1414static inline void amdgpu_acpi_detect(void) { }
1415static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1416static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1417 u8 dev_state, bool drv_state) { return 0; }
1418static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1419 enum amdgpu_ss ss_state) { return 0; }
1420#endif
1421
1422int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1423 uint64_t addr, struct amdgpu_bo **bo,
1424 struct amdgpu_bo_va_mapping **mapping);
1425
1426#if defined(CONFIG_DRM_AMD_DC)
1427int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1428#else
1429static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1430#endif
1431
1432
1433void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1434void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1435
1436pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1437 pci_channel_state_t state);
1438pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1439pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1440void amdgpu_pci_resume(struct pci_dev *pdev);
1441
1442bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1443bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1444
1445bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1446
1447int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1448 enum amd_clockgating_state state);
1449int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1450 enum amd_powergating_state state);
1451
1452#include "amdgpu_object.h"
1453
1454static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1455{
1456 return adev->gmc.tmz_enabled;
1457}
1458
1459static inline int amdgpu_in_reset(struct amdgpu_device *adev)
1460{
1461 return atomic_read(&adev->in_gpu_reset);
1462}
1463#endif