A game about forced loneliness, made by TACStudios
tacstudios.tngl.sh
1using System;
2using System.Linq;
3
4namespace Unity.Burst.Editor
5{
6 internal partial class BurstDisassembler
7 {
8 internal class ARM64InstructionInfo
9 {
10 internal static bool GetARM64Info(string instructionName, out string instructionInfo)
11 {
12 var instr = ARM64AsmTokenKindProvider.TryRemoveT(new StringSlice(instructionName));
13 var retVal = TryFindInstructionInfo(instr, out instructionInfo);
14
15 if (retVal)
16 {
17 return retVal;
18 }
19
20 // Could not find info, so try and remove possible instruction condition code.
21 instr = ARM64AsmTokenKindProvider.TryRemoveCond(instr);
22 return TryFindInstructionInfo(instr, out instructionInfo);
23 }
24
25 private static bool TryFindInstructionInfo(StringSlice instr, out string instructionInfo)
26 {
27 var returnValue = true;
28
29 switch (instr.ToString())
30 {
31 case "bkpt":
32 instructionInfo = "Functions as breakpoint by causing the core to enter Debug state.";
33 break;
34 case "usat":
35 instructionInfo = "Unsigned saturate to any bit position, with optional shift before saturating.";
36 break;
37 case "stmia":
38 case "stm":
39 instructionInfo = "Store multiple registers incrementing address after each transfer.";
40 break;
41 case "stmib":
42 instructionInfo = "Store multiple registers incrementing address before each transfer.";
43 break;
44 case "stmda":
45 instructionInfo = "Store multiple registers decrement address after each transfer.";
46 break;
47 case "stmdb":
48 instructionInfo = "Store multiple registers decrement address before each transfer.";
49 break;
50 case "ldmia":
51 case "ldm":
52 instructionInfo = "Load multiple registers incrementing address after each transfer.";
53 break;
54 case "ldmib":
55 instructionInfo = "Load multiple registers incrementing address before each transfer.";
56 break;
57 case "ldmda":
58 instructionInfo = "Load multiple registers decrement address after each transfer.";
59 break;
60 case "ldmdb":
61 instructionInfo = "Load multiple registers decrement addres before each transfer.";
62 break;
63 case "adc":
64 instructionInfo = "Add with Carry.";
65 break;
66 case "add":
67 case "addw":
68 instructionInfo = "Add.";
69 break;
70 case "adds":
71 instructionInfo = "Add, setting flags.";
72 break;
73 case "vadd":
74 instructionInfo = "Adds corresponding elements of two vectors.";
75 break;
76 case "vaddl":
77 instructionInfo = "Vector add long.";
78 break;
79 case "vaddw":
80 instructionInfo = "Vector add wide.";
81 break;
82 case "adr":
83 instructionInfo = "Form PC-relative address.";
84 break;
85 case "adrl":
86 instructionInfo = "Loads a program or register-relative address.";
87 break;
88 case "adrp":
89 instructionInfo = "Form PC-relative address to 4KB page.";
90 break;
91 case "and":
92 instructionInfo = "Bitwise AND.";
93 break;
94 case "asr":
95 instructionInfo = "Arithmetic Shift Right.";
96 break;
97 case "asrs":
98 instructionInfo = "Arithmetic Shift Right, setting flags.";
99 break;
100 case "uxtab":
101 instructionInfo = "Zero extend Byte and Add.";
102 break;
103 case "uxtah":
104 instructionInfo = "Zero extend Halfword and Add. Extends a 16-bit value to a 32-bit value.";
105 break;
106 case "at":
107 instructionInfo = "Address Translate.";
108 break;
109 case "it":
110 case "itt":
111 case "ittt":
112 case "itttt":
113 instructionInfo = "If-Then condition for the next #t instruction(s).";
114 break;
115 case "ite":
116 case "itte":
117 case "itee":
118 case "ittee":
119 case "ittte":
120 instructionInfo = "If-Then-Else condition running next #t instruction(s) if true and then " +
121 "the instruction thereafter if condition is false.";
122 break;
123 case "b":
124 instructionInfo = "Branch.";
125 break;
126 case "bfi":
127 instructionInfo = "Bitfield Insert.";
128 break;
129 case "bfm":
130 instructionInfo = "Bitfield Move.";
131 break;
132 case "bfxil":
133 instructionInfo = "Bitfield extract and insert at low end.";
134 break;
135 case "bic":
136 instructionInfo = "Bitwise Bit Clear.";
137 break;
138 case "bl":
139 instructionInfo = "Branch with Link.";
140 break;
141 case "blr":
142 instructionInfo = "Branch with Link to Register.";
143 break;
144 case "br":
145 instructionInfo = "Branch to Register.";
146 break;
147 case "brk":
148 instructionInfo = "Breakpoint instruction.";
149 break;
150 case "cbnz":
151 instructionInfo = "Compare and Branch on Nonzero.";
152 break;
153 case "cbz":
154 instructionInfo = "Compare and Branch on Zero.";
155 break;
156 case "ccmn":
157 instructionInfo = "Conditional Compare Negative.";
158 break;
159 case "ccmp":
160 instructionInfo = "Conditional Compare.";
161 break;
162 case "clrex":
163 instructionInfo = "Clear Exclusive.";
164 break;
165 case "cls":
166 instructionInfo = "Count leading sign bits.";
167 break;
168 case "clz":
169 instructionInfo = "Count leading zero bits.";
170 break;
171 case "cmn":
172 instructionInfo = "Compare Negative.";
173 break;
174 case "cmp":
175 instructionInfo = "Compare.";
176 break;
177 case "crc32b":
178 case "crc32h":
179 case "crc32w":
180 case "crc32x":
181 instructionInfo = "CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register.";
182 break;
183 case "crc32cb":
184 case "crc32ch":
185 case "crc32cw":
186 case "crc32cx":
187 instructionInfo = "CRC32C checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register.";
188 break;
189 case "csel":
190 instructionInfo = "Conditional Select.";
191 break;
192 case "csinc":
193 instructionInfo = "Conditional Select Increment.";
194 break;
195 case "csinv":
196 instructionInfo = "Conditional Select Invert.";
197 break;
198 case "csneg":
199 instructionInfo = "Conditional Select Negation.";
200 break;
201 case "dc":
202 instructionInfo = "Data Cache operation.";
203 break;
204 case "dcps1":
205 instructionInfo = "Debug Change PE State to EL1.";
206 break;
207 case "dcps2":
208 instructionInfo = "Debug Change PE State to EL2.";
209 break;
210 case "dcps3":
211 instructionInfo = "Debug Change PE State to EL3.";
212 break;
213 case "dmb":
214 instructionInfo = "Data Memory Barrier.";
215 break;
216 case "drps":
217 instructionInfo = "Debug restore process state.";
218 break;
219 case "dsb":
220 instructionInfo = "Data Synchronization Barrier.";
221 break;
222 case "eon":
223 instructionInfo = "Bitwise Exclusive OR NOT.";
224 break;
225 case "eor":
226 instructionInfo = "Bitwise Exclusive OR.";
227 break;
228 case "eors":
229 instructionInfo = "Bitwise Exclusive OR, setting flags.";
230 break;
231 case "eret":
232 instructionInfo = "Returns from an exception.";
233 break;
234 case "extr":
235 instructionInfo = "Extract register.";
236 break;
237 case "hint":
238 instructionInfo = "Hint instruction.";
239 break;
240 case "hlt":
241 instructionInfo = "Halt instruction.";
242 break;
243 case "hvc":
244 instructionInfo = "Hypervisor call to allow OS code to call the Hypervisor.";
245 break;
246 case "ic":
247 instructionInfo = "Instruction Cache operation.";
248 break;
249 case "isb":
250 instructionInfo = "Instruction Synchronization Barrier.";
251 break;
252 case "lsl":
253 instructionInfo = "Logical Shift Left.";
254 break;
255 case "lsls":
256 instructionInfo = "Logical Shift Left, setting flags.";
257 break;
258 case "lsr":
259 instructionInfo = "Logical Shift Right.";
260 break;
261 case "lsrs":
262 instructionInfo = "Logical Shift Right, setting flags.";
263 break;
264 case "smmul":
265 instructionInfo = "Signed Most significant word Multiply.";
266 break;
267 case "umaal":
268 instructionInfo = "Unsigned Multiply Accumulate Accumulate Long.";
269 break;
270 case "madd":
271 instructionInfo = "Multiply-Add.";
272 break;
273 case "mneg":
274 instructionInfo = "Multiply-Negate.";
275 break;
276 case "beq":
277 instructionInfo = "Conditional branch Equal.";
278 break;
279 case "bne":
280 instructionInfo = "Conditional branch Not equal.";
281 break;
282 case "bcs":
283 instructionInfo = "Conditional branch Carry set (identical to HS).";
284 break;
285 case "bhs":
286 instructionInfo = "Conditional branch Unsigned higher or same (identical to CS).";
287 break;
288 case "bcc":
289 instructionInfo = "Conditional branch Carry clear (identical to LO).";
290 break;
291 case "blo":
292 instructionInfo = "Conditional branch Unsigned lower (identical to CC).";
293 break;
294 case "bmi":
295 instructionInfo = "Conditional branch Minus or negative result.";
296 break;
297 case "bpl":
298 instructionInfo = "Conditional branch Positive or zero result.";
299 break;
300 case "bvs":
301 instructionInfo = "Conditional branch Overflow.";
302 break;
303 case "bvc":
304 instructionInfo = "Conditional branch No overflow.";
305 break;
306 case "bhi":
307 instructionInfo = "Conditional branch Unsigned higher.";
308 break;
309 case "bls":
310 instructionInfo = "Conditional branch Unsigned lower or same.";
311 break;
312 case "bge":
313 instructionInfo = "Conditional branch Signed greater than or equal.";
314 break;
315 case "blt":
316 instructionInfo = "Conditional branch Signed less than.";
317 break;
318 case "bgt":
319 instructionInfo = "Conditional branch Signed greater than.";
320 break;
321 case "ble":
322 instructionInfo = "Conditional branch Signed less than or equal.";
323 break;
324 case "bal":
325 instructionInfo = "Conditional branch Always (this is the default).";
326 break;
327 case "bnv":
328 instructionInfo = "Conditional branch No overflow.";
329 break;
330 case "bx":
331 instructionInfo = "Branch and exchange instruction set.";
332 break;
333 case "blx":
334 instructionInfo =
335 "transfers program execution to the address specified by label and stores the " +
336 "address of the next instruction in the LR (R14) register. BLX can change the core state from ARM to Thumb, or from Thumb to ARM.";
337 break;
338 case "bxj":
339 instructionInfo = "Branch and change Jazelle state. Jazelle state means the processor executes Java bytecodes.";
340 break;
341 case "mov":
342 instructionInfo = "Move.";
343 break;
344 case "movs":
345 instructionInfo = "Move, setting condition flags.";
346 break;
347 case "movl":
348 instructionInfo = "Load a register with eiter a 32-bit or 64-bit immediate value, or any adress.";
349 break;
350 case "vmov":
351 instructionInfo = "Inset a floating-point immediate value in a single-precision or double-precision register, or" +
352 "copy one register into another register.";
353 break;
354 case "movk":
355 instructionInfo = "Move wide with keep.";
356 break;
357 case "movn":
358 instructionInfo = "Move wide with NOT.";
359 break;
360 case "movz":
361 instructionInfo = "Move wide with zero.";
362 break;
363 case "movt":
364 instructionInfo = "Move to top half of register.";
365 break;
366 case "movw":
367 instructionInfo = "Move word.";
368 break;
369 case "mrs":
370 instructionInfo = "Move System Register.";
371 break;
372 case "msr":
373 instructionInfo = "Move immediate value to Special Register.";
374 break;
375 case "msub":
376 instructionInfo = "Multiply-Subtract.";
377 break;
378 case "mul":
379 instructionInfo = "Multiply.";
380 break;
381 case "muls":
382 instructionInfo = "Multiply, setting flags.";
383 break;
384 case "vmul":
385 instructionInfo = "Multiplies corresponding elements in two vectors, and places the results in the destination vector.";
386 break;
387 case "mvn":
388 instructionInfo = "Bitwise NOT.";
389 break;
390 case "mvns":
391 instructionInfo = "Bitwise NOT, setting flags.";
392 break;
393 case "neg":
394 instructionInfo = "Negate.";
395 break;
396 case "ngc":
397 instructionInfo = "Negate with Carry.";
398 break;
399 case "nop":
400 instructionInfo = "No Operation.";
401 break;
402 case "orn":
403 instructionInfo = "Bitwise OR NOT.";
404 break;
405 case "orr":
406 instructionInfo = "Bitwise OR.";
407 break;
408 case "orrs":
409 instructionInfo = "Bitwise OR, setting flags.";
410 break;
411 case "rbit":
412 instructionInfo = "Reverse Bits.";
413 break;
414 case "ret":
415 instructionInfo = "Return from subroutine.";
416 break;
417 case "rev16":
418 instructionInfo = "Reverse bytes in 16-bit halfwords.";
419 break;
420 case "rev32":
421 instructionInfo = "Reverse bytes in 32-bit words.";
422 break;
423 case "rev64":
424 instructionInfo = "Reverse Bytes.";
425 break;
426 case "rev":
427 instructionInfo = "Reverse Bytes.";
428 break;
429 case "rrx":
430 instructionInfo = "Rotate right with extend.";
431 break;
432 case "ror":
433 instructionInfo = "Rotate right.";
434 break;
435 case "sbc":
436 instructionInfo = "Subtract with Carry.";
437 break;
438 case "sbfiz":
439 instructionInfo = "Signed Bitfield Insert in Zero.";
440 break;
441 case "sbfm":
442 instructionInfo = "Signed Bitfield Move.";
443 break;
444 case "sbfx":
445 instructionInfo = "Signed Bitfield Extract.";
446 break;
447 case "sdiv":
448 instructionInfo = "Signed Divide.";
449 break;
450 case "sev":
451 instructionInfo = "Send Event.";
452 break;
453 case "sevl":
454 instructionInfo = "Send Event Local.";
455 break;
456 case "smaddl":
457 instructionInfo = "Signed Multiply-Add Long.";
458 break;
459 case "smc":
460 instructionInfo = "Supervisor call to allow OS or Hypervisor code to call the Secure Monitor.";
461 break;
462 case "smnegl":
463 instructionInfo = "Signed Multiply-Negate Long.";
464 break;
465 case "smsubl":
466 instructionInfo = "Signed Multiply-Subtract Long.";
467 break;
468 case "smulh":
469 instructionInfo = "Signed Multiply High.";
470 break;
471 case "smull":
472 instructionInfo = "Signed Multiply Long.";
473 break;
474 case "sub":
475 case "subw":
476 instructionInfo = "Subtract.";
477 break;
478 case "vsub":
479 instructionInfo = "Subtract the elements of one vector from the corresponding elements of another " +
480 "vector, and places the results in the destination vector.";
481 break;
482 case "subs":
483 instructionInfo = "Subtract (extended register), setting flags.";
484 break;
485 case "rsb":
486 instructionInfo = "Reverse subtract i.e. for \"rsb {Rd, } Rn, <Operand2>\" Rn is subtracted " +
487 "from operand2 and saved in Rd register.";
488 break;
489 case "rsbs":
490 instructionInfo = "Reverse subtract, setting flags, i.e. for \"rsb {Rd, } Rn, <Operand2>\" Rn is subtracted " +
491 "from operand2 and saved in Rd register.";
492 break;
493 case "svc":
494 instructionInfo = "Supervisor call to allow application code to call the OS.";
495 break;
496 case "sxtb":
497 instructionInfo = "Signed Extend Byte.";
498 break;
499 case "sxth":
500 instructionInfo = "Sign Extend Halfword.";
501 break;
502 case "sxtw":
503 instructionInfo = "Sign Extend Word.";
504 break;
505 case "sys":
506 instructionInfo = "System instruction.";
507 break;
508 case "sysl":
509 instructionInfo = "System instruction with result.";
510 break;
511 case "tbnz":
512 instructionInfo = "Test bit and Branch if Nonzero.";
513 break;
514 case "tbz":
515 instructionInfo = "Test bit and Branch if Zero.";
516 break;
517 case "tlbi":
518 instructionInfo = "TLB Invalidate operation.";
519 break;
520 case "tst":
521 instructionInfo = ", setting the condition flags and discarding the result.";
522 break;
523 case "ubfiz":
524 instructionInfo = "Unsigned Bitfield Insert in Zero.";
525 break;
526 case "ubfm":
527 instructionInfo = "Unsigned Bitfield Move.";
528 break;
529 case "ubfx":
530 instructionInfo = "Unsigned Bitfield Extract.";
531 break;
532 case "udiv":
533 instructionInfo = "Unsigned Divide.";
534 break;
535 case "umaddl":
536 instructionInfo = "Unsigned Multiply-Add Long.";
537 break;
538 case "umnegl":
539 instructionInfo = "Unsigned Multiply-Negate Long.";
540 break;
541 case "umsubl":
542 instructionInfo = "Unsigned Multiply-Subtract Long.";
543 break;
544 case "umulh":
545 instructionInfo = "Unsigned Multiply High.";
546 break;
547 case "umull":
548 instructionInfo = "Unsigned Multiply Long.";
549 break;
550 case "uxtb":
551 instructionInfo = "Unsigned Extend Byte.";
552 break;
553 case "uxth":
554 instructionInfo = "Unsigned Extend Halfword.";
555 break;
556 case "wfe":
557 instructionInfo = "Wait For Event.";
558 break;
559 case "wfi":
560 instructionInfo = "Wait For Interrupt.";
561 break;
562 case "yield":
563 instructionInfo = "YIELD.";
564 break;
565 case "ldar":
566 instructionInfo = "Load-Acquire Register.";
567 break;
568 case "ldarb":
569 instructionInfo = "Load-Acquire Register Byte.";
570 break;
571 case "ldarh":
572 instructionInfo = "Load-Acquire Register Halfword.";
573 break;
574 case "ldaxp":
575 instructionInfo = "Load-Acquire Exclusive Pair of Registers.";
576 break;
577 case "ldaxr":
578 instructionInfo = "Load-Acquire Exclusive Register.";
579 break;
580 case "ldaxrb":
581 instructionInfo = "Load-Acquire Exclusive Register Byte.";
582 break;
583 case "ldaxrh":
584 instructionInfo = "Load-Acquire Exclusive Register Halfword.";
585 break;
586 case "ldnp":
587 instructionInfo = "Load Pair of Registers, with non-temporal hint.";
588 break;
589 case "ldp":
590 instructionInfo = "Load Pair of Registers.";
591 break;
592 case "ldpsw":
593 instructionInfo = "Load Pair of Registers Signed Word.";
594 break;
595 case "ldr":
596 instructionInfo = "Load Register.";
597 break;
598 case "ldrb":
599 instructionInfo = "Load Register Byte.";
600 break;
601 case "ldrh":
602 instructionInfo = "Load Register Halfword.";
603 break;
604 case "ldrd":
605 instructionInfo = "Load Register double.";
606 break;
607 case "ldrsb":
608 instructionInfo = "Load Register Signed Byte.";
609 break;
610 case "ldrsh":
611 instructionInfo = "Load Register Signed Halfword.";
612 break;
613 case "ldrsw":
614 instructionInfo = "Load Register Signed Word.";
615 break;
616 case "ldtr":
617 instructionInfo = "Load Register.";
618 break;
619 case "ldtrb":
620 instructionInfo = "Load Register Byte.";
621 break;
622 case "ldtrh":
623 instructionInfo = "Load Register Halfword.";
624 break;
625 case "ldtrsb":
626 instructionInfo = "Load Register Signed Byte.";
627 break;
628 case "ldtrsh":
629 instructionInfo = "Load Register Signed Halfword.";
630 break;
631 case "ldtrsw":
632 instructionInfo = "Load Register Signed Word.";
633 break;
634 case "ldur":
635 instructionInfo = "Load Register.";
636 break;
637 case "ldurb":
638 instructionInfo = "Load Register Byte.";
639 break;
640 case "ldurh":
641 instructionInfo = "Load Register Halfword.";
642 break;
643 case "ldursb":
644 instructionInfo = "Load Register Signed Byte.";
645 break;
646 case "ldursh":
647 instructionInfo = "Load Register Signed Halfword.";
648 break;
649 case "ldursw":
650 instructionInfo = "Load Register Signed Word.";
651 break;
652 case "ldxp":
653 instructionInfo = "Load Exclusive Pair of Registers.";
654 break;
655 case "ldxr":
656 instructionInfo = "Load Exclusive Register.";
657 break;
658 case "ldxrb":
659 instructionInfo = "Load Exclusive Register Byte.";
660 break;
661 case "ldxrh":
662 instructionInfo = "Load Exclusive Register Halfword.";
663 break;
664 case "prfm":
665 instructionInfo = "Prefetch Memory.";
666 break;
667 case "prfum":
668 instructionInfo = "Prefetch Memory.";
669 break;
670 case "stlr":
671 instructionInfo = "Store-Release Register.";
672 break;
673 case "stlrb":
674 instructionInfo = "Store-Release Register Byte.";
675 break;
676 case "stlrh":
677 instructionInfo = "Store-Release Register Halfword.";
678 break;
679 case "stlxp":
680 instructionInfo = "Store-Release Exclusive Pair of registers.";
681 break;
682 case "stlxr":
683 instructionInfo = "Store-Release Exclusive Register.";
684 break;
685 case "stlxrb":
686 instructionInfo = "Store-Release Exclusive Register Byte.";
687 break;
688 case "stlxrh":
689 instructionInfo = "Store-Release Exclusive Register Halfword.";
690 break;
691 case "stnp":
692 instructionInfo = "Store Pair of Registers, with non-temporal hint.";
693 break;
694 case "stp":
695 instructionInfo = "Store Pair of Registers.";
696 break;
697 case "str":
698 instructionInfo = "Store Register.";
699 break;
700 case "strd":
701 instructionInfo = "Store register double.";
702 break;
703 case "strb":
704 instructionInfo = "Store Register Byte.";
705 break;
706 case "strh":
707 instructionInfo = "Store Register Halfword.";
708 break;
709 case "sttr":
710 instructionInfo = "Store Register.";
711 break;
712 case "sttrb":
713 instructionInfo = "Store Register Byte.";
714 break;
715 case "sttrh":
716 instructionInfo = "Store Register Halfword.";
717 break;
718 case "stur":
719 instructionInfo = "Store Register.";
720 break;
721 case "sturb":
722 instructionInfo = "Store Register Byte.";
723 break;
724 case "sturh":
725 instructionInfo = "Store Register Halfword.";
726 break;
727 case "stxp":
728 instructionInfo = "Store Exclusive Pair of registers.";
729 break;
730 case "stxr":
731 instructionInfo = "Store Exclusive Register.";
732 break;
733 case "stxrb":
734 instructionInfo = "Store Exclusive Register Byte.";
735 break;
736 case "stxrh":
737 instructionInfo = "Store Exclusive Register Halfword.";
738 break;
739 case "fabs":
740 instructionInfo = "Floating-point Absolute value.";
741 break;
742 case "fadd":
743 instructionInfo = "Floating-point Add.";
744 break;
745 case "fccmp":
746 instructionInfo = "Floating-point Conditional quiet Compare.";
747 break;
748 case "fccmpe":
749 instructionInfo = "Floating-point Conditional signaling Compare.";
750 break;
751 case "fcmp":
752 instructionInfo = "Floating-point quiet Compare.";
753 break;
754 case "fcmpe":
755 instructionInfo = "Floating-point signaling Compare.";
756 break;
757 case "fcsel":
758 instructionInfo = "Floating-point Conditional Select.";
759 break;
760 case "fcvt":
761 instructionInfo = "Floating-point Convert precision.";
762 break;
763 case "fcvtas":
764 instructionInfo = "Floating-point Convert to Signed integer, rounding to nearest with ties to Away.";
765 break;
766 case "fcvtau":
767 instructionInfo = "Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away.";
768 break;
769 case "fcvtms":
770 instructionInfo = "Floating-point Convert to Signed integer, rounding toward Minus infinity.";
771 break;
772 case "fcvtmu":
773 instructionInfo = "Floating-point Convert to Unsigned integer, rounding toward Minus infinity.";
774 break;
775 case "fcvtns":
776 instructionInfo = "Floating-point Convert to Signed integer, rounding to nearest with ties to even.";
777 break;
778 case "fcvtnu":
779 instructionInfo = "Floating-point Convert to Unsigned integer, rounding to nearest with ties to even.";
780 break;
781 case "fcvtps":
782 instructionInfo = "Floating-point Convert to Signed integer, rounding toward Plus infinity.";
783 break;
784 case "fcvtpu":
785 instructionInfo = "Floating-point Convert to Unsigned integer, rounding toward Plus infinity.";
786 break;
787 case "fcvtzs":
788 instructionInfo = "Floating-point Convert to Signed fixed-point, rounding toward Zero.";
789 break;
790 case "fcvtzu":
791 instructionInfo = "Floating-point Convert to Unsigned fixed-point, rounding toward Zero.";
792 break;
793 case "fdiv":
794 instructionInfo = "Floating-point Divide.";
795 break;
796 case "fmadd":
797 instructionInfo = "Floating-point fused Multiply-Add.";
798 break;
799 case "fmax":
800 instructionInfo = "Floating-point Maximum.";
801 break;
802 case "fmaxnm":
803 instructionInfo = "Floating-point Maximum Number.";
804 break;
805 case "fmin":
806 instructionInfo = "Floating-point Minimum.";
807 break;
808 case "fminnm":
809 instructionInfo = "Floating-point Minimum Number.";
810 break;
811 case "fmov":
812 instructionInfo = "Floating-point Move register without conversion.";
813 break;
814 case "fmsub":
815 instructionInfo = "Floating-point Fused Multiply-Subtract.";
816 break;
817 case "fmul":
818 instructionInfo = "Floating-point Multiply.";
819 break;
820 case "fneg":
821 instructionInfo = "Floating-point Negate.";
822 break;
823 case "fnmadd":
824 instructionInfo = "Floating-point Negated fused Multiply-Add.";
825 break;
826 case "fnmsub":
827 instructionInfo = "Floating-point Negated fused Multiply-Subtract.";
828 break;
829 case "fnmul":
830 instructionInfo = "Floating-point Multiply-Negate.";
831 break;
832 case "frinta":
833 instructionInfo = "Floating-point Round to Integral, to nearest with ties to Away.";
834 break;
835 case "frinti":
836 instructionInfo = "Floating-point Round to Integral, using current rounding mode.";
837 break;
838 case "frintm":
839 instructionInfo = "Floating-point Round to Integral, toward Minus infinity.";
840 break;
841 case "frintn":
842 instructionInfo = "Floating-point Round to Integral, to nearest with ties to even.";
843 break;
844 case "frintp":
845 instructionInfo = "Floating-point Round to Integral, toward Plus infinity.";
846 break;
847 case "frintx":
848 instructionInfo = "Floating-point Round to Integral exact, using current rounding mode.";
849 break;
850 case "frintz":
851 instructionInfo = "Floating-point Round to Integral, toward Zero.";
852 break;
853 case "fsqrt":
854 instructionInfo = "Floating-point Square Root.";
855 break;
856 case "fsub":
857 instructionInfo = "Floating-point Subtract.";
858 break;
859 case "scvtf":
860 instructionInfo = "Signed fixed-point Convert to Floating-point.";
861 break;
862 case "ucvtf":
863 instructionInfo = "Unsigned fixed-point Convert to Floating-point.";
864 break;
865 case "abs":
866 instructionInfo = "Absolute value.";
867 break;
868 case "vabs":
869 instructionInfo = "Returns the absolute value of each element in a vector.";
870 break;
871 case "addp":
872 instructionInfo = "Add Pair of elements.";
873 break;
874 case "cmeq":
875 instructionInfo = "Compare bitwise Equal.";
876 break;
877 case "cmge":
878 instructionInfo = "Compare signed Greater than or Equal.";
879 break;
880 case "cmgt":
881 instructionInfo = "Compare signed Greater than.";
882 break;
883 case "cmhi":
884 instructionInfo = "Compare unsigned Higher.";
885 break;
886 case "cmhs":
887 instructionInfo = "Compare unsigned Higher or Same.";
888 break;
889 case "cmle":
890 instructionInfo = "Compare signed Less than or Equal to zero.";
891 break;
892 case "cmlt":
893 instructionInfo = "Compare signed Less than zero.";
894 break;
895 case "cmtst":
896 instructionInfo = "Compare bitwise Test bits nonzero.";
897 break;
898 case "dup":
899 instructionInfo = "Duplicate vector element to scalar.";
900 break;
901 case "fabd":
902 instructionInfo = "Floating-point Absolute Difference.";
903 break;
904 case "facge":
905 instructionInfo = "Floating-point Absolute Compare Greater than or Equal.";
906 break;
907 case "facgt":
908 instructionInfo = "Floating-point Absolute Compare Greater than.";
909 break;
910 case "faddp":
911 instructionInfo = "Floating-point Add Pair of elements.";
912 break;
913 case "fcmeq":
914 instructionInfo = "Floating-point Compare Equal.";
915 break;
916 case "fcmge":
917 instructionInfo = "Floating-point Compare Greater than or Equal.";
918 break;
919 case "fcmgt":
920 instructionInfo = "Floating-point Compare Greater than.";
921 break;
922 case "fcmle":
923 instructionInfo = "Floating-point Compare Less than or Equal to zero.";
924 break;
925 case "fcmlt":
926 instructionInfo = "Floating-point Compare Less than zero.";
927 break;
928 case "fcvtxn":
929 instructionInfo = "Floating-point Convert to lower precision Narrow, rounding to odd.";
930 break;
931 case "fmaxnmp":
932 instructionInfo = "Floating-point Maximum Number of Pair of elements.";
933 break;
934 case "fmaxp":
935 instructionInfo = "Floating-point Maximum of Pair of elements.";
936 break;
937 case "fminnmp":
938 instructionInfo = "Floating-point Minimum Number of Pair of elements.";
939 break;
940 case "fminp":
941 instructionInfo = "Floating-point Minimum of Pair of elements.";
942 break;
943 case "fmla":
944 instructionInfo = "Floating-point fused Multiply-Add to accumulator.";
945 break;
946 case "fmls":
947 instructionInfo = "Floating-point fused Multiply-Subtract from accumulator.";
948 break;
949 case "fmulx":
950 instructionInfo = "Floating-point Multiply extended.";
951 break;
952 case "frecpe":
953 instructionInfo = "Floating-point Reciprocal Estimate.";
954 break;
955 case "frecps":
956 instructionInfo = "Floating-point Reciprocal Step.";
957 break;
958 case "frsqrte":
959 instructionInfo = "Floating-point Reciprocal Square Root Estimate.";
960 break;
961 case "frsqrts":
962 instructionInfo = "Floating-point Reciprocal Square Root Step.";
963 break;
964 case "shl":
965 instructionInfo = "Shift Left.";
966 break;
967 case "sli":
968 instructionInfo = "Shift Left and Insert.";
969 break;
970 case "sqabs":
971 instructionInfo = "Signed saturating Absolute value.";
972 break;
973 case "sqadd":
974 instructionInfo = "Signed saturating Add.";
975 break;
976 case "sqdmlal":
977 instructionInfo = "Signed saturating Doubling Multiply-Add Long.";
978 break;
979 case "sqdmlsl":
980 instructionInfo = "Signed saturating Doubling Multiply-Subtract Long.";
981 break;
982 case "sqdmulh":
983 instructionInfo = "Signed saturating Doubling Multiply returning High half.";
984 break;
985 case "sqdmull":
986 instructionInfo = "Signed saturating Doubling Multiply Long.";
987 break;
988 case "sqneg":
989 instructionInfo = "Signed saturating Negate.";
990 break;
991 case "sqrdmulh":
992 instructionInfo = "Signed saturating Rounding Doubling Multiply returning High half.";
993 break;
994 case "sqrshl":
995 instructionInfo = "Signed saturating Rounding Shift Left.";
996 break;
997 case "sqrshrn":
998 instructionInfo = "Signed saturating Rounded Shift Right Narrow.";
999 break;
1000 case "sqrshrun":
1001 instructionInfo = "Signed saturating Rounded Shift Right Unsigned Narrow.";
1002 break;
1003 case "sqshl":
1004 instructionInfo = "Signed saturating Shift Left.";
1005 break;
1006 case "sqshlu":
1007 instructionInfo = "Signed saturating Shift Left Unsigned.";
1008 break;
1009 case "sqshrn":
1010 instructionInfo = "Signed saturating Shift Right Narrow.";
1011 break;
1012 case "sqshrun":
1013 instructionInfo = "Signed saturating Shift Right Unsigned Narrow.";
1014 break;
1015 case "sqsub":
1016 instructionInfo = "Signed saturating Subtract.";
1017 break;
1018 case "sqxtn":
1019 instructionInfo = "Signed saturating extract Narrow.";
1020 break;
1021 case "sqxtun":
1022 instructionInfo = "Signed saturating extract Unsigned Narrow.";
1023 break;
1024 case "sri":
1025 instructionInfo = "Shift Right and Insert.";
1026 break;
1027 case "srshl":
1028 instructionInfo = "Signed Rounding Shift Left.";
1029 break;
1030 case "srshr":
1031 instructionInfo = "Signed Rounding Shift Right.";
1032 break;
1033 case "srsra":
1034 instructionInfo = "Signed Rounding Shift Right and Accumulate.";
1035 break;
1036 case "sshl":
1037 instructionInfo = "Signed Shift Left.";
1038 break;
1039 case "sshr":
1040 instructionInfo = "Signed Shift Right.";
1041 break;
1042 case "ssra":
1043 instructionInfo = "Signed Shift Right and Accumulate.";
1044 break;
1045 case "suqadd":
1046 instructionInfo = "Signed saturating Accumulate of Unsigned value.";
1047 break;
1048 case "uqadd":
1049 instructionInfo = "Unsigned saturating Add.";
1050 break;
1051 case "uqrshl":
1052 instructionInfo = "Unsigned saturating Rounding Shift Left.";
1053 break;
1054 case "uqrshrn":
1055 instructionInfo = "Unsigned saturating Rounded Shift Right Narrow.";
1056 break;
1057 case "uqshl":
1058 instructionInfo = "Unsigned saturating Shift Left.";
1059 break;
1060 case "uqshrn":
1061 instructionInfo = "Unsigned saturating Shift Right Narrow.";
1062 break;
1063 case "uqsub":
1064 instructionInfo = "Unsigned saturating Subtract.";
1065 break;
1066 case "uqxtn":
1067 instructionInfo = "Unsigned saturating extract Narrow.";
1068 break;
1069 case "urshl":
1070 instructionInfo = "Unsigned Rounding Shift Left.";
1071 break;
1072 case "urshr":
1073 instructionInfo = "Unsigned Rounding Shift Right.";
1074 break;
1075 case "ursra":
1076 instructionInfo = "Unsigned Rounding Shift Right and Accumulate.";
1077 break;
1078 case "ushl":
1079 instructionInfo = "Unsigned Shift Left.";
1080 break;
1081 case "ushr":
1082 instructionInfo = "Unsigned Shift Right.";
1083 break;
1084 case "usqadd":
1085 instructionInfo = "Unsigned saturating Accumulate of Signed value.";
1086 break;
1087 case "usra":
1088 instructionInfo = "Unsigned Shift Right and Accumulate.";
1089 break;
1090 case "addhn":
1091 case "addhn2":
1092 instructionInfo = "Add returning High Narrow.";
1093 break;
1094 case "addv":
1095 instructionInfo = "Add across Vector.";
1096 break;
1097 case "bif":
1098 instructionInfo = "Bitwise Insert if False.";
1099 break;
1100 case "bit":
1101 instructionInfo = "Bitwise Insert if True.";
1102 break;
1103 case "bsl":
1104 instructionInfo = "Bitwise Select.";
1105 break;
1106 case "cnt":
1107 instructionInfo = "Population Count per byte.";
1108 break;
1109 case "ext":
1110 instructionInfo = "Extract vector from pair of vectors.";
1111 break;
1112 case "fcvtl":
1113 case "fcvtl2":
1114 instructionInfo = "Floating-point Convert to higher precision Long.";
1115 break;
1116 case "fcvtn":
1117 case "fcvtn2":
1118 instructionInfo = "Floating-point Convert to lower precision Narrow.";
1119 break;
1120 case "fcvtxn2":
1121 instructionInfo = "Floating-point Convert to lower precision Narrow, rounding to odd.";
1122 break;
1123 case "fmaxnmv":
1124 instructionInfo = "Floating-point Maximum Number across Vector.";
1125 break;
1126 case "fmaxv":
1127 instructionInfo = "Floating-point Maximum across Vector.";
1128 break;
1129 case "fminnmv":
1130 instructionInfo = "Floating-point Minimum Number across Vector.";
1131 break;
1132 case "fminv":
1133 instructionInfo = "Floating-point Minimum across Vector.";
1134 break;
1135 case "frecpx":
1136 instructionInfo = "Floating-point Reciprocal exponent.";
1137 break;
1138 case "ins":
1139 instructionInfo = "Insert vector element from another vector element.";
1140 break;
1141 case "ld1":
1142 instructionInfo = "Load multiple single-element structures to one, two, three, or four registers.";
1143 break;
1144 case "ld1r":
1145 instructionInfo = "Load one single-element structure and Replicate to all lanes.";
1146 break;
1147 case "ld2":
1148 instructionInfo = "Load multiple 2-element structures to two registers.";
1149 break;
1150 case "ld2r":
1151 instructionInfo = "Load single 2-element structure and Replicate to all lanes of two registers.";
1152 break;
1153 case "ld3":
1154 instructionInfo = "Load multiple 3-element structures to three registers.";
1155 break;
1156 case "ld3r":
1157 instructionInfo = "Load single 3-element structure and Replicate to all lanes of three registers.";
1158 break;
1159 case "ld4":
1160 instructionInfo = "Load multiple 4-element structures to four registers.";
1161 break;
1162 case "ld4r":
1163 instructionInfo = "Load single 4-element structure and Replicate to all lanes of four registers.";
1164 break;
1165 case "mla":
1166 instructionInfo = "Multiply-Add to accumulator (vector, by element).";
1167 break;
1168 case "mls":
1169 instructionInfo = "Multiply-Subtract from accumulator (vector, by element).";
1170 break;
1171 case "movi":
1172 instructionInfo = "Move Immediate.";
1173 break;
1174 case "mvni":
1175 instructionInfo = "Move inverted Immediate.";
1176 break;
1177 case "not":
1178 instructionInfo = "Bitwise NOT.";
1179 break;
1180 case "pmul":
1181 instructionInfo = "Polynomial Multiply.";
1182 break;
1183 case "pmull":
1184 case "pmull2":
1185 instructionInfo = "Polynomial Multiply Long.";
1186 break;
1187 case "raddhn":
1188 case "raddhn2":
1189 instructionInfo = "Rounding Add returning High Narrow.";
1190 break;
1191 case "rshrn":
1192 case "rshrn2":
1193 instructionInfo = "Rounding Shift Right Narrow.";
1194 break;
1195 case "rsubhn":
1196 case "rsubhn2":
1197 instructionInfo = "Rounding Subtract returning High Narrow.";
1198 break;
1199 case "saba":
1200 instructionInfo = "Signed Absolute difference and Accumulate.";
1201 break;
1202 case "sabal":
1203 case "sabal2":
1204 instructionInfo = "Signed Absolute difference and Accumulate Long.";
1205 break;
1206 case "sabd":
1207 instructionInfo = "Signed Absolute Difference.";
1208 break;
1209 case "sabdl":
1210 case "sabdl2":
1211 instructionInfo = "Signed Absolute Difference Long.";
1212 break;
1213 case "sadalp":
1214 instructionInfo = "Signed Add and Accumulate Long Pairwise.";
1215 break;
1216 case "saddl":
1217 case "saddl2":
1218 instructionInfo = "Signed Add Long.";
1219 break;
1220 case "saddlp":
1221 instructionInfo = "Signed Add Long Pairwise.";
1222 break;
1223 case "saddlv":
1224 instructionInfo = "Signed Add Long across Vector.";
1225 break;
1226 case "saddw":
1227 case "saddw2":
1228 instructionInfo = "Signed Add Wide.";
1229 break;
1230 case "shadd":
1231 instructionInfo = "Signed Halving Add.";
1232 break;
1233 case "shll":
1234 case "shll2":
1235 instructionInfo = "Shift Left Long.";
1236 break;
1237 case "shrn":
1238 case "shrn2":
1239 instructionInfo = "Shift Right Narrow.";
1240 break;
1241 case "shsub":
1242 instructionInfo = "Signed Halving Subtract.";
1243 break;
1244 case "smax":
1245 instructionInfo = "Signed Maximum.";
1246 break;
1247 case "smaxp":
1248 instructionInfo = "Signed Maximum Pairwise.";
1249 break;
1250 case "smaxv":
1251 instructionInfo = "Signed Maximum across Vector.";
1252 break;
1253 case "smin":
1254 instructionInfo = "Signed Minimum.";
1255 break;
1256 case "sminp":
1257 instructionInfo = "Signed Minimum Pairwise.";
1258 break;
1259 case "sminv":
1260 instructionInfo = "Signed Minimum across Vector.";
1261 break;
1262 case "smlabb":
1263 case "smlabt":
1264 case "smlatb":
1265 case "smlatt":
1266 instructionInfo = "Signed Multiply Accumulate performs a signed multiply accumulate operation.";
1267 break;
1268 case "smlal":
1269 case "smlal2":
1270 instructionInfo = "Signed Multiply-Add Long (vector, by element).";
1271 break;
1272 case "smlsl":
1273 case "smlsl2":
1274 instructionInfo = "Signed Multiply-Subtract Long (vector, by element).";
1275 break;
1276 case "smov":
1277 instructionInfo = "Signed Move vector element to general-purpose register.";
1278 break;
1279 case "smull2":
1280 instructionInfo = "Signed Multiply Long (vector, by element).";
1281 break;
1282 case "sqdmlal2":
1283 instructionInfo = "Signed saturating Doubling Multiply-Add Long.";
1284 break;
1285 case "sqdmlsl2":
1286 instructionInfo = "Signed saturating Doubling Multiply-Subtract Long.";
1287 break;
1288 case "sqdmull2":
1289 instructionInfo = "Signed saturating Doubling Multiply Long.";
1290 break;
1291 case "sqrshrn2":
1292 instructionInfo = "Signed saturating Rounded Shift Right Narrow.";
1293 break;
1294 case "sqrshrun2":
1295 instructionInfo = "Signed saturating Rounded Shift Right Unsigned Narrow.";
1296 break;
1297 case "sqshrn2":
1298 instructionInfo = "Signed saturating Shift Right Narrow.";
1299 break;
1300 case "sqshrun2":
1301 instructionInfo = "Signed saturating Shift Right Unsigned Narrow.";
1302 break;
1303 case "sqxtn2":
1304 instructionInfo = "Signed saturating extract Narrow.";
1305 break;
1306 case "sqxtun2":
1307 instructionInfo = "Signed saturating extract Unsigned Narrow.";
1308 break;
1309 case "srhadd":
1310 instructionInfo = "Signed Rounding Halving Add.";
1311 break;
1312 case "sshll":
1313 case "sshll2":
1314 instructionInfo = "Signed Shift Left Long.";
1315 break;
1316 case "ssubl":
1317 case "ssubl2":
1318 instructionInfo = "Signed Subtract Long.";
1319 break;
1320 case "ssubw":
1321 case "ssubw2":
1322 instructionInfo = "Signed Subtract Wide.";
1323 break;
1324 case "st1":
1325 instructionInfo = "Store multiple single-element structures from one, two, three, or four registers.";
1326 break;
1327 case "st2":
1328 instructionInfo = "Store multiple 2-element structures from two registers.";
1329 break;
1330 case "st3":
1331 instructionInfo = "Store multiple 3-element structures from three registers.";
1332 break;
1333 case "st4":
1334 instructionInfo = "Store multiple 4-element structures from four registers.";
1335 break;
1336 case "subhn":
1337 case "subhn2":
1338 instructionInfo = "Subtract returning High Narrow.";
1339 break;
1340 case "tbl":
1341 instructionInfo = "Table vector Lookup.";
1342 break;
1343 case "tbx":
1344 instructionInfo = "Table vector lookup extension.";
1345 break;
1346 case "tbb":
1347 instructionInfo = "PC-relative forward branch using table of single byte offsets.";
1348 break;
1349 case "tbh":
1350 instructionInfo = "PC-relative forward branch using table of halfword offsets.";
1351 break;
1352 case "trn1":
1353 instructionInfo = "Transpose vectors.";
1354 break;
1355 case "trn2":
1356 instructionInfo = "Transpose vectors.";
1357 break;
1358 case "uaba":
1359 instructionInfo = "Unsigned Absolute difference and Accumulate.";
1360 break;
1361 case "uabal":
1362 case "uabal2":
1363 instructionInfo = "Unsigned Absolute difference and Accumulate Long.";
1364 break;
1365 case "uabd":
1366 instructionInfo = "Unsigned Absolute Difference.";
1367 break;
1368 case "uabdl":
1369 case "uabdl2":
1370 instructionInfo = "Unsigned Absolute Difference Long.";
1371 break;
1372 case "uadalp":
1373 instructionInfo = "Unsigned Add and Accumulate Long Pairwise.";
1374 break;
1375 case "uaddl":
1376 case "uaddl2":
1377 instructionInfo = "Unsigned Add Long.";
1378 break;
1379 case "uaddlp":
1380 instructionInfo = "Unsigned Add Long Pairwise.";
1381 break;
1382 case "uaddlv":
1383 instructionInfo = "Unsigned sum Long across Vector.";
1384 break;
1385 case "uaddw":
1386 case "uaddw2":
1387 instructionInfo = "Unsigned Add Wide.";
1388 break;
1389 case "uhadd":
1390 instructionInfo = "Unsigned Halving Add.";
1391 break;
1392 case "uhsub":
1393 instructionInfo = "Unsigned Halving Subtract.";
1394 break;
1395 case "umax":
1396 instructionInfo = "Unsigned Maximum.";
1397 break;
1398 case "umaxp":
1399 instructionInfo = "Unsigned Maximum Pairwise.";
1400 break;
1401 case "umaxv":
1402 instructionInfo = "Unsigned Maximum across Vector.";
1403 break;
1404 case "umin":
1405 instructionInfo = "Unsigned Minimum.";
1406 break;
1407 case "uminp":
1408 instructionInfo = "Unsigned Minimum Pairwise.";
1409 break;
1410 case "uminv":
1411 instructionInfo = "Unsigned Minimum across Vector.";
1412 break;
1413 case "umlal":
1414 case "umlal2":
1415 instructionInfo = "Unsigned Multiply-Add Long (vector, by element).";
1416 break;
1417 case "umlsl":
1418 case "umlsl2":
1419 instructionInfo = "Unsigned Multiply-Subtract Long (vector, by element).";
1420 break;
1421 case "umov":
1422 instructionInfo = "Unsigned Move vector element to general-purpose register.";
1423 break;
1424 case "umull2":
1425 instructionInfo = "Unsigned Multiply Long (vector, by element).";
1426 break;
1427 case "uqrshrn2":
1428 instructionInfo = "Unsigned saturating Rounded Shift Right Narrow.";
1429 break;
1430 case "uqshrn2":
1431 instructionInfo = "Unsigned saturating Shift Right Narrow.";
1432 break;
1433 case "uqxtn2":
1434 instructionInfo = "Unsigned saturating extract Narrow.";
1435 break;
1436 case "urecpe":
1437 instructionInfo = "Unsigned Reciprocal Estimate.";
1438 break;
1439 case "urhadd":
1440 instructionInfo = "Unsigned Rounding Halving Add.";
1441 break;
1442 case "ursqrte":
1443 instructionInfo = "Unsigned Reciprocal Square Root Estimate.";
1444 break;
1445 case "ushll":
1446 case "ushll2":
1447 instructionInfo = "Unsigned Shift Left Long.";
1448 break;
1449 case "usubl":
1450 case "usubl2":
1451 instructionInfo = "Unsigned Subtract Long.";
1452 break;
1453 case "usubw":
1454 case "usubw2":
1455 instructionInfo = "Unsigned Subtract Wide.";
1456 break;
1457 case "uzp1":
1458 instructionInfo = "Unzip vectors.";
1459 break;
1460 case "uzp2":
1461 instructionInfo = "Unzip vectors.";
1462 break;
1463 case "xtn":
1464 case "xtn2":
1465 instructionInfo = "Extract Narrow.";
1466 break;
1467 case "zip1":
1468 instructionInfo = "Zip vectors.";
1469 break;
1470 case "zip2":
1471 instructionInfo = "Zip vectors.";
1472 break;
1473 case "aesd":
1474 instructionInfo = "AES single round decryption.";
1475 break;
1476 case "aese":
1477 instructionInfo = "AES single round encryption.";
1478 break;
1479 case "aesimc":
1480 instructionInfo = "AES inverse mix columns.";
1481 break;
1482 case "aesmc":
1483 instructionInfo = "AES mix columns.";
1484 break;
1485 case "sha1c":
1486 instructionInfo = "SHA1 hash update.";
1487 break;
1488 case "sha1h":
1489 instructionInfo = "SHA1 fixed rotate.";
1490 break;
1491 case "sha1m":
1492 instructionInfo = "SHA1 hash update.";
1493 break;
1494 case "sha1p":
1495 instructionInfo = "SHA1 hash update.";
1496 break;
1497 case "sha1su0":
1498 instructionInfo = "SHA1 schedule update 0.";
1499 break;
1500 case "sha1su1":
1501 instructionInfo = "SHA1 schedule update 1.";
1502 break;
1503 case "sha256h2":
1504 instructionInfo = "SHA256 hash update.";
1505 break;
1506 case "sha256h":
1507 instructionInfo = "SHA256 hash update.";
1508 break;
1509 case "sha256su0":
1510 instructionInfo = "SHA256 schedule update 0.";
1511 break;
1512 case "sha256su1":
1513 instructionInfo = "SHA256 schedule update 1.";
1514 break;
1515 case "adcs":
1516 instructionInfo = "Add with Carry, setting flags.";
1517 break;
1518 case "addg":
1519 instructionInfo = "Add with Tag.";
1520 break;
1521 case "ands":
1522 instructionInfo = "Bitwise AND (immediate), setting flags.";
1523 break;
1524 case "asrv":
1525 instructionInfo = "Arithmetic Shift Right Variable.";
1526 break;
1527 case "autda":
1528 instructionInfo = "Authenticate Data address, using key A.";
1529 break;
1530 case "autdza":
1531 instructionInfo = "Authenticate Data address, using key A.";
1532 break;
1533 case "autdb":
1534 instructionInfo = "Authenticate Data address, using key B.";
1535 break;
1536 case "autdzb":
1537 instructionInfo = "Authenticate Data address, using key B.";
1538 break;
1539 case "autia":
1540 instructionInfo = "Authenticate Instruction address, using key A.";
1541 break;
1542 case "autiza":
1543 instructionInfo = "Authenticate Instruction address, using key A.";
1544 break;
1545 case "autia1716":
1546 instructionInfo = "Authenticate Instruction address, using key A.";
1547 break;
1548 case "autiasp":
1549 instructionInfo = "Authenticate Instruction address, using key A.";
1550 break;
1551 case "autiaz":
1552 instructionInfo = "Authenticate Instruction address, using key A.";
1553 break;
1554 case "autib":
1555 instructionInfo = "Authenticate Instruction address, using key B.";
1556 break;
1557 case "autizb":
1558 instructionInfo = "Authenticate Instruction address, using key B.";
1559 break;
1560 case "autib1716":
1561 instructionInfo = "Authenticate Instruction address, using key B.";
1562 break;
1563 case "autibsp":
1564 instructionInfo = "Authenticate Instruction address, using key B.";
1565 break;
1566 case "autibz":
1567 instructionInfo = "Authenticate Instruction address, using key B.";
1568 break;
1569 case "axflag":
1570 instructionInfo = "Convert floating-point condition flags from Arm to external format.";
1571 break;
1572 case "b.cond":
1573 instructionInfo = "Branch conditionally.";
1574 break;
1575 case "bfc":
1576 instructionInfo = "Bitfield Clear, leaving other bits unchanged.";
1577 break;
1578 case "bics":
1579 instructionInfo = "Bitwise Bit Clear (shifted register), setting flags.";
1580 break;
1581 case "blraa":
1582 instructionInfo = "Branch with Link to Register, with pointer authentication.";
1583 break;
1584 case "blraaz":
1585 instructionInfo = "Branch with Link to Register, with pointer authentication.";
1586 break;
1587 case "blrab":
1588 instructionInfo = "Branch with Link to Register, with pointer authentication.";
1589 break;
1590 case "blrabz":
1591 instructionInfo = "Branch with Link to Register, with pointer authentication.";
1592 break;
1593 case "braa":
1594 instructionInfo = "Branch to Register, with pointer authentication.";
1595 break;
1596 case "braaz":
1597 instructionInfo = "Branch to Register, with pointer authentication.";
1598 break;
1599 case "brab":
1600 instructionInfo = "Branch to Register, with pointer authentication.";
1601 break;
1602 case "brabz":
1603 instructionInfo = "Branch to Register, with pointer authentication.";
1604 break;
1605 case "bti":
1606 instructionInfo = "Branch Target Identification.";
1607 break;
1608 case "cinc":
1609 instructionInfo = "Conditional Increment.";
1610 break;
1611 case "cinv":
1612 instructionInfo = "Conditional Invert.";
1613 break;
1614 case "cmpp":
1615 instructionInfo = "Compare with Tag.";
1616 break;
1617 case "cneg":
1618 instructionInfo = "Conditional Negate.";
1619 break;
1620 case "csdb":
1621 instructionInfo = "Consumption of Speculative Data Barrier.";
1622 break;
1623 case "cset":
1624 instructionInfo = "Conditional Set.";
1625 break;
1626 case "csetm":
1627 instructionInfo = "Conditional Set Mask.";
1628 break;
1629 case "eretaa":
1630 instructionInfo = "Exception Return, with pointer authentication.";
1631 break;
1632 case "eretab":
1633 instructionInfo = "Exception Return, with pointer authentication.";
1634 break;
1635 case "esb":
1636 instructionInfo = "Error Synchronization Barrier.";
1637 break;
1638 case "irg":
1639 instructionInfo = "Insert Random Tag.";
1640 break;
1641 case "ldg":
1642 instructionInfo = "Load Allocation Tag.";
1643 break;
1644 case "ldgv":
1645 instructionInfo = "Load Allocation Tag.";
1646 break;
1647 case "lslv":
1648 instructionInfo = "Logical Shift Left Variable.";
1649 break;
1650 case "lsrv":
1651 instructionInfo = "Logical Shift Right Variable.";
1652 break;
1653 case "movl pseudo-instruction":
1654 instructionInfo = "Load a register with either a 32-bit or 64-bit immediate value or any address.";
1655 break;
1656 case "negs":
1657 instructionInfo = "Negate, setting flags.";
1658 break;
1659 case "ngcs":
1660 instructionInfo = "Negate with Carry, setting flags.";
1661 break;
1662 case "pacda":
1663 instructionInfo = "Pointer Authentication Code for Data address, using key A.";
1664 break;
1665 case "pacdza":
1666 instructionInfo = "Pointer Authentication Code for Data address, using key A.";
1667 break;
1668 case "pacdb":
1669 instructionInfo = "Pointer Authentication Code for Data address, using key B.";
1670 break;
1671 case "pacdzb":
1672 instructionInfo = "Pointer Authentication Code for Data address, using key B.";
1673 break;
1674 case "pacga":
1675 instructionInfo = "Pointer Authentication Code, using Generic key.";
1676 break;
1677 case "pacia":
1678 instructionInfo = "Pointer Authentication Code for Instruction address, using key A.";
1679 break;
1680 case "paciza":
1681 instructionInfo = "Pointer Authentication Code for Instruction address, using key A.";
1682 break;
1683 case "pacia1716":
1684 instructionInfo = "Pointer Authentication Code for Instruction address, using key A.";
1685 break;
1686 case "paciasp":
1687 instructionInfo = "Pointer Authentication Code for Instruction address, using key A.";
1688 break;
1689 case "paciaz":
1690 instructionInfo = "Pointer Authentication Code for Instruction address, using key A.";
1691 break;
1692 case "pacib":
1693 instructionInfo = "Pointer Authentication Code for Instruction address, using key B.";
1694 break;
1695 case "pacizb":
1696 instructionInfo = "Pointer Authentication Code for Instruction address, using key B.";
1697 break;
1698 case "pacib1716":
1699 instructionInfo = "Pointer Authentication Code for Instruction address, using key B.";
1700 break;
1701 case "pacibsp":
1702 instructionInfo = "Pointer Authentication Code for Instruction address, using key B.";
1703 break;
1704 case "pacibz":
1705 instructionInfo = "Pointer Authentication Code for Instruction address, using key B.";
1706 break;
1707 case "psb":
1708 instructionInfo = "Profiling Synchronization Barrier.";
1709 break;
1710 case "retaa":
1711 instructionInfo = "Return from subroutine, with pointer authentication.";
1712 break;
1713 case "retab":
1714 instructionInfo = "Return from subroutine, with pointer authentication.";
1715 break;
1716 case "rorv":
1717 instructionInfo = "Rotate Right Variable.";
1718 break;
1719 case "sbcs":
1720 instructionInfo = "Subtract with Carry, setting flags.";
1721 break;
1722 case "st2g":
1723 instructionInfo = "Store Allocation Tags.";
1724 break;
1725 case "stg":
1726 instructionInfo = "Store Allocation Tag.";
1727 break;
1728 case "stgp":
1729 instructionInfo = "Store Allocation Tag and Pair of registers.";
1730 break;
1731 case "stgv":
1732 instructionInfo = "Store Tag Vector.";
1733 break;
1734 case "stz2g":
1735 instructionInfo = "Store Allocation Tags, Zeroing.";
1736 break;
1737 case "stzg":
1738 instructionInfo = "Store Allocation Tag, Zeroing.";
1739 break;
1740 case "subg":
1741 instructionInfo = "Subtract with Tag.";
1742 break;
1743 case "subp":
1744 instructionInfo = "Subtract Pointer.";
1745 break;
1746 case "subps":
1747 instructionInfo = "Subtract Pointer, setting Flags.";
1748 break;
1749 case "xaflag":
1750 instructionInfo = "Convert floating-point condition flags from external format to Arm format.";
1751 break;
1752 case "xpacd":
1753 instructionInfo = "Strip Pointer Authentication Code.";
1754 break;
1755 case "xpaci":
1756 instructionInfo = "Strip Pointer Authentication Code.";
1757 break;
1758 case "xpaclri":
1759 instructionInfo = "Strip Pointer Authentication Code.";
1760 break;
1761 case "casa":
1762 instructionInfo = "Compare and Swap word or doubleword in memory.";
1763 break;
1764 case "casal":
1765 instructionInfo = "Compare and Swap word or doubleword in memory.";
1766 break;
1767 case "cas":
1768 instructionInfo = "Compare and Swap word or doubleword in memory.";
1769 break;
1770 case "casl":
1771 instructionInfo = "Compare and Swap word or doubleword in memory.";
1772 break;
1773 case "casab":
1774 instructionInfo = "Compare and Swap byte in memory.";
1775 break;
1776 case "casalb":
1777 instructionInfo = "Compare and Swap byte in memory.";
1778 break;
1779 case "casb":
1780 instructionInfo = "Compare and Swap byte in memory.";
1781 break;
1782 case "caslb":
1783 instructionInfo = "Compare and Swap byte in memory.";
1784 break;
1785 case "casah":
1786 instructionInfo = "Compare and Swap halfword in memory.";
1787 break;
1788 case "casalh":
1789 instructionInfo = "Compare and Swap halfword in memory.";
1790 break;
1791 case "cash":
1792 instructionInfo = "Compare and Swap halfword in memory.";
1793 break;
1794 case "caslh":
1795 instructionInfo = "Compare and Swap halfword in memory.";
1796 break;
1797 case "caspa":
1798 instructionInfo = "Compare and Swap Pair of words or doublewords in memory.";
1799 break;
1800 case "caspal":
1801 instructionInfo = "Compare and Swap Pair of words or doublewords in memory.";
1802 break;
1803 case "casp":
1804 instructionInfo = "Compare and Swap Pair of words or doublewords in memory.";
1805 break;
1806 case "caspl":
1807 instructionInfo = "Compare and Swap Pair of words or doublewords in memory.";
1808 break;
1809 case "ldadda":
1810 instructionInfo = "Atomic add on word or doubleword in memory.";
1811 break;
1812 case "ldaddal":
1813 instructionInfo = "Atomic add on word or doubleword in memory.";
1814 break;
1815 case "ldadd":
1816 instructionInfo = "Atomic add on word or doubleword in memory.";
1817 break;
1818 case "ldaddl":
1819 instructionInfo = "Atomic add on word or doubleword in memory.";
1820 break;
1821 case "ldaddab":
1822 instructionInfo = "Atomic add on byte in memory.";
1823 break;
1824 case "ldaddalb":
1825 instructionInfo = "Atomic add on byte in memory.";
1826 break;
1827 case "ldaddb":
1828 instructionInfo = "Atomic add on byte in memory.";
1829 break;
1830 case "ldaddlb":
1831 instructionInfo = "Atomic add on byte in memory.";
1832 break;
1833 case "ldaddah":
1834 instructionInfo = "Atomic add on halfword in memory.";
1835 break;
1836 case "ldaddalh":
1837 instructionInfo = "Atomic add on halfword in memory.";
1838 break;
1839 case "ldaddh":
1840 instructionInfo = "Atomic add on halfword in memory.";
1841 break;
1842 case "ldaddlh":
1843 instructionInfo = "Atomic add on halfword in memory.";
1844 break;
1845 case "ldapr":
1846 instructionInfo = "Load-Acquire RCpc Register.";
1847 break;
1848 case "ldaprb":
1849 instructionInfo = "Load-Acquire RCpc Register Byte.";
1850 break;
1851 case "ldaprh":
1852 instructionInfo = "Load-Acquire RCpc Register Halfword.";
1853 break;
1854 case "ldclra":
1855 instructionInfo = "Atomic bit clear on word or doubleword in memory.";
1856 break;
1857 case "ldclral":
1858 instructionInfo = "Atomic bit clear on word or doubleword in memory.";
1859 break;
1860 case "ldclr":
1861 instructionInfo = "Atomic bit clear on word or doubleword in memory.";
1862 break;
1863 case "ldclrl":
1864 instructionInfo = "Atomic bit clear on word or doubleword in memory.";
1865 break;
1866 case "ldclrab":
1867 instructionInfo = "Atomic bit clear on byte in memory.";
1868 break;
1869 case "ldclralb":
1870 instructionInfo = "Atomic bit clear on byte in memory.";
1871 break;
1872 case "ldclrb":
1873 instructionInfo = "Atomic bit clear on byte in memory.";
1874 break;
1875 case "ldclrlb":
1876 instructionInfo = "Atomic bit clear on byte in memory.";
1877 break;
1878 case "ldclrah":
1879 instructionInfo = "Atomic bit clear on halfword in memory.";
1880 break;
1881 case "ldclralh":
1882 instructionInfo = "Atomic bit clear on halfword in memory.";
1883 break;
1884 case "ldclrh":
1885 instructionInfo = "Atomic bit clear on halfword in memory.";
1886 break;
1887 case "ldclrlh":
1888 instructionInfo = "Atomic bit clear on halfword in memory.";
1889 break;
1890 case "ldeora":
1891 instructionInfo = "Atomic exclusive OR on word or doubleword in memory.";
1892 break;
1893 case "ldeoral":
1894 instructionInfo = "Atomic exclusive OR on word or doubleword in memory.";
1895 break;
1896 case "ldeor":
1897 instructionInfo = "Atomic exclusive OR on word or doubleword in memory.";
1898 break;
1899 case "ldeorl":
1900 instructionInfo = "Atomic exclusive OR on word or doubleword in memory.";
1901 break;
1902 case "ldeorab":
1903 instructionInfo = "Atomic exclusive OR on byte in memory.";
1904 break;
1905 case "ldeoralb":
1906 instructionInfo = "Atomic exclusive OR on byte in memory.";
1907 break;
1908 case "ldeorb":
1909 instructionInfo = "Atomic exclusive OR on byte in memory.";
1910 break;
1911 case "ldeorlb":
1912 instructionInfo = "Atomic exclusive OR on byte in memory.";
1913 break;
1914 case "ldeorah":
1915 instructionInfo = "Atomic exclusive OR on halfword in memory.";
1916 break;
1917 case "ldeoralh":
1918 instructionInfo = "Atomic exclusive OR on halfword in memory.";
1919 break;
1920 case "ldeorh":
1921 instructionInfo = "Atomic exclusive OR on halfword in memory.";
1922 break;
1923 case "ldeorlh":
1924 instructionInfo = "Atomic exclusive OR on halfword in memory.";
1925 break;
1926 case "ldlar":
1927 instructionInfo = "Load LOAcquire Register.";
1928 break;
1929 case "ldlarb":
1930 instructionInfo = "Load LOAcquire Register Byte.";
1931 break;
1932 case "ldlarh":
1933 instructionInfo = "Load LOAcquire Register Halfword.";
1934 break;
1935 case "ldr pseudo-instruction":
1936 instructionInfo = "Load a register with either a 32-bit or 64-bit immediate value or any address.";
1937 break;
1938 case "ldraa":
1939 instructionInfo = "Load Register, with pointer authentication.";
1940 break;
1941 case "ldrab":
1942 instructionInfo = "Load Register, with pointer authentication.";
1943 break;
1944 case "ldrex":
1945 instructionInfo = "Load Register Exclusive.";
1946 break;
1947 case "strex":
1948 instructionInfo = "Store Register Exclusive.";
1949 break;
1950 case "ldseta":
1951 instructionInfo = "Atomic bit set on word or doubleword in memory.";
1952 break;
1953 case "ldsetal":
1954 instructionInfo = "Atomic bit set on word or doubleword in memory.";
1955 break;
1956 case "ldset":
1957 instructionInfo = "Atomic bit set on word or doubleword in memory.";
1958 break;
1959 case "ldsetl":
1960 instructionInfo = "Atomic bit set on word or doubleword in memory.";
1961 break;
1962 case "ldsetab":
1963 instructionInfo = "Atomic bit set on byte in memory.";
1964 break;
1965 case "ldsetalb":
1966 instructionInfo = "Atomic bit set on byte in memory.";
1967 break;
1968 case "ldsetb":
1969 instructionInfo = "Atomic bit set on byte in memory.";
1970 break;
1971 case "ldsetlb":
1972 instructionInfo = "Atomic bit set on byte in memory.";
1973 break;
1974 case "ldsetah":
1975 instructionInfo = "Atomic bit set on halfword in memory.";
1976 break;
1977 case "ldsetalh":
1978 instructionInfo = "Atomic bit set on halfword in memory.";
1979 break;
1980 case "ldseth":
1981 instructionInfo = "Atomic bit set on halfword in memory.";
1982 break;
1983 case "ldsetlh":
1984 instructionInfo = "Atomic bit set on halfword in memory.";
1985 break;
1986 case "ldsmaxa":
1987 instructionInfo = "Atomic signed maximum on word or doubleword in memory.";
1988 break;
1989 case "ldsmaxal":
1990 instructionInfo = "Atomic signed maximum on word or doubleword in memory.";
1991 break;
1992 case "ldsmax":
1993 instructionInfo = "Atomic signed maximum on word or doubleword in memory.";
1994 break;
1995 case "ldsmaxl":
1996 instructionInfo = "Atomic signed maximum on word or doubleword in memory.";
1997 break;
1998 case "ldsmaxab":
1999 instructionInfo = "Atomic signed maximum on byte in memory.";
2000 break;
2001 case "ldsmaxalb":
2002 instructionInfo = "Atomic signed maximum on byte in memory.";
2003 break;
2004 case "ldsmaxb":
2005 instructionInfo = "Atomic signed maximum on byte in memory.";
2006 break;
2007 case "ldsmaxlb":
2008 instructionInfo = "Atomic signed maximum on byte in memory.";
2009 break;
2010 case "ldsmaxah":
2011 instructionInfo = "Atomic signed maximum on halfword in memory.";
2012 break;
2013 case "ldsmaxalh":
2014 instructionInfo = "Atomic signed maximum on halfword in memory.";
2015 break;
2016 case "ldsmaxh":
2017 instructionInfo = "Atomic signed maximum on halfword in memory.";
2018 break;
2019 case "ldsmaxlh":
2020 instructionInfo = "Atomic signed maximum on halfword in memory.";
2021 break;
2022 case "ldsmina":
2023 instructionInfo = "Atomic signed minimum on word or doubleword in memory.";
2024 break;
2025 case "ldsminal":
2026 instructionInfo = "Atomic signed minimum on word or doubleword in memory.";
2027 break;
2028 case "ldsmin":
2029 instructionInfo = "Atomic signed minimum on word or doubleword in memory.";
2030 break;
2031 case "ldsminl":
2032 instructionInfo = "Atomic signed minimum on word or doubleword in memory.";
2033 break;
2034 case "ldsminab":
2035 instructionInfo = "Atomic signed minimum on byte in memory.";
2036 break;
2037 case "ldsminalb":
2038 instructionInfo = "Atomic signed minimum on byte in memory.";
2039 break;
2040 case "ldsminb":
2041 instructionInfo = "Atomic signed minimum on byte in memory.";
2042 break;
2043 case "ldsminlb":
2044 instructionInfo = "Atomic signed minimum on byte in memory.";
2045 break;
2046 case "ldsminah":
2047 instructionInfo = "Atomic signed minimum on halfword in memory.";
2048 break;
2049 case "ldsminalh":
2050 instructionInfo = "Atomic signed minimum on halfword in memory.";
2051 break;
2052 case "ldsminh":
2053 instructionInfo = "Atomic signed minimum on halfword in memory.";
2054 break;
2055 case "ldsminlh":
2056 instructionInfo = "Atomic signed minimum on halfword in memory.";
2057 break;
2058 case "ldumaxa":
2059 instructionInfo = "Atomic unsigned maximum on word or doubleword in memory.";
2060 break;
2061 case "ldumaxal":
2062 instructionInfo = "Atomic unsigned maximum on word or doubleword in memory.";
2063 break;
2064 case "ldumax":
2065 instructionInfo = "Atomic unsigned maximum on word or doubleword in memory.";
2066 break;
2067 case "ldumaxl":
2068 instructionInfo = "Atomic unsigned maximum on word or doubleword in memory.";
2069 break;
2070 case "ldumaxab":
2071 instructionInfo = "Atomic unsigned maximum on byte in memory.";
2072 break;
2073 case "ldumaxalb":
2074 instructionInfo = "Atomic unsigned maximum on byte in memory.";
2075 break;
2076 case "ldumaxb":
2077 instructionInfo = "Atomic unsigned maximum on byte in memory.";
2078 break;
2079 case "ldumaxlb":
2080 instructionInfo = "Atomic unsigned maximum on byte in memory.";
2081 break;
2082 case "ldumaxah":
2083 instructionInfo = "Atomic unsigned maximum on halfword in memory.";
2084 break;
2085 case "ldumaxalh":
2086 instructionInfo = "Atomic unsigned maximum on halfword in memory.";
2087 break;
2088 case "ldumaxh":
2089 instructionInfo = "Atomic unsigned maximum on halfword in memory.";
2090 break;
2091 case "ldumaxlh":
2092 instructionInfo = "Atomic unsigned maximum on halfword in memory.";
2093 break;
2094 case "ldumina":
2095 instructionInfo = "Atomic unsigned minimum on word or doubleword in memory.";
2096 break;
2097 case "lduminal":
2098 instructionInfo = "Atomic unsigned minimum on word or doubleword in memory.";
2099 break;
2100 case "ldumin":
2101 instructionInfo = "Atomic unsigned minimum on word or doubleword in memory.";
2102 break;
2103 case "lduminl":
2104 instructionInfo = "Atomic unsigned minimum on word or doubleword in memory.";
2105 break;
2106 case "lduminab":
2107 instructionInfo = "Atomic unsigned minimum on byte in memory.";
2108 break;
2109 case "lduminalb":
2110 instructionInfo = "Atomic unsigned minimum on byte in memory.";
2111 break;
2112 case "lduminb":
2113 instructionInfo = "Atomic unsigned minimum on byte in memory.";
2114 break;
2115 case "lduminlb":
2116 instructionInfo = "Atomic unsigned minimum on byte in memory.";
2117 break;
2118 case "lduminah":
2119 instructionInfo = "Atomic unsigned minimum on halfword in memory.";
2120 break;
2121 case "lduminalh":
2122 instructionInfo = "Atomic unsigned minimum on halfword in memory.";
2123 break;
2124 case "lduminh":
2125 instructionInfo = "Atomic unsigned minimum on halfword in memory.";
2126 break;
2127 case "lduminlh":
2128 instructionInfo = "Atomic unsigned minimum on halfword in memory.";
2129 break;
2130 case "stadd":
2131 instructionInfo = "Atomic add on word or doubleword in memory, without return.";
2132 break;
2133 case "staddl":
2134 instructionInfo = "Atomic add on word or doubleword in memory, without return.";
2135 break;
2136 case "staddb":
2137 instructionInfo = "Atomic add on byte in memory, without return.";
2138 break;
2139 case "staddlb":
2140 instructionInfo = "Atomic add on byte in memory, without return.";
2141 break;
2142 case "staddh":
2143 instructionInfo = "Atomic add on halfword in memory, without return.";
2144 break;
2145 case "staddlh":
2146 instructionInfo = "Atomic add on halfword in memory, without return.";
2147 break;
2148 case "stclr":
2149 instructionInfo = "Atomic bit clear on word or doubleword in memory, without return.";
2150 break;
2151 case "stclrl":
2152 instructionInfo = "Atomic bit clear on word or doubleword in memory, without return.";
2153 break;
2154 case "stclrb":
2155 instructionInfo = "Atomic bit clear on byte in memory, without return.";
2156 break;
2157 case "stclrlb":
2158 instructionInfo = "Atomic bit clear on byte in memory, without return.";
2159 break;
2160 case "stclrh":
2161 instructionInfo = "Atomic bit clear on halfword in memory, without return.";
2162 break;
2163 case "stclrlh":
2164 instructionInfo = "Atomic bit clear on halfword in memory, without return.";
2165 break;
2166 case "steor":
2167 instructionInfo = "Atomic exclusive OR on word or doubleword in memory, without return.";
2168 break;
2169 case "steorl":
2170 instructionInfo = "Atomic exclusive OR on word or doubleword in memory, without return.";
2171 break;
2172 case "steorb":
2173 instructionInfo = "Atomic exclusive OR on byte in memory, without return.";
2174 break;
2175 case "steorlb":
2176 instructionInfo = "Atomic exclusive OR on byte in memory, without return.";
2177 break;
2178 case "steorh":
2179 instructionInfo = "Atomic exclusive OR on halfword in memory, without return.";
2180 break;
2181 case "steorlh":
2182 instructionInfo = "Atomic exclusive OR on halfword in memory, without return.";
2183 break;
2184 case "stllr":
2185 instructionInfo = "Store LORelease Register.";
2186 break;
2187 case "stllrb":
2188 instructionInfo = "Store LORelease Register Byte.";
2189 break;
2190 case "stllrh":
2191 instructionInfo = "Store LORelease Register Halfword.";
2192 break;
2193 case "stset":
2194 instructionInfo = "Atomic bit set on word or doubleword in memory, without return.";
2195 break;
2196 case "stsetl":
2197 instructionInfo = "Atomic bit set on word or doubleword in memory, without return.";
2198 break;
2199 case "stsetb":
2200 instructionInfo = "Atomic bit set on byte in memory, without return.";
2201 break;
2202 case "stsetlb":
2203 instructionInfo = "Atomic bit set on byte in memory, without return.";
2204 break;
2205 case "stseth":
2206 instructionInfo = "Atomic bit set on halfword in memory, without return.";
2207 break;
2208 case "stsetlh":
2209 instructionInfo = "Atomic bit set on halfword in memory, without return.";
2210 break;
2211 case "stsmax":
2212 instructionInfo = "Atomic signed maximum on word or doubleword in memory, without return.";
2213 break;
2214 case "stsmaxl":
2215 instructionInfo = "Atomic signed maximum on word or doubleword in memory, without return.";
2216 break;
2217 case "stsmaxb":
2218 instructionInfo = "Atomic signed maximum on byte in memory, without return.";
2219 break;
2220 case "stsmaxlb":
2221 instructionInfo = "Atomic signed maximum on byte in memory, without return.";
2222 break;
2223 case "stsmaxh":
2224 instructionInfo = "Atomic signed maximum on halfword in memory, without return.";
2225 break;
2226 case "stsmaxlh":
2227 instructionInfo = "Atomic signed maximum on halfword in memory, without return.";
2228 break;
2229 case "stsmin":
2230 instructionInfo = "Atomic signed minimum on word or doubleword in memory, without return.";
2231 break;
2232 case "stsminl":
2233 instructionInfo = "Atomic signed minimum on word or doubleword in memory, without return.";
2234 break;
2235 case "stsminb":
2236 instructionInfo = "Atomic signed minimum on byte in memory, without return.";
2237 break;
2238 case "stsminlb":
2239 instructionInfo = "Atomic signed minimum on byte in memory, without return.";
2240 break;
2241 case "stsminh":
2242 instructionInfo = "Atomic signed minimum on halfword in memory, without return.";
2243 break;
2244 case "stsminlh":
2245 instructionInfo = "Atomic signed minimum on halfword in memory, without return.";
2246 break;
2247 case "stumax":
2248 instructionInfo = "Atomic unsigned maximum on word or doubleword in memory, without return.";
2249 break;
2250 case "stumaxl":
2251 instructionInfo = "Atomic unsigned maximum on word or doubleword in memory, without return.";
2252 break;
2253 case "stumaxb":
2254 instructionInfo = "Atomic unsigned maximum on byte in memory, without return.";
2255 break;
2256 case "stumaxlb":
2257 instructionInfo = "Atomic unsigned maximum on byte in memory, without return.";
2258 break;
2259 case "stumaxh":
2260 instructionInfo = "Atomic unsigned maximum on halfword in memory, without return.";
2261 break;
2262 case "stumaxlh":
2263 instructionInfo = "Atomic unsigned maximum on halfword in memory, without return.";
2264 break;
2265 case "stumin":
2266 instructionInfo = "Atomic unsigned minimum on word or doubleword in memory, without return.";
2267 break;
2268 case "stuminl":
2269 instructionInfo = "Atomic unsigned minimum on word or doubleword in memory, without return.";
2270 break;
2271 case "stuminb":
2272 instructionInfo = "Atomic unsigned minimum on byte in memory, without return.";
2273 break;
2274 case "stuminlb":
2275 instructionInfo = "Atomic unsigned minimum on byte in memory, without return.";
2276 break;
2277 case "stuminh":
2278 instructionInfo = "Atomic unsigned minimum on halfword in memory, without return.";
2279 break;
2280 case "stuminlh":
2281 instructionInfo = "Atomic unsigned minimum on halfword in memory, without return.";
2282 break;
2283 case "swpa":
2284 instructionInfo = "Swap word or doubleword in memory.";
2285 break;
2286 case "swpal":
2287 instructionInfo = "Swap word or doubleword in memory.";
2288 break;
2289 case "swp":
2290 instructionInfo = "Swap word or doubleword in memory.";
2291 break;
2292 case "swpl":
2293 instructionInfo = "Swap word or doubleword in memory.";
2294 break;
2295 case "swpab":
2296 instructionInfo = "Swap byte in memory.";
2297 break;
2298 case "swpalb":
2299 instructionInfo = "Swap byte in memory.";
2300 break;
2301 case "swpb":
2302 instructionInfo = "Swap byte in memory.";
2303 break;
2304 case "swplb":
2305 instructionInfo = "Swap byte in memory.";
2306 break;
2307 case "swpah":
2308 instructionInfo = "Swap halfword in memory.";
2309 break;
2310 case "swpalh":
2311 instructionInfo = "Swap halfword in memory.";
2312 break;
2313 case "swph":
2314 instructionInfo = "Swap halfword in memory.";
2315 break;
2316 case "swplh":
2317 instructionInfo = "Swap halfword in memory.";
2318 break;
2319 case "fjcvtzs":
2320 instructionInfo = "Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero.";
2321 break;
2322 case "fcmla":
2323 instructionInfo = "Floating-point Complex Multiply Accumulate (by element).";
2324 break;
2325 case "fmlal":
2326 instructionInfo = "Floating-point fused Multiply-Add Long to accumulator (by element).";
2327 break;
2328 case "":
2329 instructionInfo = "Floating-point fused Multiply-Add Long to accumulator (by element).";
2330 break;
2331 case "fmlsl":
2332 instructionInfo = "Floating-point fused Multiply-Subtract Long from accumulator (by element).";
2333 break;
2334 case "sqrdmlah":
2335 instructionInfo = "Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element).";
2336 break;
2337 case "sqrdmlsh":
2338 instructionInfo = "Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element).";
2339 break;
2340 case "fcadd":
2341 instructionInfo = "Floating-point Complex Add.";
2342 break;
2343 case "sdot":
2344 instructionInfo = "Dot Product signed arithmetic (vector, by element).";
2345 break;
2346 case "sxtl":
2347 instructionInfo = "Signed extend Long.";
2348 break;
2349 case "sxtl2":
2350 instructionInfo = "Signed extend Long.";
2351 break;
2352 case "udot":
2353 instructionInfo = "Dot Product unsigned arithmetic (vector, by element).";
2354 break;
2355 case "uxtl":
2356 instructionInfo = "Unsigned extend Long.";
2357 break;
2358 case "uxtl2":
2359 instructionInfo = "Unsigned extend Long.";
2360 break;
2361 case "bcax":
2362 instructionInfo = "SHA3 Bit Clear and XOR.";
2363 break;
2364 case "eor3":
2365 instructionInfo = "SHA3 Three-way Exclusive OR.";
2366 break;
2367 case "rax1":
2368 instructionInfo = "SHA3 Rotate and Exclusive OR.";
2369 break;
2370 case "sha512h2":
2371 instructionInfo = "SHA512 Hash update part 2.";
2372 break;
2373 case "sha512h":
2374 instructionInfo = "SHA512 Hash update part 1.";
2375 break;
2376 case "sha512su0":
2377 instructionInfo = "SHA512 Schedule Update 0.";
2378 break;
2379 case "sha512su1":
2380 instructionInfo = "SHA512 Schedule Update 1.";
2381 break;
2382 case "sm3partw1":
2383 instructionInfo = "SM3 three-way exclusive OR on the combination of three 128-bit vectors.";
2384 break;
2385 case "sm3partw2":
2386 instructionInfo = "SM3 three-way exclusive OR on the combination of three 128-bit vectors.";
2387 break;
2388 case "sm3ss1":
2389 instructionInfo = "SM3 perform rotates and adds on three 128-bit vectors combined into a destination 128-bit SIMD and FP register.";
2390 break;
2391 case "sm3tt1a":
2392 instructionInfo = "SM3 three-way exclusive OR on the combination of three 128-bit vectors and a 2-bit immediate index value.";
2393 break;
2394 case "sm3tt1b":
2395 instructionInfo = "SM3 perform 32-bit majority function on the combination of three 128-bit vectors and 2-bit immediate index value.";
2396 break;
2397 case "sm3tt2a":
2398 instructionInfo = "SM3 three-way exclusive OR of combined three 128-bit vectors and a 2-bit immediate index value.";
2399 break;
2400 case "sm3tt2b":
2401 instructionInfo = "SM3 perform 32-bit majority function on the combination of three 128-bit vectors and 2-bit immediate index value.";
2402 break;
2403 case "sm4e":
2404 instructionInfo = "SM4 Encode.";
2405 break;
2406 case "sm4ekey":
2407 instructionInfo = "SM4 Key.";
2408 break;
2409 case "xar":
2410 instructionInfo = "SHA3 Exclusive OR and Rotate.";
2411 break;
2412 case "vaba":
2413 instructionInfo = "Absolute difference and Accumulate, Absolute difference and Accumulate Long.";
2414 break;
2415 case "vabl":
2416 instructionInfo = "Absolute difference and Accumulate, Absolute difference and Accumulate Long.";
2417 break;
2418 case "vabd":
2419 instructionInfo = "Absolute difference, Absolute difference Long.";
2420 break;
2421 case "vabdl":
2422 instructionInfo = "Absolute difference, Absolute difference Long.";
2423 break;
2424 case "vacge":
2425 instructionInfo = "Absolute Compare Greater than or Equal, Greater Than.";
2426 break;
2427 case "vacgt":
2428 instructionInfo = "Absolute Compare Greater than or Equal, Greater Than.";
2429 break;
2430 case "vacle":
2431 instructionInfo = "Absolute Compare Less than or Equal, Less Than (pseudo-instructions).";
2432 break;
2433 case "vaclt":
2434 instructionInfo = "Absolute Compare Less than or Equal, Less Than (pseudo-instructions).";
2435 break;
2436 case "vaddhn":
2437 instructionInfo = "Add, select High half.";
2438 break;
2439 case "vand":
2440 instructionInfo = "Bitwise AND.";
2441 break;
2442 case "vbic":
2443 instructionInfo = "Bitwise Bit Clear (register).";
2444 break;
2445 case "vbif":
2446 instructionInfo = "Bitwise Insert if False.";
2447 break;
2448 case "vbit":
2449 instructionInfo = "Bitwise Insert if True.";
2450 break;
2451 case "vbsl":
2452 instructionInfo = "Bitwise Select.";
2453 break;
2454 case "vceq":
2455 instructionInfo = "Compare Equal.";
2456 break;
2457 case "vcge":
2458 instructionInfo = "Compare Greater than or Equal.";
2459 break;
2460 case "vcgt":
2461 instructionInfo = "Compare Greater Than.";
2462 break;
2463 case "vcle":
2464 instructionInfo = "Compare Less than or Equal.";
2465 break;
2466 case "vcls":
2467 instructionInfo = "Count Leading Sign bits.";
2468 break;
2469 case "vcnt":
2470 instructionInfo = "Count set bits.";
2471 break;
2472 case "vclt":
2473 instructionInfo = "Compare Less Than.";
2474 break;
2475 case "vclz":
2476 instructionInfo = "Count Leading Zeros.";
2477 break;
2478 case "vcvt":
2479 instructionInfo = "Convert fixed-point or integer to floating point, floating-point to integer or fixed-point.";
2480 break;
2481 case "vdup":
2482 instructionInfo = "Duplicate scalar to all lanes of vector.";
2483 break;
2484 case "veor":
2485 instructionInfo = "Bitwise Exclusive OR.";
2486 break;
2487 case "vext":
2488 instructionInfo = "Extract.";
2489 break;
2490 case "vfma":
2491 instructionInfo = "Fused Multiply Accumulate, Fused Multiply Subtract (vector).";
2492 break;
2493 case "vfms":
2494 instructionInfo = "Fused Multiply Accumulate, Fused Multiply Subtract (vector).";
2495 break;
2496 case "vhadd":
2497 instructionInfo = "Halving Add.";
2498 break;
2499 case "vhsub":
2500 instructionInfo = "Halving Subtract.";
2501 break;
2502 case "vld":
2503 case "vld1":
2504 case "vld2":
2505 case "vld3":
2506 case "vld4":
2507 instructionInfo = "Vector Load.";
2508 break;
2509 case "vmax":
2510 instructionInfo = "Maximum, Minimum.";
2511 break;
2512 case "vmin":
2513 instructionInfo = "Maximum, Minimum.";
2514 break;
2515 case "vmla":
2516 instructionInfo = "Multiply Accumulate (vector).";
2517 break;
2518 case "vmls":
2519 instructionInfo = "Multiply Subtract (vector).";
2520 break;
2521 case "vmovl":
2522 instructionInfo = "Move Long (register).";
2523 break;
2524 case "vmovn":
2525 instructionInfo = "Move Narrow (register).";
2526 break;
2527 case "vmvn":
2528 instructionInfo = "Move Negative (immediate).";
2529 break;
2530 case "vneg":
2531 instructionInfo = "Negate.";
2532 break;
2533 case "vorn":
2534 instructionInfo = "Bitwise OR NOT.";
2535 break;
2536 case "vorr":
2537 instructionInfo = "Bitwise OR (register).";
2538 break;
2539 case "vpadal":
2540 instructionInfo = "Pairwise Add and Accumulate Long.";
2541 break;
2542 case "vpadd":
2543 instructionInfo = "Pairwise Add.";
2544 break;
2545 case "vpmax":
2546 instructionInfo = "Pairwise Maximum, Pairwise Minimum.";
2547 break;
2548 case "vpmin":
2549 instructionInfo = "Pairwise Maximum, Pairwise Minimum.";
2550 break;
2551 case "vqabs":
2552 instructionInfo = "Absolute value, saturate.";
2553 break;
2554 case "vqadd":
2555 instructionInfo = "Add, saturate.";
2556 break;
2557 case "vqdmlal":
2558 instructionInfo = "Saturating Doubling Multiply Accumulate, and Multiply Subtract.";
2559 break;
2560 case "vqdmlsl":
2561 instructionInfo = "Saturating Doubling Multiply Accumulate, and Multiply Subtract.";
2562 break;
2563 case "vqdmull":
2564 instructionInfo = "Saturating Doubling Multiply.";
2565 break;
2566 case "vqdmulh":
2567 instructionInfo = "Saturating Doubling Multiply returning High half.";
2568 break;
2569 case "vqmovn":
2570 instructionInfo = "Saturating Move (register).";
2571 break;
2572 case "vqneg":
2573 instructionInfo = "Negate, saturate.";
2574 break;
2575 case "vqrdmulh":
2576 instructionInfo = "Saturating Doubling Multiply returning High half.";
2577 break;
2578 case "vqrshl":
2579 instructionInfo = "Shift Left, Round, saturate (by signed variable).";
2580 break;
2581 case "vqrshrn":
2582 instructionInfo = "Shift Right, Round, saturate (by immediate).";
2583 break;
2584 case "vqshl":
2585 instructionInfo = "Shift Left, saturate (by immediate).";
2586 break;
2587 case "vqshrn":
2588 instructionInfo = "Shift Right, saturate (by immediate).";
2589 break;
2590 case "vqsub":
2591 instructionInfo = "Subtract, saturate.";
2592 break;
2593 case "vraddhn":
2594 instructionInfo = "Add, select High half, Round.";
2595 break;
2596 case "vrecpe":
2597 instructionInfo = "Reciprocal Estimate.";
2598 break;
2599 case "vrecps":
2600 instructionInfo = "Reciprocal Step.";
2601 break;
2602 case "vrev":
2603 case "vrev16":
2604 case "vrev32":
2605 case "vrev64":
2606 instructionInfo = "Reverse elements.";
2607 break;
2608 case "vrhadd":
2609 instructionInfo = "Halving Add, Round.";
2610 break;
2611 case "vrshr":
2612 instructionInfo = "Shift Right and Round (by immediate).";
2613 break;
2614 case "vrshrn":
2615 instructionInfo = "Shift Right, Round, Narrow (by immediate).";
2616 break;
2617 case "vrsqrte":
2618 instructionInfo = "Reciprocal Square Root Estimate.";
2619 break;
2620 case "vrsqrts":
2621 instructionInfo = "Reciprocal Square Root Step.";
2622 break;
2623 case "vrsra":
2624 instructionInfo = "Shift Right, Round, and Accumulate (by immediate).";
2625 break;
2626 case "vrsubhn":
2627 instructionInfo = "Subtract, select High half, Round.";
2628 break;
2629 case "vshl":
2630 instructionInfo = "Shift Left (by immediate).";
2631 break;
2632 case "vshr":
2633 instructionInfo = "Shift Right (by immediate).";
2634 break;
2635 case "vshrn":
2636 instructionInfo = "Shift Right, Narrow (by immediate).";
2637 break;
2638 case "vsli":
2639 instructionInfo = "Shift Left and Insert.";
2640 break;
2641 case "vsra":
2642 instructionInfo = "Shift Right, Accumulate (by immediate).";
2643 break;
2644 case "vsri":
2645 instructionInfo = "Shift Right and Insert.";
2646 break;
2647 case "vst":
2648 case "vst1":
2649 case "vst2":
2650 case "vst3":
2651 case "vst4":
2652 instructionInfo = "Vector Store.";
2653 break;
2654 case "vsubhn":
2655 instructionInfo = "Subtract, select High half.";
2656 break;
2657 case "vswp":
2658 instructionInfo = "Swap vectors.";
2659 break;
2660 case "vtbl":
2661 instructionInfo = "Vector table look-up.";
2662 break;
2663 case "vtbx":
2664 instructionInfo = "Vector table look-up.";
2665 break;
2666 case "vtrn":
2667 instructionInfo = "Vector transpose.";
2668 break;
2669 case "vtst":
2670 instructionInfo = "Test bits.";
2671 break;
2672 case "vuzp":
2673 instructionInfo = "Vector de-interleave.";
2674 break;
2675 case "vzip":
2676 instructionInfo = "Vector interleave.";
2677 break;
2678 case "vldm":
2679 case "vldmia":
2680 case "vldmdb":
2681 instructionInfo = "Load multiple.";
2682 break;
2683 case "vldr":
2684 instructionInfo = "Load (see also VLDR pseudo-instruction).";
2685 break;
2686 case "vmrs":
2687 instructionInfo = "Transfer from NEON and VFP system register to ARM register.";
2688 break;
2689 case "vmsr":
2690 instructionInfo = "Transfer from ARM register to NEON and VFP system register.";
2691 break;
2692 case "vpop":
2693 instructionInfo = "Pop VFP or NEON registers from full-descending stack.";
2694 break;
2695 case "vpush":
2696 instructionInfo = "Push VFP or NEON registers to full-descending stack.";
2697 break;
2698 case "vstm":
2699 case "vstmia":
2700 instructionInfo = "Store multiple.";
2701 break;
2702 case "vstr":
2703 instructionInfo = "Store.";
2704 break;
2705 case "vcmp":
2706 instructionInfo = "Compare.";
2707 break;
2708 case "vcmpe":
2709 instructionInfo = "Compare.";
2710 break;
2711 case "vcvtb":
2712 instructionInfo = "Convert between half-precision and single-precision floating-point.";
2713 break;
2714 case "vcvtt":
2715 instructionInfo = "Convert between half-precision and single-precision floating-point.";
2716 break;
2717 case "vdiv":
2718 instructionInfo = "Divide.";
2719 break;
2720 case "vfnma":
2721 instructionInfo = "Fused multiply accumulate with negation, Fused multiply subtract with negation.";
2722 break;
2723 case "vfnms":
2724 instructionInfo = "Fused multiply accumulate with negation, Fused multiply subtract with negation.";
2725 break;
2726 case "vnmla":
2727 instructionInfo = "Negated multiply accumulate.";
2728 break;
2729 case "vnmls":
2730 instructionInfo = "Negated multiply subtract.";
2731 break;
2732 case "vnmul":
2733 instructionInfo = "Negated multiply.";
2734 break;
2735 case "vsqrt":
2736 instructionInfo = "Square Root.";
2737 break;
2738 case "push":
2739 instructionInfo = "Push registers onto a full descending stack.";
2740 break;
2741 case "pop":
2742 instructionInfo = "Pop registers of a full descending stack.";
2743 break;
2744 case "pkhbt":
2745 case "pkhtb":
2746 instructionInfo = "Halfword Packing instructions. Combine a halfword from one register with a halfword from another register.";
2747 break;
2748 default:
2749 instructionInfo = string.Empty;
2750 returnValue = false;
2751 break;
2752 }
2753
2754 return returnValue;
2755 }
2756 }
2757 }
2758}