use core::{
    panic::PanicInfo,
    sync::atomic::{Ordering, compiler_fence},
};

#[cfg(not(feature = "defmt"))]
#[inline(never)]
#[panic_handler]
fn panic_reset(_info: &PanicInfo) -> ! {
    cortex_m::interrupt::disable();

    // Halt execution and reset the chip.
    compiler_fence(Ordering::SeqCst);
    cortex_m::peripheral::SCB::sys_reset();
}