1{ lib 2, buildPythonPackage 3, fetchPypi 4, pythonOlder 5, jinja2 6, ply 7, verilog 8, pytest-pythonpath 9, pytestCheckHook 10}: 11 12buildPythonPackage rec { 13 pname = "pyverilog"; 14 version = "1.3.0"; 15 16 src = fetchPypi { 17 inherit pname version; 18 sha256 = "1a74k8r21swmfwvgv4c014y6nbcyl229fspxw89ygsgb0j83xnar"; 19 }; 20 21 disabled = pythonOlder "3.7"; 22 23 patchPhase = '' 24 # The path to Icarus can still be overridden via an environment variable at runtime. 25 substituteInPlace pyverilog/vparser/preprocessor.py \ 26 --replace "iverilog = 'iverilog'" "iverilog = '${verilog}/bin/iverilog'" 27 ''; 28 29 propagatedBuildInputs = [ 30 jinja2 31 ply 32 verilog 33 ]; 34 35 checkInputs = [ 36 pytest-pythonpath 37 pytestCheckHook 38 ]; 39 40 meta = with lib; { 41 homepage = "https://github.com/PyHDI/Pyverilog"; 42 description = "Python-based Hardware Design Processing Toolkit for Verilog HDL"; 43 license = licenses.asl20; 44 maintainers = with maintainers; [ trepetti ]; 45 }; 46}