pyrox.dev
1{ stdenv, fetchFromGitHub, fetchFromBitbucket
2, pkgconfig, tcl, readline, libffi, python3, bison, flex
3}:
4
5with builtins;
6
7stdenv.mkDerivation rec {
8 name = "yosys-${version}";
9 version = "2018.02.14";
10
11 srcs = [
12 (fetchFromGitHub {
13 owner = "yosyshq";
14 repo = "yosys";
15 rev = "c1abd3b02cab235334342f3520e2535eb74c5792";
16 sha256 = "0pzrplv4p0qzy115rg19lxv4w274iby337zfd7hhlinnpx3gzqvw";
17 name = "yosys";
18 })
19
20 # NOTE: the version of abc used here is synchronized with
21 # the one in the yosys Makefile of the version above;
22 # keep them the same for quality purposes.
23 (fetchFromBitbucket {
24 owner = "alanmi";
25 repo = "abc";
26 rev = "6e3c24b3308a";
27 sha256 = "1i4wv0si4fb6dpv2yrpkp588mdlfrnx2s02q2fgra5apdm54c53w";
28 name = "yosys-abc";
29 })
30 ];
31 sourceRoot = "yosys";
32
33 enableParallelBuilding = true;
34 nativeBuildInputs = [ pkgconfig ];
35 buildInputs = [ tcl readline libffi python3 bison flex ];
36
37 patchPhase = ''
38 substituteInPlace ./Makefile \
39 --replace 'echo UNKNOWN' 'echo ${substring 0 10 (elemAt srcs 0).rev}'
40 '';
41
42 preBuild = ''
43 chmod -R u+w ../yosys-abc
44 ln -s ../yosys-abc abc
45 make config-gcc
46 echo 'ABCREV := default' >> Makefile.conf
47 makeFlags="PREFIX=$out $makeFlags"
48 '';
49
50 meta = {
51 description = "Framework for RTL synthesis tools";
52 longDescription = ''
53 Yosys is a framework for RTL synthesis tools. It currently has
54 extensive Verilog-2005 support and provides a basic set of
55 synthesis algorithms for various application domains.
56 Yosys can be adapted to perform any synthesis job by combining
57 the existing passes (algorithms) using synthesis scripts and
58 adding additional passes as needed by extending the yosys C++
59 code base.
60 '';
61 homepage = http://www.clifford.at/yosys/;
62 license = stdenv.lib.licenses.isc;
63 maintainers = with stdenv.lib.maintainers; [ shell thoughtpolice ];
64 platforms = stdenv.lib.platforms.linux;
65 };
66}