Summary#
Build the low-level infrastructure for JIT compilation: an AArch64 machine code assembler, executable memory allocation, and the interface between interpreted and JIT-compiled code.
Background#
The JS engine uses register-based bytecode designed for JIT from day one. This issue implements the assembler layer that translates high-level JIT IR or bytecode directly into AArch64 machine code. This is unsafe code (allowed in the js crate per CLAUDE.md).
Acceptance Criteria#
- Executable memory allocator:
mmapwithPROT_READ | PROT_WRITE | PROT_EXEC(or W^X withmprotectflip) -
JitBufferstruct: manages allocated code pages, tracks used/free space -
Assemblerstruct with methods to emit AArch64 instructions:- Arithmetic:
add,sub,mul,sdiv(register and immediate forms) - Logic:
and,orr,eor,lsl,lsr,asr - Memory:
ldr,str(register offset, immediate offset, pre/post-index) - Branch:
b,b.cond,bl,blr,br,ret,cbz,cbnz - Comparison:
cmp,tst - Move:
mov,movz,movk(for loading 64-bit immediates) - FP:
fmov,fadd,fsub,fmul,fdiv,fcmp,scvtf,fcvtzs(for f64 arithmetic)
- Arithmetic:
- Instruction encoding tests: verify each emitted instruction matches expected byte patterns
-
CodePtrtype wrapping a function pointer for calling into JIT code - Entry/exit stubs: save/restore callee-saved registers, set up frame pointer, bridge between VM and JIT code
- AArch64 calling convention support (registers x0-x7 for args, x8 for indirect result, x19-x28 callee-saved)
Implementation Notes#
- All JIT code lives in
crates/js/src/jit/(new module) - Use
libc::mmap/libc::mprotect/libc::munmapfor memory management (these are syscalls, not external crates) - W^X policy: write code with PROT_WRITE, then flip to PROT_READ|PROT_EXEC before execution
- AArch64 instructions are fixed 32-bit width — encoding is straightforward
- The assembler should support label-based forward references with backpatching (similar to bytecode jump patching)
unsafeis allowed here per CLAUDE.md (JIT compiler)
Dependencies#
None — can be developed in parallel with shape/IC work.
Phase#
Phase 15: Performance