nonbinary.computer
OR-1 dataflow CPU sketch
1> **⚠ SUPERSEDED** — This was an early syntax sketch. The canonical grammar
2> is `dfasm.lark` (Lark/Earley parser, 38+ tests in `tests/test_parser.py`).
3> Mnemonics, naming conventions, and some semantics have diverged from this
4> sketch. Preserved for historical context and design rationale only.
5
6## Ops
7
8### CM tokens
9Type 1 (0b00)
10 - token carries operand for a dyadic (two-input) instruction. requires matching store lookup.
11Type 2 (0b01)
12 - token carries operand for a monadic (single-input) instruction. bypasses matching store.
13
14#### Fields
15 - offset instruction slot
16 - ctx execution context (data) slot
17 - port L/R operand discriminator (dyadic)
18 - gen generation counter (dyadic)
19 - inl|wid inline flag on monadic ops, width flag on dyadic ops
20 - data
21
22
23### ALU - Arithmetic Logic Unit (Control Memory module)
24 - 5-bit opcode (initial)
25 - opcodes not present on bus except as part of `cfg` token data words
26
27#### Arithmetic
28- add
29- sub
30- inc (monadic)
31- dec (monadic)
32
33NOTE: could we re-use the same opcodes for add/sub and inc/dec?
34everything about them is essentially the same except for dyadic/monadic
35
36**Shifts** (monadic)
37- shiftl - Shift A left by N+1 bits. N from IRAM immediate field (1-8 allow for shifting of a full byte's width)
38- shiftr - Logical shift A right by N+1 bits. Zero-fill. N from immediate.
39- ashftr - Arithmetic shift A right by N bits. Sign-extend. N from immediate.
40 (NOTE: implementation uses `shl`/`shr`/`asr` mnemonics — see `alu-and-output-design.md`)
41
42#### Logical
43- and
44- or
45- xor
46- not (monadic)
47
48**Comparison**
49- eq
50- lt (do we want explicit signed/unsigned?)
51- lte
52- gt
53- gte
54
55#### Routing/switching/branching
56All of these have perhaps odd wire semantics (see alu-and-output-design.md)
57
58- br(eq/gt/ge/of/ty) - branch plus continue|local bit
59- sw(eq/gt/ge/of/ty) - branch plus output enable
60- gate - pass or suppress
61- sel
62- merge
63
64
65#### Data (all monadic)
66- pass
67- const - constant load
68- free_ctx - dealloc context slot, no data output
69
70
71#### System (Type 4)
72PE_id bits repurposed as subtype
73
74**iop**
75 - r
76 - w
77 - rw
78fields:
79 - dest
80 - addr|payload1
81 - data|payload2
82**cfg**
83 - load_inst
84 - fields:
85 - dest
86 - addr
87 - data_l
88 - data_h
89 - ...chainable (data_l, data_h) to enable efficient loading of sequential addresses
90 - route_set
91 - fields:
92 - dest
93 - data (address mapping)
94 -
95
96plus 2 reserved
97
98
99
100### MLU - Memory Logic Unit (Structure Memory module)
101Type 3 (0b10) token
102- 3-4 bit ext opcode + 9-8 bit internal addr
103- 4+ bit internal opcode + 12-bit internal addr
104
105#### Fields
106- SM id
107- opcode
108- flags (in extended mode)
109- data
110- return route
111
112# Syntax
113
114```vhdl
115@output <| op L, R
116; or
117op L, R |> @out1, @out2
118```
119direction doesn't dictate number of outputs
120direction could dictate strong/weak connections
121- `@name` refers to a node
122- can be chained with | to manually specify a PE (e.g. `@sum|pe0` )
123- opcode or node can be chained with `:` to manually specify an iram addr or
124 context slot (e.g. `sub:0x02`) or L|R
125- NO spaces allowed in chains
126- `$name` refers to a function/subroutine/subgraph label, same rules as above
127- alternatively an opcode plus any const arg can be labeled as: `&label <| op, arg`
128- `;` for comments, as is tradition, this is ASM
129- named args for clarity are allowed
130```vhdl
131@serial <| r dest=0x45, addr=0x91, data=0x43
132```
133function definition:
134```vhdl
135$fib |> {
136 &const_n <| const, 10
137 &sub1 <| sub
138 &sub2 <| sub
139 &branch <| switch
140
141 &const_n |> &branch:L
142 &const_n |> &sub1:L
143 &const_n |> &sub1:R
144 &const_n |> &sub2:R
145 &sub1 |> &recurse_a:L
146 ; ...
147}
148```
149for initial data:
150 - if it should start resident in SM, use `=` with a name or label expression
151 ```typescript
152 @hello = #str "hello"
153 ```
154 - `#` denotes a macro, (here, 'str') which expands the above to something more like
155```vhdl
156@hello|sm0:0 = 0x05 ; length
157@hello|sm0:1 = 'h','e' ; 16-bit data slots can hold 2 utf8/ascii chars
158@hello|sm0:2 = 'l','l'
159...
160```
161
162loading:
163 - initial program loading happens via a generated (or explicit) series of cfg and sm instructions
164
165 inst_defs and adjacent edges are collected and transformed into a series of load_inst calls