nonbinary.computer
OR-1 dataflow CPU sketch
1# SRAM market for homebrew CPUs: what you can actually buy in 2026
2
3**Alliance Memory is the last manufacturer standing for DIP-package SRAM, and their lineup is surprisingly complete.** You can get 8KB through 512KB parts in DIP at $3–9 each, all at 55ns, all in current production and stocked at DigiKey and Mouser. The bad news: dual-port SRAMs and FIFO chips are extinct in production — only NOS remains — and the AT28C256 EEPROM has hit **$11.62** on its way to full obsolescence. The good news: SMD parts offer 8–15ns access times and 16-bit-wide organization that don't exist in DIP, and adapter boards make them breadboard-usable. For your dataflow architecture specifically, a combination of AS6C62256 (32Kx8) for per-PE memories, AS6C1008 (128Kx8) for SM bulk storage, NOS IDT7201 FIFOs while they last, and ATF1504 CPLDs for future-proof FIFO control gives you the best cost/complexity/availability tradeoff.
4
5---
6
7## The Alliance Memory lineup: your four real options in DIP
8
9Alliance Memory is effectively a monopoly supplier for through-hole SRAM. No other manufacturer — not ISSI, not Cypress/Infineon, not Renesas — still produces DIP-package async SRAM. Alliance's parts run on **2.7–5.5V** (compatible with both 3.3V and 5V logic) and carry 55ns access times across the board.
10
11| Part | Organization | Package | Speed | Qty 1 | Qty 25 | Qty 50 | $/KB |
12|---|---|---|---|---|---|---|---|
13| **AS6C6264-55PCN** | 8Kx8 | DIP-28 | 55ns | $3.30 | $2.95 | $2.70 | $0.41 |
14| **AS6C62256-55PCN** | 32Kx8 | DIP-28 | 55ns | $3.79 | $3.36 | $2.77 | $0.12 |
15| **AS6C1008-55PCN** | 128Kx8 | DIP-32 | 55ns | $5.90 | $5.30 | $4.80 | $0.046 |
16| **AS6C4008-55PCN** | 512Kx8 | DIP-32 | 55ns | $8.50 | $7.50 | $6.80 | $0.017 |
17
18There is one outlier worth noting: the **AS7C256B-15PIN**, a 32Kx8 at **15ns** in a narrow (0.3") DIP-28, 5V-only, at ~$3.10. This is the fastest DIP SRAM currently manufactured — roughly 3.5x faster than the low-power series. It exists because Alliance still makes a "fast async" product line alongside their low-power line.
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20The 6116 (2Kx8), 2114 (1Kx4), and all Cypress CY62256 parts are **gone from production**. The 6116 can be found as NOS on eBay for $5–10 but Alliance never made a replacement — their smallest is the 6264. The practical advice from the retro community is unanimous: just use an AS6C62256 and decode only the address space you need. A 32KB chip serving 2KB costs the same as a vintage 2KB chip and is actually in stock.
21
22**No 16-bit-wide DIP SRAMs exist or have ever existed.** The pin count required (16 data + 15+ address + control = 35+ pins) exceeds practical DIP limits. All x16 SRAMs use SMD packages. The universal homebrew approach — used in every 68000 build — is to parallel two x8 chips with shared address lines.
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24---
25
26## Mapping parts to your dataflow architecture
27
28Your system has 4+ PEs and 2–4 SMs, each needing several memory subsystems. Here's how the available parts map to each:
29
30**Matching Store (per PE, 512–1024 x 16-bit = 1–2KB):** Two AS6C62256-55PCN in parallel give you **32Kx16** with single-cycle 16-bit access. Massive overkill on capacity but at $7.58/pair it's cheaper than hunting for smaller parts. Address lines A0–A9 cover your 1024-cell space; tie A10–A14 low or use them for future expansion. Alternatively, one AS7C256B-15PIN gives 8-bit-wide access at 15ns — fast enough for two sequential byte accesses within a single 100ns clock at 10MHz, avoiding the second chip entirely.
31
32**Instruction RAM (per PE, 128–256 x 24–48 bits):** For a 32-bit instruction word, use four AS6C6264-55PCN (8Kx8) in parallel for 8Kx32. That's $13.20 per PE. For 48-bit words, six chips at $19.80. The 8K depth gives you **32x more IRAM than minimum** — useful if instruction sets grow. If chip count matters more than depth headroom, three or four AS6C62256 chips work too (same price per chip, 4x the depth you won't use).
33
34**SM Data Memory (per SM, 2K–8K x 16-bit = 4–16KB):** Two AS6C1008-55PCN in parallel give **128Kx16 = 256KB** per SM at $11.80/pair. For I-structure presence bits (1 per cell), a single AS6C6264 provides **8K bytes = 64K bits** of presence storage, far exceeding your 8K-cell maximum. Total per SM: ~$15.10 for three chips.
35
36**Token FIFOs:** See the dedicated FIFO section below. Short answer: NOS IDT7201 (512x9) at $3–8 from eBay, or build from SRAM + ATF1504 CPLD.
37
38**Metadata (presence bitmaps, counters):** At 64–128 bytes, any SRAM is absurd overkill. Use a 74HC574 octal register ($0.50) for 8-bit counters, a 74HC670 4x4 register file for tiny lookup tables, or carve a few bytes from an existing SRAM via address decode. The AS6C6264 serving as your presence-bit store can also hold metadata in a separate address region.
39
40**Estimated total cost for a 4-PE, 2-SM system using DIP parts only** (SRAM/ROM, not counting logic ICs):
41
42| Subsystem | Chips needed | Per-unit | Total |
43|---|---|---|---|
44| Matching Stores (4 PEs × 2 chips) | 8× AS6C62256 | $2.77 | $22.16 |
45| IRAM (4 PEs × 4 chips for 32-bit) | 16× AS6C6264 | $2.70 | $43.20 |
46| SM Data Memory (2 SMs × 2 chips) | 4× AS6C1008 | $4.80 | $19.20 |
47| Presence Bits (2 SMs × 1 chip) | 2× AS6C6264 | $2.70 | $5.40 |
48| Bootstrap ROM (1× SM00) | 1× SST39SF010A | $2.89 | $2.89 |
49| **Total SRAM + ROM** | **31 chips** | | **$92.85** |
50
51All prices at qty 50 tiers. Every part is current production, stocked today at DigiKey and Mouser.
52
53---
54
55## Speed grades and what clock rate you can actually hit
56
57The 55ns DIP parts define a hard ceiling. In a 74HC-based system, address decode eats **20–45ns** (two to three gate delays at 10–15ns each, plus bus settling). That leaves this timing budget:
58
59| Target clock | Cycle time | After decode overhead | Required SRAM | Feasible? |
60|---|---|---|---|---|
61| **8 MHz** | 125ns | 80–105ns | 55ns ✅ | Comfortable |
62| **10 MHz** | 100ns | 55–80ns | 55ns ⚠️ | Tight but works with 2-gate decode |
63| **12.5 MHz** | 80ns | 35–60ns | 55ns ❌ / 25ns ✅ | Needs faster SRAM |
64| **16 MHz** | 62.5ns | 18–42ns | 15–20ns ✅ | SMD only |
65| **20 MHz** | 50ns | 5–30ns | 10–15ns ✅ | SMD + 74AHC decode |
66
67**For 10 MHz with 55ns DIP SRAMs:** achievable but requires disciplined address decode design — keep it to two gate delays maximum (e.g., one 74HC138 decoder directly generating chip selects). Adding a third decode stage pushes you past the margin.
68
69**The fast DIP option matters here.** The AS7C256B-15PIN at 15ns gives you comfortable margins up to **16 MHz** even with 74HC decode logic. At ~$3.10 each, it's actually cheaper than the 55ns AS6C62256. The tradeoff: it's 5V-only and uses a narrow 0.3" DIP body that sits oddly in breadboards designed for 0.6" chips. For PCBs this is irrelevant.
70
71In SMD, the picture improves dramatically. Alliance's AS7C34096A-10TCN (512Kx8, 10ns, TSOP-44) and ISSI's IS61WV51216BLL-10TLI (512Kx16, 10ns, TSOP-44) enable **20+ MHz** operation. TSOP-to-DIP adapter boards cost $4–6 from Proto-Advantage or can be fabbed at JLCPCB for pennies. The retro community on VOGONS has shared open-source adapter PCB designs specifically for this purpose.
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73---
74
75## The SMD advantage: 16-bit width and sub-15ns speed
76
77SMD SRAMs offer two capabilities that simply don't exist in DIP: native 16-bit data width and access times under 15ns. For a dataflow architecture with 16-bit data paths, these are transformative.
78
79The best 16-bit options currently available are the **Alliance AS7C4098A** (256Kx16, 12ns, 5V, TSOP-44) at ~$5.46 and the **ISSI IS61WV51216BLL-10TLI** (512Kx16, 10ns, 3.3V, TSOP-44) at ~$5.59. Both include separate UB#/LB# byte-select pins for individual byte writes. A single AS7C4098A replaces two parallel DIP SRAMs while being faster and cheaper — you'd save 50% of your matching-store chip count and gain 12ns access instead of 55ns.
80
81The fastest currently manufactured async SRAM appears to be the **ISSI IS61WV51216EDBLL-8TLI** at **8ns** with built-in ECC, and Alliance's **AS7C34096A-8TIN** (512Kx8, 8ns). These parts would support system clocks of 25+ MHz if paired with 74AHC decode logic (3–5ns propagation instead of 74HC's 10–15ns).
82
83For breadboarding, adapter boards are the key enabler. SOIC-28 to DIP-28 adapters are standardized (SparkFun BOB-00496 at $3, or generic boards in 5-packs for $8). TSOP-44 adapters are available from Proto-Advantage ($4–6) and Amazon. The soldering is manageable with a fine-tip iron and flux — 0.8mm pitch TSOP-II is well within hand-soldering territory.
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86
87## Pumping multiple accesses per clock: practical but not free
88
89With a 10 MHz clock (100ns) and 15ns SRAM, the arithmetic suggests ~6 accesses per cycle. Reality is less generous. Each sub-access needs address MUX propagation (~12ns for 74HC157), SRAM access (15ns), and data latch setup (~5ns) — roughly **32–40ns per sub-access**.
90
91**Two accesses per clock** is practical and well-proven. The BBC Micro and Commodore 64 both used this technique for interleaved CPU/video memory access. The bill of materials: **3–4× 74HC157** (address MUX), **1–2× 74HC574** (data latches), **1× 74HC74** (phase generator), and **1–2× 74HC00** (control logic) — about **8–10 extra chips** per memory port. At 10 MHz with 15ns SRAM, each 50ns half-cycle provides comfortable margins.
92
93**Four accesses per clock** requires 4:1 MUXes (74HC153, handling only 2 bits each), four sets of output latches, and tighter timing — **18–25 extra chips** with only ~7ns of margin per sub-phase. This is PCB-only territory and generally not worth the complexity.
94
95**The better alternative in most cases is simply using separate SRAM chips for separate memory functions** (Harvard architecture). Your matching store and IRAM are architecturally independent — putting them on separate chips with separate buses gives truly simultaneous access with zero timing complexity. The retro community is nearly unanimous on this: separate chips for separate functions beats time-division multiplexing every time. TDM makes sense only when you have one logical memory that genuinely needs two ports (like shared memory between a PE and an SM), and even then a CPLD-managed pseudo-dual-port approach is cleaner.
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98
99## Dual-port SRAM and FIFO chips: the NOS scavenger hunt
100
101**Every dedicated dual-port SRAM and FIFO chip in DIP has been discontinued.** The IDT7130/7132 (dual-port, 1–2Kx8 with BUSY/INT arbitration), the CY7C130/138 (Cypress equivalents), and the IDT7200/7201/7202 (256–1024x9 FIFOs with that useful 9th bit) are all confirmed EOL by Renesas. DIP packages went first; some PLCC and ceramic variants lingered but are in final last-time-buy.
102
103The secondary market remains viable for now. **IDT7201LA20TP** (512x9 FIFO, 20ns, DIP-28) runs **$3–8 on eBay** with multiple sellers showing stock. **IDT7132SA** (2Kx8 dual-port, DIP-48) is **$5–15 on eBay**. At these prices, buying 10–20 extras as spares is smart insurance. Authenticity risk exists with Chinese broker sites but established eBay sellers with good feedback selling clearly-marked NOS pulls are generally reliable.
104
105**The future-proof alternative is the ATF1504AS CPLD** ($3–6, PLCC-44, current production from Microchip) driving external SRAM. This is the last 5V-compatible CPLD still manufactured, it fits in through-hole PLCC sockets for breadboarding, and 64 macrocells can implement complete FIFO control logic (dual counters, full/empty/half-full flags, async handshaking) driving any commodity SRAM. An ATF1504 + AS6C62256 gives you a **32K-deep x 8-bit FIFO for ~$7 total** using entirely in-production parts. The retro community has embraced ATF150x CPLDs specifically because they bridge the 5V TTL world and modern programmable logic — WinCUPL II (updated August 2025) provides the toolchain.
106
107The 74HC40105 is technically the only currently-manufactured dedicated FIFO IC in DIP, but at **4 bits wide × 16 deep** it's nearly useless for token buffers. You'd need 8 chips just to get a 64-deep × 8-bit FIFO.
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110
111## Bootstrap ROM: skip the AT28C256, use SST39SF Flash
112
113The AT28C256-15PU EEPROM has become a cautionary tale in component economics. Once a $4 staple, it now commands **$11.62 at DigiKey** and is **backordered at Mouser with 15+ week lead times**. DigiKey marks it as obsolete with finite remaining stock. Microchip has effectively discontinued this product line.
114
115The **SST39SF series** is the clear replacement for bootstrap ROM. The SST39SF010A (128Kx8, 70ns, DIP-32) at **$2.89** provides 4x the capacity at one-quarter the price. The SST39SF040 (512Kx8) at **$3.87** gives 16x the capacity. These are genuine current-production parts with Microchip qualifying new manufacturing sites as recently as 2025. The tradeoff: sector erase (4KB granularity) instead of byte-write, which means you can't tweak individual bytes during development as conveniently as with an EEPROM. For a bootstrap ROM that gets programmed in bulk via a TL866/T48 programmer and then runs, this is a non-issue.
116
117One caveat: the **DIP-32 package specifically** (-PHE suffix) is getting harder to source at some distributors. Mouser shows it as non-stocked with a 34-week lead. DigiKey still has stock. Buy from DigiKey or stock up. The TSOP and PLCC package variants remain widely available.
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119For development where you want byte-level in-circuit reprogramming, the AT28C256 is worth its premium while stock lasts. Buy a few now. For the final build's bootstrap ROM, SST39SF is the right choice.
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122
123## Consolidation tradeoffs and the recommended architecture
124
125A single AS6C62256 can absolutely serve both a PE's matching store (~2KB) and IRAM (~1.5KB) via address partitioning — you'd use less than 15% of the 32KB capacity. The cost savings are real: one $2.77 chip instead of six. But the tradeoff is severe for a dataflow architecture: **a single-ported SRAM cannot serve two concurrent accesses**. If your PE needs to read an IRAM instruction and access the matching store in the same cycle, consolidation forces either a two-cycle operation or time-division multiplexing (adding 8–10 chips of MUX/latch/timing logic, which negates the chip-count savings).
126
127The retro community consensus, validated across dozens of builds, is to **keep functionally independent memories on separate chips**. The AS6C62256 at $2.77 qty 50 is cheap enough that saving one chip isn't worth the architectural constraint. Use separate chips for matching store and IRAM, with independent address and data buses, enabling true single-cycle parallel access. Reserve address-partitioned consolidation for memories that are never accessed simultaneously (e.g., metadata + presence bits within the same SM, where you sequence access across phases anyway).
128
129The strongest cost-optimization move isn't consolidation — it's **upgrading from DIP to SMD with adapter boards**. A single ISSI IS61WV51216BLL-10TLI (512Kx16, TSOP-44) at ~$5.59 on an adapter replaces two parallel DIP SRAMs at $5.54 combined, while being 5.5x faster and natively 16-bit wide. If your build will eventually move to PCB (likely, given 4 PEs + 2–4 SMs), designing around TSOP-44 footprints from the start saves both cost and board area while unlocking clock speeds well above 10 MHz.
130
131## Conclusion
132
133The DIP SRAM market has consolidated to a single manufacturer but remains remarkably healthy for hobbyist needs. **Alliance Memory's AS6C62256-55PCN is the new universal default** — cheap, stocked everywhere, and sufficient for most homebrew memory needs. The AS6C1008 and AS6C4008 extend the range to 128KB and 512KB. For your dataflow CPU specifically, the critical scarcity is in dual-port SRAMs and FIFOs, both of which are NOS-only; the ATF1504 CPLD bridges that gap elegantly with fully in-production parts. The AT28C256 EEPROM era is ending — SST39SF Flash takes over at a fraction of the cost. And if you're willing to solder SMD parts onto adapters, the 10–12ns 16-bit-wide SRAMs from Alliance and ISSI unlock a performance tier that makes 16–20 MHz single-cycle operation realistic in a 74HC-based design.