jonaskruckenberg.de
Next Generation WASM Microkernel Operating System
1// Copyright 2025 Jonas Kruckenberg
2//
3// Licensed under the Apache License, Version 2.0, <LICENSE-APACHE or
4// http://apache.org/licenses/LICENSE-2.0> or the MIT license <LICENSE-MIT or
5// http://opensource.org/licenses/MIT>, at your option. This file may not be
6// copied, modified, or distributed except according to those terms.
7
8use core::ops::{Deref, DerefMut};
9
10/// `CachePadded` wraps an inner type `T` applying architecture-specific padding to ensure the type
11/// takes up exactly one cache line on the target architecture. This avoids [false sharing].
12///
13/// The cache padding rules are copied from crossbeam-utils/src/cache_padded.rs
14///
15/// Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache
16/// lines at a time, so we have to align to 128 bytes rather than 64.
17///
18/// Sources:
19/// - <https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf>
20/// - <https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107>
21///
22/// ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size.
23///
24/// Sources:
25/// - <https://www.mono-project.com/news/2016/09/12/arm64-icache/>
26///
27/// powerpc64 has 128-byte cache line size.
28///
29/// Sources:
30/// - <https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9>
31///
32/// [false sharing]: <https://en.wikipedia.org/wiki/False_sharing>
33#[cfg_attr(
34 any(
35 target_arch = "x86_64",
36 target_arch = "aarch64",
37 target_arch = "powerpc64",
38 ),
39 repr(align(128))
40)]
41///
42/// arm, mips, mips64, sparc, and hexagon have 32-byte cache line size.
43///
44/// Sources:
45/// - <https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7>
46/// - <https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7>
47/// - <https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7>
48/// - <https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9>
49/// - <https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L17>
50/// - <https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/hexagon/include/asm/cache.h#L12>
51#[cfg_attr(
52 any(
53 target_arch = "arm",
54 target_arch = "mips",
55 target_arch = "mips64",
56 target_arch = "sparc",
57 target_arch = "hexagon",
58 ),
59 repr(align(32))
60)]
61///
62/// m68k has 16-byte cache line size.
63///
64/// Sources:
65/// - <https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/m68k/include/asm/cache.h#L9>
66#[cfg_attr(target_arch = "m68k", repr(align(16)))]
67///
68/// s390x has 256-byte cache line size.
69///
70/// Sources:
71/// - <https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7>
72/// - <https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/s390/include/asm/cache.h#L13>
73#[cfg_attr(target_arch = "s390x", repr(align(256)))]
74///
75/// x86, riscv, wasm, and sparc64 have 64-byte cache line size.
76///
77/// Sources:
78/// - <https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9>
79/// - <https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7>
80/// - <https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L19>
81/// - <https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/riscv/include/asm/cache.h#L10>
82///
83/// All others are assumed to have 64-byte cache line size.
84#[cfg_attr(
85 not(any(
86 target_arch = "x86_64",
87 target_arch = "aarch64",
88 target_arch = "powerpc64",
89 target_arch = "arm",
90 target_arch = "mips",
91 target_arch = "mips64",
92 target_arch = "sparc",
93 target_arch = "hexagon",
94 target_arch = "m68k",
95 target_arch = "s390x",
96 )),
97 repr(align(64))
98)]
99#[derive(Debug, Default, PartialEq, Eq, PartialOrd, Ord, Hash)]
100pub struct CachePadded<T>(pub T);
101
102impl<T> Deref for CachePadded<T> {
103 type Target = T;
104
105 fn deref(&self) -> &Self::Target {
106 &self.0
107 }
108}
109
110impl<T> DerefMut for CachePadded<T> {
111 fn deref_mut(&mut self) -> &mut Self::Target {
112 &mut self.0
113 }
114}
115
116impl<T> From<T> for CachePadded<T> {
117 fn from(value: T) -> Self {
118 Self(value)
119 }
120}