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"Das U-Boot" Source Tree
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * ARM PrimeCell Dual-Timer Module (SP804) driver
4 * Copyright (C) 2022 Arm Ltd.
5 */
6
7#include <clk.h>
8#include <dm.h>
9#include <init.h>
10#include <log.h>
11#include <asm/global_data.h>
12#include <dm/ofnode.h>
13#include <mapmem.h>
14#include <dt-structs.h>
15#include <timer.h>
16#include <asm/io.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20#define SP804_TIMERX_LOAD 0x00
21#define SP804_TIMERX_VALUE 0x04
22#define SP804_TIMERX_CONTROL 0x08
23
24#define SP804_CTRL_TIMER_ENABLE (1U << 7)
25#define SP804_CTRL_TIMER_PERIODIC (1U << 6)
26#define SP804_CTRL_INT_ENABLE (1U << 5)
27#define SP804_CTRL_TIMER_PRESCALE_SHIFT 2
28#define SP804_CTRL_TIMER_PRESCALE_MASK (3U << SP804_CTRL_TIMER_PRESCALE_SHIFT)
29#define SP804_CTRL_TIMER_32BIT (1U << 1)
30#define SP804_CTRL_ONESHOT (1U << 0)
31
32struct sp804_timer_plat {
33 uintptr_t base;
34};
35
36static u64 sp804_timer_get_count(struct udevice *dev)
37{
38 struct sp804_timer_plat *plat = dev_get_plat(dev);
39 uint32_t cntr = readl(plat->base + SP804_TIMERX_VALUE);
40
41 /* timers are down-counting */
42 return ~0u - cntr;
43}
44
45static int sp804_clk_of_to_plat(struct udevice *dev)
46{
47 struct sp804_timer_plat *plat = dev_get_plat(dev);
48
49 plat->base = dev_read_addr(dev);
50 if (!plat->base)
51 return -ENOENT;
52
53 return 0;
54}
55
56static int sp804_timer_probe(struct udevice *dev)
57{
58 struct sp804_timer_plat *plat = dev_get_plat(dev);
59 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
60 struct clk base_clk;
61 unsigned int divider = 1;
62 uint32_t ctlr;
63 int ret;
64
65 ctlr = readl(plat->base + SP804_TIMERX_CONTROL);
66 ctlr &= SP804_CTRL_TIMER_PRESCALE_MASK;
67 switch (ctlr >> SP804_CTRL_TIMER_PRESCALE_SHIFT) {
68 case 0x0: divider = 1; break;
69 case 0x1: divider = 16; break;
70 case 0x2: divider = 256; break;
71 case 0x3: printf("illegal!\n"); break;
72 }
73
74 ret = clk_get_by_index(dev, 0, &base_clk);
75 if (ret) {
76 printf("could not find SP804 timer base clock in DT\n");
77 return ret;
78 }
79
80 uc_priv->clock_rate = clk_get_rate(&base_clk) / divider;
81
82 /* keep divider, free-running, wrapping, no IRQs, 32-bit mode */
83 ctlr |= SP804_CTRL_TIMER_32BIT | SP804_CTRL_TIMER_ENABLE;
84 writel(ctlr, plat->base + SP804_TIMERX_CONTROL);
85
86 return 0;
87}
88
89static const struct timer_ops sp804_timer_ops = {
90 .get_count = sp804_timer_get_count,
91};
92
93static const struct udevice_id sp804_timer_ids[] = {
94 { .compatible = "arm,sp804" },
95 {}
96};
97
98U_BOOT_DRIVER(arm_sp804_timer) = {
99 .name = "arm_sp804_timer",
100 .id = UCLASS_TIMER,
101 .of_match = sp804_timer_ids,
102 .probe = sp804_timer_probe,
103 .ops = &sp804_timer_ops,
104 .plat_auto = sizeof(struct sp804_timer_plat),
105 .of_to_plat = sp804_clk_of_to_plat,
106};