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"Das U-Boot" Source Tree
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Renesas RZ/A1 R7S72100 OSTM Timer driver
4 *
5 * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
6 */
7
8#include <clock_legacy.h>
9#include <malloc.h>
10#include <asm/global_data.h>
11#include <asm/io.h>
12#include <dm.h>
13#include <clk.h>
14#include <timer.h>
15#include <linux/bitops.h>
16
17#define OSTM_CMP 0x00
18#define OSTM_CNT 0x04
19#define OSTM_TE 0x10
20#define OSTM_TS 0x14
21#define OSTM_TT 0x18
22#define OSTM_CTL 0x20
23#define OSTM_CTL_D BIT(1)
24
25DECLARE_GLOBAL_DATA_PTR;
26
27struct ostm_priv {
28 fdt_addr_t regs;
29};
30
31static u64 ostm_get_count(struct udevice *dev)
32{
33 struct ostm_priv *priv = dev_get_priv(dev);
34
35 return timer_conv_64(readl(priv->regs + OSTM_CNT));
36}
37
38static int ostm_probe(struct udevice *dev)
39{
40 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
41 struct ostm_priv *priv = dev_get_priv(dev);
42#if CONFIG_IS_ENABLED(CLK)
43 struct clk clk;
44 int ret;
45
46 ret = clk_get_by_index(dev, 0, &clk);
47 if (ret)
48 return ret;
49
50 uc_priv->clock_rate = clk_get_rate(&clk);
51#else
52 uc_priv->clock_rate = get_board_sys_clk() / 2;
53#endif
54
55 readb(priv->regs + OSTM_CTL);
56 writeb(OSTM_CTL_D, priv->regs + OSTM_CTL);
57
58 setbits_8(priv->regs + OSTM_TT, BIT(0));
59 writel(0xffffffff, priv->regs + OSTM_CMP);
60 setbits_8(priv->regs + OSTM_TS, BIT(0));
61
62 return 0;
63}
64
65static int ostm_of_to_plat(struct udevice *dev)
66{
67 struct ostm_priv *priv = dev_get_priv(dev);
68
69 priv->regs = dev_read_addr(dev);
70
71 return 0;
72}
73
74static const struct timer_ops ostm_ops = {
75 .get_count = ostm_get_count,
76};
77
78static const struct udevice_id ostm_ids[] = {
79 { .compatible = "renesas,ostm" },
80 {}
81};
82
83U_BOOT_DRIVER(ostm_timer) = {
84 .name = "ostm-timer",
85 .id = UCLASS_TIMER,
86 .ops = &ostm_ops,
87 .probe = ostm_probe,
88 .of_match = ostm_ids,
89 .of_to_plat = ostm_of_to_plat,
90 .priv_auto = sizeof(struct ostm_priv),
91};