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"Das U-Boot" Source Tree
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek High-speed UART driver
4 *
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
7 */
8
9#include <clk.h>
10#include <config.h>
11#include <div64.h>
12#include <dm.h>
13#include <dm/device.h>
14#include <dm/device_compat.h>
15#include <errno.h>
16#include <log.h>
17#include <serial.h>
18#include <watchdog.h>
19#include <asm/global_data.h>
20#include <asm/io.h>
21#include <asm/types.h>
22#include <linux/err.h>
23#include <linux/printk.h>
24
25struct mtk_serial_regs {
26 u32 rbr;
27 u32 ier;
28 u32 fcr;
29 u32 lcr;
30 u32 mcr;
31 u32 lsr;
32 u32 msr;
33 u32 spr;
34 u32 mdr1;
35 u32 highspeed;
36 u32 sample_count;
37 u32 sample_point;
38 u32 fracdiv_l;
39 u32 fracdiv_m;
40 u32 escape_en;
41 u32 guard;
42 u32 rx_sel;
43};
44
45#define thr rbr
46#define iir fcr
47#define dll rbr
48#define dlm ier
49
50#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
51#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
52
53#define UART_LSR_DR 0x01 /* Data ready */
54#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
55#define UART_LSR_TEMT 0x40 /* Xmitter empty */
56
57#define UART_MCR_DTR 0x01 /* DTR */
58#define UART_MCR_RTS 0x02 /* RTS */
59
60#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
61#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
62#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
63
64#define UART_MCRVAL (UART_MCR_DTR | \
65 UART_MCR_RTS)
66
67/* Clear & enable FIFOs */
68#define UART_FCRVAL (UART_FCR_FIFO_EN | \
69 UART_FCR_RXSR | \
70 UART_FCR_TXSR)
71
72/* the data is correct if the real baud is within 3%. */
73#define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100)
74#define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100)
75
76/* struct mtk_serial_priv - Structure holding all information used by the
77 * driver
78 * @regs: Register base of the serial port
79 * @clk: The baud clock device
80 * @clk_bus: The bus clock device
81 * @fixed_clk_rate: Fallback fixed baud clock rate if baud clock
82 * device is not specified
83 * @force_highspeed: Force using high-speed mode
84 * @upstream_highspeed_logic: Apply upstream high-speed logic
85 */
86struct mtk_serial_priv {
87 struct mtk_serial_regs __iomem *regs;
88 struct clk clk;
89 struct clk clk_bus;
90 u32 fixed_clk_rate;
91 bool force_highspeed;
92 bool upstream_highspeed_logic;
93};
94
95static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud,
96 uint clk_rate)
97{
98 u32 quot, realbaud, samplecount = 1;
99
100 /* Special case for low baud clock */
101 if (baud <= 115200 && clk_rate == 12000000) {
102 writel(3, &priv->regs->highspeed);
103
104 quot = DIV_ROUND_CLOSEST(clk_rate, 256 * baud);
105 if (quot == 0)
106 quot = 1;
107
108 samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud);
109
110 realbaud = clk_rate / samplecount / quot;
111 if (realbaud > BAUD_ALLOW_MAX(baud) ||
112 realbaud < BAUD_ALLOW_MIX(baud)) {
113 pr_info("baud %d can't be handled\n", baud);
114 }
115
116 goto set_baud;
117 }
118
119 /*
120 * Upstream linux use highspeed for anything >= 115200 and lowspeed
121 * for < 115200. Simulate this if we are using the upstream compatible.
122 */
123 if (priv->force_highspeed ||
124 (priv->upstream_highspeed_logic && baud >= 115200))
125 goto use_hs3;
126
127 if (baud <= 115200) {
128 writel(0, &priv->regs->highspeed);
129 quot = DIV_ROUND_CLOSEST(clk_rate, 16 * baud);
130 } else if (baud <= 576000) {
131 writel(2, &priv->regs->highspeed);
132
133 /* Set to next lower baudrate supported */
134 if ((baud == 500000) || (baud == 576000))
135 baud = 460800;
136
137 quot = DIV_ROUND_UP(clk_rate, 4 * baud);
138 } else {
139use_hs3:
140 writel(3, &priv->regs->highspeed);
141
142 quot = DIV_ROUND_UP(clk_rate, 256 * baud);
143 samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud);
144 }
145
146set_baud:
147 /* set divisor */
148 writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr);
149 writel(quot & 0xff, &priv->regs->dll);
150 writel((quot >> 8) & 0xff, &priv->regs->dlm);
151 writel(UART_LCR_WLS_8, &priv->regs->lcr);
152
153 /* set highspeed mode sample count & point */
154 writel(samplecount - 1, &priv->regs->sample_count);
155 writel((samplecount - 2) >> 1, &priv->regs->sample_point);
156}
157
158static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
159{
160 if (!(readl(&priv->regs->lsr) & UART_LSR_THRE))
161 return -EAGAIN;
162
163 writel(ch, &priv->regs->thr);
164
165 if (ch == '\n')
166 schedule();
167
168 return 0;
169}
170
171static int _mtk_serial_getc(struct mtk_serial_priv *priv)
172{
173 if (!(readl(&priv->regs->lsr) & UART_LSR_DR))
174 return -EAGAIN;
175
176 return readl(&priv->regs->rbr);
177}
178
179static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input)
180{
181 if (input)
182 return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0;
183 else
184 return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
185}
186
187#if CONFIG_IS_ENABLED(DM_SERIAL)
188static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
189{
190 struct mtk_serial_priv *priv = dev_get_priv(dev);
191 u32 clk_rate;
192
193 clk_rate = clk_get_rate(&priv->clk);
194 if (IS_ERR_VALUE(clk_rate) || clk_rate == 0)
195 clk_rate = priv->fixed_clk_rate;
196
197 _mtk_serial_setbrg(priv, baudrate, clk_rate);
198
199 return 0;
200}
201
202static int mtk_serial_putc(struct udevice *dev, const char ch)
203{
204 struct mtk_serial_priv *priv = dev_get_priv(dev);
205
206 return _mtk_serial_putc(priv, ch);
207}
208
209static int mtk_serial_getc(struct udevice *dev)
210{
211 struct mtk_serial_priv *priv = dev_get_priv(dev);
212
213 return _mtk_serial_getc(priv);
214}
215
216static int mtk_serial_pending(struct udevice *dev, bool input)
217{
218 struct mtk_serial_priv *priv = dev_get_priv(dev);
219
220 return _mtk_serial_pending(priv, input);
221}
222
223static int mtk_serial_probe(struct udevice *dev)
224{
225 struct mtk_serial_priv *priv = dev_get_priv(dev);
226
227 /* Disable interrupt */
228 writel(0, &priv->regs->ier);
229
230 writel(UART_MCRVAL, &priv->regs->mcr);
231 writel(UART_FCRVAL, &priv->regs->fcr);
232
233 clk_enable(&priv->clk);
234 if (priv->clk_bus.dev)
235 clk_enable(&priv->clk_bus);
236
237 return 0;
238}
239
240static int mtk_serial_of_to_plat(struct udevice *dev)
241{
242 struct mtk_serial_priv *priv = dev_get_priv(dev);
243 fdt_addr_t addr;
244 int err;
245
246 addr = dev_read_addr(dev);
247 if (addr == FDT_ADDR_T_NONE)
248 return -EINVAL;
249
250 priv->regs = map_physmem(addr, 0, MAP_NOCACHE);
251
252 err = clk_get_by_index(dev, 0, &priv->clk);
253 if (err) {
254 err = dev_read_u32(dev, "clock-frequency", &priv->fixed_clk_rate);
255 if (err) {
256 dev_err(dev, "baud clock not defined\n");
257 return -EINVAL;
258 }
259 } else {
260 err = clk_get_rate(&priv->clk);
261 if (IS_ERR_VALUE(err)) {
262 dev_err(dev, "invalid baud clock\n");
263 return -EINVAL;
264 }
265 }
266
267 clk_get_by_name(dev, "bus", &priv->clk_bus);
268
269 priv->force_highspeed = dev_read_bool(dev, "mediatek,force-highspeed");
270 priv->upstream_highspeed_logic =
271 device_is_compatible(dev, "mediatek,mt6577-uart");
272
273 return 0;
274}
275
276static const struct dm_serial_ops mtk_serial_ops = {
277 .putc = mtk_serial_putc,
278 .pending = mtk_serial_pending,
279 .getc = mtk_serial_getc,
280 .setbrg = mtk_serial_setbrg,
281};
282
283static const struct udevice_id mtk_serial_ids[] = {
284 { .compatible = "mediatek,hsuart" },
285 { .compatible = "mediatek,mt6577-uart" },
286 { }
287};
288
289U_BOOT_DRIVER(serial_mtk) = {
290 .name = "serial_mtk",
291 .id = UCLASS_SERIAL,
292 .of_match = mtk_serial_ids,
293 .of_to_plat = mtk_serial_of_to_plat,
294 .priv_auto = sizeof(struct mtk_serial_priv),
295 .probe = mtk_serial_probe,
296 .ops = &mtk_serial_ops,
297 .flags = DM_FLAG_PRE_RELOC,
298};
299#else
300
301DECLARE_GLOBAL_DATA_PTR;
302
303#define DECLARE_HSUART_PRIV(port) \
304 static struct mtk_serial_priv mtk_hsuart##port = { \
305 .regs = (struct mtk_serial_regs *)CFG_SYS_NS16550_COM##port, \
306 .fixed_clk_rate = CFG_SYS_NS16550_CLK \
307};
308
309#define DECLARE_HSUART_FUNCTIONS(port) \
310 static int mtk_serial##port##_init(void) \
311 { \
312 writel(0, &mtk_hsuart##port.regs->ier); \
313 writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \
314 writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \
315 _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate, \
316 mtk_hsuart##port.fixed_clk_rate); \
317 return 0 ; \
318 } \
319 static void mtk_serial##port##_setbrg(void) \
320 { \
321 _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate, \
322 mtk_hsuart##port.fixed_clk_rate); \
323 } \
324 static int mtk_serial##port##_getc(void) \
325 { \
326 int err; \
327 do { \
328 err = _mtk_serial_getc(&mtk_hsuart##port); \
329 if (err == -EAGAIN) \
330 schedule(); \
331 } while (err == -EAGAIN); \
332 return err >= 0 ? err : 0; \
333 } \
334 static int mtk_serial##port##_tstc(void) \
335 { \
336 return _mtk_serial_pending(&mtk_hsuart##port, true); \
337 } \
338 static void mtk_serial##port##_putc(const char c) \
339 { \
340 int err; \
341 if (c == '\n') \
342 mtk_serial##port##_putc('\r'); \
343 do { \
344 err = _mtk_serial_putc(&mtk_hsuart##port, c); \
345 } while (err == -EAGAIN); \
346 } \
347 static void mtk_serial##port##_puts(const char *s) \
348 { \
349 while (*s) { \
350 mtk_serial##port##_putc(*s++); \
351 } \
352 }
353
354/* Serial device descriptor */
355#define INIT_HSUART_STRUCTURE(port, __name) { \
356 .name = __name, \
357 .start = mtk_serial##port##_init, \
358 .stop = NULL, \
359 .setbrg = mtk_serial##port##_setbrg, \
360 .getc = mtk_serial##port##_getc, \
361 .tstc = mtk_serial##port##_tstc, \
362 .putc = mtk_serial##port##_putc, \
363 .puts = mtk_serial##port##_puts, \
364}
365
366#define DECLARE_HSUART(port, __name) \
367 DECLARE_HSUART_PRIV(port); \
368 DECLARE_HSUART_FUNCTIONS(port); \
369 struct serial_device mtk_hsuart##port##_device = \
370 INIT_HSUART_STRUCTURE(port, __name);
371
372#if !defined(CONFIG_CONS_INDEX)
373#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6)
374#error "Invalid console index value."
375#endif
376
377#if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1)
378#error "Console port 1 defined but not configured."
379#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2)
380#error "Console port 2 defined but not configured."
381#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3)
382#error "Console port 3 defined but not configured."
383#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4)
384#error "Console port 4 defined but not configured."
385#elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5)
386#error "Console port 5 defined but not configured."
387#elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6)
388#error "Console port 6 defined but not configured."
389#endif
390
391#if defined(CFG_SYS_NS16550_COM1)
392DECLARE_HSUART(1, "mtk-hsuart0");
393#endif
394#if defined(CFG_SYS_NS16550_COM2)
395DECLARE_HSUART(2, "mtk-hsuart1");
396#endif
397#if defined(CFG_SYS_NS16550_COM3)
398DECLARE_HSUART(3, "mtk-hsuart2");
399#endif
400#if defined(CFG_SYS_NS16550_COM4)
401DECLARE_HSUART(4, "mtk-hsuart3");
402#endif
403#if defined(CFG_SYS_NS16550_COM5)
404DECLARE_HSUART(5, "mtk-hsuart4");
405#endif
406#if defined(CFG_SYS_NS16550_COM6)
407DECLARE_HSUART(6, "mtk-hsuart5");
408#endif
409
410__weak struct serial_device *default_serial_console(void)
411{
412#if CONFIG_CONS_INDEX == 1
413 return &mtk_hsuart1_device;
414#elif CONFIG_CONS_INDEX == 2
415 return &mtk_hsuart2_device;
416#elif CONFIG_CONS_INDEX == 3
417 return &mtk_hsuart3_device;
418#elif CONFIG_CONS_INDEX == 4
419 return &mtk_hsuart4_device;
420#elif CONFIG_CONS_INDEX == 5
421 return &mtk_hsuart5_device;
422#elif CONFIG_CONS_INDEX == 6
423 return &mtk_hsuart6_device;
424#else
425#error "Bad CONFIG_CONS_INDEX."
426#endif
427}
428
429void mtk_serial_initialize(void)
430{
431#if defined(CFG_SYS_NS16550_COM1)
432 serial_register(&mtk_hsuart1_device);
433#endif
434#if defined(CFG_SYS_NS16550_COM2)
435 serial_register(&mtk_hsuart2_device);
436#endif
437#if defined(CFG_SYS_NS16550_COM3)
438 serial_register(&mtk_hsuart3_device);
439#endif
440#if defined(CFG_SYS_NS16550_COM4)
441 serial_register(&mtk_hsuart4_device);
442#endif
443#if defined(CFG_SYS_NS16550_COM5)
444 serial_register(&mtk_hsuart5_device);
445#endif
446#if defined(CFG_SYS_NS16550_COM6)
447 serial_register(&mtk_hsuart6_device);
448#endif
449}
450
451#endif
452
453#ifdef CONFIG_DEBUG_UART_MTK
454
455#include <debug_uart.h>
456
457static inline void _debug_uart_init(void)
458{
459 struct mtk_serial_priv priv;
460
461 memset(&priv, 0, sizeof(struct mtk_serial_priv));
462 priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
463 priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK;
464
465 writel(0, &priv.regs->ier);
466 writel(UART_MCRVAL, &priv.regs->mcr);
467 writel(UART_FCRVAL, &priv.regs->fcr);
468
469 _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE, priv.fixed_clk_rate);
470}
471
472static inline void _debug_uart_putc(int ch)
473{
474 struct mtk_serial_regs __iomem *regs =
475 (void *) CONFIG_VAL(DEBUG_UART_BASE);
476
477 while (!(readl(®s->lsr) & UART_LSR_THRE))
478 ;
479
480 writel(ch, ®s->thr);
481}
482
483DEBUG_UART_FUNCS
484
485#endif