jcs.org
"Das U-Boot" Source Tree
1#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
7config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
16config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
19 default MISC
20 help
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
24 access the device.
25
26config TPL_MISC
27 bool "Enable Driver Model for Misc drivers in TPL"
28 depends on TPL_DM
29 default MISC
30 help
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
34 access the device.
35
36config VPL_MISC
37 bool "Enable Driver Model for Misc drivers in VPL"
38 depends on VPL_DM
39 default MISC
40 help
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
44 access the device.
45
46config NVMEM
47 bool "NVMEM support"
48 help
49 This adds support for a common interface to different types of
50 non-volatile memory. Consumers can use nvmem-cells properties to look
51 up hardware configuration data such as MAC addresses and calibration
52 settings.
53
54config SPL_NVMEM
55 bool "NVMEM support in SPL"
56 help
57 This adds support for a common interface to different types of
58 non-volatile memory. Consumers can use nvmem-cells properties to look
59 up hardware configuration data such as MAC addresses and calibration
60 settings.
61
62config ALTERA_SYSID
63 bool "Altera Sysid support"
64 depends on MISC
65 help
66 Select this to enable a sysid for Altera devices. Please find
67 details on the "Embedded Peripherals IP User Guide" of Altera.
68
69config ATSHA204A
70 bool "Support for Atmel ATSHA204A module"
71 select BITREVERSE
72 depends on MISC
73 help
74 Enable support for I2C connected Atmel's ATSHA204A
75 CryptoAuthentication module found for example on the Turris Omnia
76 board.
77
78config GATEWORKS_SC
79 bool "Gateworks System Controller Support"
80 depends on MISC
81 help
82 Enable access for the Gateworks System Controller used on Gateworks
83 boards to provide a boot watchdog, power control, temperature monitor,
84 voltage ADCs, and EEPROM.
85
86config ROCKCHIP_EFUSE
87 bool "Rockchip e-fuse support"
88 depends on MISC
89 help
90 Enable (read-only) access for the e-fuse block found in Rockchip
91 SoCs: accesses can either be made using byte addressing and a length
92 or through child-nodes that are generated based on the e-fuse map
93 retrieved from the DTS.
94
95config ROCKCHIP_OTP
96 bool "Rockchip OTP Support"
97 depends on MISC
98 help
99 Enable (read-only) access for the one-time-programmable memory block
100 found in Rockchip SoCs: accesses can either be made using byte
101 addressing and a length or through child-nodes that are generated
102 based on the e-fuse map retrieved from the DTS.
103
104config ROCKCHIP_IODOMAIN
105 bool "Rockchip IO-domain driver support"
106 depends on DM_REGULATOR && ARCH_ROCKCHIP
107 default y if ROCKCHIP_RK3328 || ROCKCHIP_RK3568
108 help
109 Enable support for IO-domains in Rockchip SoCs. It is necessary
110 for the IO-domain setting of the SoC to match the voltage supplied
111 by the regulators.
112
113config SIFIVE_OTP
114 bool "SiFive eMemory OTP driver"
115 depends on MISC
116 help
117 Enable support for reading and writing the eMemory OTP on the
118 SiFive SoCs.
119
120config SMSC_LPC47M
121 bool "LPC47M SMSC driver"
122
123config SMSC_SIO1007
124 bool "SIO1007 SMSC driver"
125
126config VEXPRESS_CONFIG
127 bool "Enable support for Arm Versatile Express config bus"
128 depends on MISC
129 help
130 If you say Y here, you will get support for accessing the
131 configuration bus on the Arm Versatile Express boards via
132 a sysreg driver.
133
134config CBMEM_CONSOLE
135 bool "Write console output to coreboot cbmem"
136 depends on X86
137 help
138 Enables console output to the cbmem console, which is a memory
139 region set up by coreboot to hold a record of all console output.
140 Enable this only if booting from coreboot.
141
142config CMD_CROS_EC
143 bool "Enable crosec command"
144 depends on CROS_EC
145 help
146 Enable command-line access to the Chrome OS EC (Embedded
147 Controller). This provides the 'crosec' command which has
148 a number of sub-commands for performing EC tasks such as
149 updating its flash, accessing a small saved context area
150 and talking to the I2C bus behind the EC (if there is one).
151
152config CROS_EC
153 bool "Enable Chrome OS EC"
154 help
155 Enable access to the Chrome OS EC. This is a separate
156 microcontroller typically available on a SPI bus on Chromebooks. It
157 provides access to the keyboard, some internal storage and may
158 control access to the battery and main PMIC depending on the
159 device. You can use the 'crosec' command to access it.
160
161config SPL_CROS_EC
162 bool "Enable Chrome OS EC in SPL"
163 depends on SPL_MISC
164 help
165 Enable access to the Chrome OS EC in SPL. This is a separate
166 microcontroller typically available on a SPI bus on Chromebooks. It
167 provides access to the keyboard, some internal storage and may
168 control access to the battery and main PMIC depending on the
169 device. You can use the 'crosec' command to access it.
170
171config TPL_CROS_EC
172 bool "Enable Chrome OS EC in TPL"
173 depends on TPL_MISC
174 help
175 Enable access to the Chrome OS EC in TPL. This is a separate
176 microcontroller typically available on a SPI bus on Chromebooks. It
177 provides access to the keyboard, some internal storage and may
178 control access to the battery and main PMIC depending on the
179 device. You can use the 'crosec' command to access it.
180
181config VPL_CROS_EC
182 bool "Enable Chrome OS EC in VPL"
183 depends on VPL_MISC
184 help
185 Enable access to the Chrome OS EC in VPL. This is a separate
186 microcontroller typically available on a SPI bus on Chromebooks. It
187 provides access to the keyboard, some internal storage and may
188 control access to the battery and main PMIC depending on the
189 device. You can use the 'crosec' command to access it.
190
191config CROS_EC_I2C
192 bool "Enable Chrome OS EC I2C driver"
193 depends on CROS_EC
194 help
195 Enable I2C access to the Chrome OS EC. This is used on older
196 ARM Chromebooks such as snow and spring before the standard bus
197 changed to SPI. The EC will accept commands across the I2C using
198 a special message protocol, and provide responses.
199
200config CROS_EC_LPC
201 bool "Enable Chrome OS EC LPC driver"
202 depends on CROS_EC
203 help
204 Enable I2C access to the Chrome OS EC. This is used on x86
205 Chromebooks such as link and falco. The keyboard is provided
206 through a legacy port interface, so on x86 machines the main
207 function of the EC is power and thermal management.
208
209config SPL_CROS_EC_LPC
210 bool "Enable Chrome OS EC LPC driver in SPL"
211 depends on CROS_EC && SPL_MISC
212 help
213 Enable I2C access to the Chrome OS EC. This is used on x86
214 Chromebooks such as link and falco. The keyboard is provided
215 through a legacy port interface, so on x86 machines the main
216 function of the EC is power and thermal management.
217
218config TPL_CROS_EC_LPC
219 bool "Enable Chrome OS EC LPC driver in TPL"
220 depends on CROS_EC && TPL_MISC
221 help
222 Enable I2C access to the Chrome OS EC. This is used on x86
223 Chromebooks such as link and falco. The keyboard is provided
224 through a legacy port interface, so on x86 machines the main
225 function of the EC is power and thermal management.
226
227config VPL_CROS_EC_LPC
228 bool "Enable Chrome OS EC LPC driver in VPL"
229 depends on CROS_EC && VPL_MISC
230 help
231 Enable I2C access to the Chrome OS EC. This is used on x86
232 Chromebooks such as link and falco. The keyboard is provided
233 through a legacy port interface, so on x86 machines the main
234 function of the EC is power and thermal management.
235
236config CROS_EC_SANDBOX
237 bool "Enable Chrome OS EC sandbox driver"
238 depends on CROS_EC && SANDBOX
239 help
240 Enable a sandbox emulation of the Chrome OS EC. This supports
241 keyboard (use the -l flag to enable the LCD), verified boot context,
242 EC flash read/write/erase support and a few other things. It is
243 enough to perform a Chrome OS verified boot on sandbox.
244
245config SPL_CROS_EC_SANDBOX
246 bool "Enable Chrome OS EC sandbox driver in SPL"
247 depends on SPL_CROS_EC && SANDBOX
248 help
249 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
250 keyboard (use the -l flag to enable the LCD), verified boot context,
251 EC flash read/write/erase support and a few other things. It is
252 enough to perform a Chrome OS verified boot on sandbox.
253
254config TPL_CROS_EC_SANDBOX
255 bool "Enable Chrome OS EC sandbox driver in TPL"
256 depends on TPL_CROS_EC && SANDBOX
257 help
258 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
259 keyboard (use the -l flag to enable the LCD), verified boot context,
260 EC flash read/write/erase support and a few other things. It is
261 enough to perform a Chrome OS verified boot on sandbox.
262
263config VPL_CROS_EC_SANDBOX
264 bool "Enable Chrome OS EC sandbox driver in VPL"
265 depends on VPL_CROS_EC && SANDBOX
266 help
267 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
268 keyboard (use the -l flag to enable the LCD), verified boot context,
269 EC flash read/write/erase support and a few other things. It is
270 enough to perform a Chrome OS verified boot on sandbox.
271
272config CROS_EC_SPI
273 bool "Enable Chrome OS EC SPI driver"
274 depends on CROS_EC
275 help
276 Enable SPI access to the Chrome OS EC. This is used on newer
277 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
278 provides a faster and more robust interface than I2C but the bugs
279 are less interesting.
280
281config DS4510
282 bool "Enable support for DS4510 CPU supervisor"
283 help
284 Enable support for the Maxim DS4510 CPU supervisor. It has an
285 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
286 and a configurable timer for the supervisor function. The device is
287 connected over I2C.
288
289config FSL_IIM
290 bool "Enable FSL IC Identification Module (IIM) driver"
291 depends on ARCH_MX31 || ARCH_MX5
292
293config FSL_SEC_MON
294 bool "Enable FSL SEC_MON Driver"
295 help
296 Freescale Security Monitor block is responsible for monitoring
297 system states.
298 Security Monitor can be transitioned on any security failures,
299 like software violations or hardware security violations.
300
301choice
302 prompt "Security monitor interaction endianess"
303 depends on FSL_SEC_MON
304 default SYS_FSL_SEC_MON_BE if PPC
305 default SYS_FSL_SEC_MON_LE
306
307config SYS_FSL_SEC_MON_LE
308 bool "Security monitor interactions are little endian"
309
310config SYS_FSL_SEC_MON_BE
311 bool "Security monitor interactions are big endian"
312
313endchoice
314
315config IRQ
316 bool "Interrupt controller"
317 help
318 This enables support for interrupt controllers, including ITSS.
319 Some devices have extra features, such as Apollo Lake. The
320 device has its own uclass since there are several operations
321 involved.
322
323config JZ4780_EFUSE
324 bool "Ingenic JZ4780 eFUSE support"
325 depends on ARCH_JZ47XX
326 help
327 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
328
329config LS2_SFP
330 bool "Layerscape Security Fuse Processor"
331 depends on FSL_LSCH2 || ARCH_LS1021A
332 depends on MISC
333 imply DM_REGULATOR
334 help
335 This adds support for the Security Fuse Processor found on Layerscape
336 SoCs. It contains various fuses related to secure boot, including the
337 Super Root Key hash, One-Time-Programmable Master Key, Debug
338 Challenge/Response values, and others. Fuses are numbered according
339 to their four-byte offset from the start of the bank.
340
341 If you don't need to read/program fuses, say 'n'.
342
343config MXC_OCOTP
344 bool "Enable MXC OCOTP Driver"
345 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
346 default y
347 help
348 If you say Y here, you will get support for the One Time
349 Programmable memory pages that are stored on the some
350 Freescale i.MX processors.
351
352config MXS_OCOTP
353 bool "Enable MXS OCOTP Driver"
354 depends on ARCH_MX23 || ARCH_MX28
355 help
356 If you say Y here, you will get support for the One Time
357 Programmable memory pages that are stored on the
358 Freescale i.MXS family of processors.
359
360config NPCM_HOST
361 bool "Enable support espi or LPC for Host"
362 depends on REGMAP && SYSCON
363 help
364 Enable NPCM BMC espi or LPC support for Host reading and writing.
365
366config SPL_MXC_OCOTP
367 bool "Enable MXC OCOTP driver in SPL"
368 depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
369 default y
370 help
371 If you say Y here, you will get support for the One Time
372 Programmable memory pages, that are stored on some
373 Freescale i.MX processors, in SPL.
374
375config NPCM_OTP
376 bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
377 depends on (ARM && ARCH_NPCM)
378 help
379 Support NPCM BMC OTP memory (fuse).
380 To compile this driver as a module, choose M here: the module
381 will be called npcm_otp.
382
383config IMX_ELE
384 bool "Enable i.MX EdgeLock Enclave MU driver and API"
385 depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
386 help
387 If you say Y here to enable Message Unit driver to work with
388 Sentinel core on some NXP i.MX processors.
389
390config NUVOTON_NCT6102D
391 bool "Enable Nuvoton NCT6102D Super I/O driver"
392 help
393 If you say Y here, you will get support for the Nuvoton
394 NCT6102D Super I/O driver. This can be used to enable or
395 disable the legacy UART, the watchdog or other devices
396 in the Nuvoton Super IO chips on X86 platforms.
397
398config P2SB
399 bool "Intel Primary to Sideband Bridge"
400 depends on X86 || SANDBOX
401 help
402 This enables support for the Intel Primary to Sideband Bridge,
403 abbreviated to P2SB. The P2SB is used to access various peripherals
404 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
405 space. The space is segmented into different channels and peripherals
406 are accessed by device-specific means within those channels. Devices
407 should be added in the device tree as subnodes of the P2SB. A
408 Peripheral Channel Register? (PCR) API is provided to access those
409 devices - see pcr_readl(), etc.
410
411config SPL_P2SB
412 bool "Intel Primary to Sideband Bridge in SPL"
413 depends on SPL_MISC && (X86 || SANDBOX)
414 help
415 The Primary to Sideband Bridge is used to access various peripherals
416 through memory-mapped I/O in a large chunk of PCI space. The space is
417 segmented into different channels and peripherals are accessed by
418 device-specific means within those channels. Devices should be added
419 in the device tree as subnodes of the p2sb.
420
421config TPL_P2SB
422 bool "Intel Primary to Sideband Bridge in TPL"
423 depends on TPL_MISC && (X86 || SANDBOX)
424 help
425 The Primary to Sideband Bridge is used to access various peripherals
426 through memory-mapped I/O in a large chunk of PCI space. The space is
427 segmented into different channels and peripherals are accessed by
428 device-specific means within those channels. Devices should be added
429 in the device tree as subnodes of the p2sb.
430
431config PWRSEQ
432 bool "Enable power-sequencing drivers"
433 depends on DM
434 help
435 Power-sequencing drivers provide support for controlling power for
436 devices. They are typically referenced by a phandle from another
437 device. When the device is started up, its power sequence can be
438 initiated.
439
440config SPL_PWRSEQ
441 bool "Enable power-sequencing drivers for SPL"
442 depends on SPL_MISC && PWRSEQ
443 help
444 Power-sequencing drivers provide support for controlling power for
445 devices. They are typically referenced by a phandle from another
446 device. When the device is started up, its power sequence can be
447 initiated.
448
449config PCA9551_LED
450 bool "Enable PCA9551 LED driver"
451 help
452 Enable driver for PCA9551 LED controller. This controller
453 is connected via I2C. So I2C needs to be enabled.
454
455config PCA9551_I2C_ADDR
456 hex "I2C address of PCA9551 LED controller"
457 depends on PCA9551_LED
458 default 0x60
459 help
460 The I2C address of the PCA9551 LED controller.
461
462config STM32MP_FUSE
463 bool "Enable STM32MP fuse wrapper providing the fuse API"
464 depends on ARCH_STM32MP && MISC
465 default y if CMD_FUSE
466 help
467 If you say Y here, you will get support for the fuse API (OTP)
468 for STM32MP architecture.
469 This API is needed for CMD_FUSE.
470
471config STM32_RCC
472 bool "Enable RCC driver for the STM32 SoC's family"
473 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
474 help
475 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
476 block) is responsible of the management of the clock and reset
477 generation.
478 This driver is similar to an MFD driver in the Linux kernel.
479
480config TEGRA_CAR
481 bool "Enable support for the Tegra CAR driver"
482 depends on TEGRA_NO_BPMP
483 help
484 The Tegra CAR (Clock and Reset Controller) is a HW module that
485 controls almost all clocks and resets in a Tegra SoC.
486
487config TEGRA186_BPMP
488 bool "Enable support for the Tegra186 BPMP driver"
489 depends on TEGRA186
490 help
491 The Tegra BPMP (Boot and Power Management Processor) is a separate
492 auxiliary CPU embedded into Tegra to perform power management work,
493 and controls related features such as clocks, resets, power domains,
494 PMIC I2C bus, etc. This driver provides the core low-level
495 communication path by which feature-specific drivers (such as clock)
496 can make requests to the BPMP. This driver is similar to an MFD
497 driver in the Linux kernel.
498
499config TEST_DRV
500 bool "Enable support for test drivers"
501 default y if SANDBOX
502 help
503 This enables drivers and uclasses that provides a way of testing the
504 operations of memory allocation and driver/uclass methods in driver
505 model. This should only be enabled for testing as it is not useful for
506 anything else.
507
508config TURRIS_OMNIA_MCU
509 bool "Enable Turris Omnia MCU driver"
510 depends on DM_I2C
511 depends on DM_GPIO
512 depends on DM_RNG
513 depends on SYSRESET
514 default y if TARGET_TURRIS_OMNIA
515 help
516 This enables support for Turris Omnia MCU connected GPIOs and
517 board power off.
518
519config USB_HUB_USB251XB
520 tristate "USB251XB Hub Controller Configuration Driver"
521 depends on I2C
522 help
523 This option enables support for configuration via SMBus of the
524 Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
525 parameters may be set in devicetree or platform data.
526 Say Y or M here if you need to configure such a device via SMBus.
527
528config TWL4030_LED
529 bool "Enable TWL4030 LED controller"
530 help
531 Enable this to add support for the TWL4030 LED controller.
532
533config WINBOND_W83627
534 bool "Enable Winbond Super I/O driver"
535 help
536 If you say Y here, you will get support for the Winbond
537 W83627 Super I/O driver. This can be used to enable the
538 legacy UART or other devices in the Winbond Super IO chips
539 on X86 platforms.
540
541config QFW
542 bool
543 help
544 Hidden option to enable QEMU fw_cfg interface and uclass. This will
545 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
546
547config QFW_ACPI
548 bool
549 default y
550 depends on QFW && GENERATE_ACPI_TABLE && !SANDBOX
551 help
552 Hidden option to read ACPI tables from QEMU.
553
554config QFW_PIO
555 bool
556 depends on QFW
557 help
558 Hidden option to enable PIO QEMU fw_cfg interface. This will be
559 selected by the appropriate QEMU board.
560
561config QFW_MMIO
562 bool
563 depends on QFW
564 help
565 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
566 selected by the appropriate QEMU board.
567
568config QFW_SMBIOS
569 bool
570 default y
571 depends on QFW && SMBIOS && !SANDBOX && !SYSINFO_SMBIOS
572 help
573 Hidden option to read SMBIOS tables from QEMU.
574
575config I2C_EEPROM
576 bool "Enable driver for generic I2C-attached EEPROMs"
577 depends on MISC
578 help
579 Enable a generic driver for EEPROMs attached via I2C.
580
581
582config SPL_I2C_EEPROM
583 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
584 depends on SPL_MISC
585 help
586 This option is an SPL-variant of the I2C_EEPROM option.
587 See the help of I2C_EEPROM for details.
588
589config SYS_I2C_EEPROM_ADDR
590 hex "Chip address of the EEPROM device"
591 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
592 default 0x0
593
594if I2C_EEPROM
595
596config SYS_I2C_EEPROM_ADDR_OVERFLOW
597 hex "EEPROM Address Overflow"
598 default 0x0
599 help
600 EEPROM chips that implement "address overflow" are ones
601 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
602 address and the extra bits end up in the "chip address" bit
603 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
604 byte chips.
605
606endif
607
608config GDSYS_RXAUI_CTRL
609 bool "Enable gdsys RXAUI control driver"
610 depends on MISC
611 help
612 Support gdsys FPGA's RXAUI control.
613
614config GDSYS_IOEP
615 bool "Enable gdsys IOEP driver"
616 depends on MISC
617 help
618 Support gdsys FPGA's IO endpoint driver.
619
620config MPC83XX_SERDES
621 bool "Enable MPC83xx serdes driver"
622 depends on MISC
623 help
624 Support for serdes found on MPC83xx SoCs.
625
626config FS_LOADER
627 bool "Enable loader driver for file system"
628 help
629 This is file system generic loader which can be used to load
630 the file image from the storage into target such as memory.
631
632 The consumer driver would then use this loader to program whatever,
633 ie. the FPGA device.
634
635config SPL_FS_LOADER
636 bool "Enable loader driver for file system in SPL"
637 depends on SPL
638 help
639 This is file system generic loader which can be used to load
640 the file image from the storage into target such as memory.
641
642 The consumer driver would then use this loader to program whatever,
643 ie. the FPGA device.
644
645config GDSYS_SOC
646 bool "Enable gdsys SOC driver"
647 depends on MISC
648 help
649 Support for gdsys IHS SOC, a simple bus associated with each gdsys
650 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
651 register maps are contained within the FPGA's register map.
652
653config IHS_FPGA
654 bool "Enable IHS FPGA driver"
655 depends on MISC
656 help
657 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
658 gdsys devices, which supply the majority of the functionality offered
659 by the devices. This driver supports both CON and CPU variants of the
660 devices, depending on the device tree entry.
661config ESM_K3
662 bool "Enable K3 ESM driver"
663 depends on ARCH_K3
664 help
665 Support ESM (Error Signaling Module) on TI K3 SoCs.
666
667config MICROCHIP_FLEXCOM
668 bool "Enable Microchip Flexcom driver"
669 depends on MISC
670 help
671 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
672 an I2C controller and an USART.
673 Only one function can be used at a time and is chosen at boot time
674 according to the device tree.
675
676config K3_AVS0
677 depends on ARCH_K3 && SPL_DM_REGULATOR
678 bool "AVS class 0 support for K3 devices"
679 help
680 K3 devices have the optimized voltage values for the main voltage
681 domains stored in efuse within the VTM IP. This driver reads the
682 optimized voltage from the efuse, so that it can be programmed
683 to the PMIC on board.
684
685config ESM_PMIC
686 bool "Enable PMIC ESM driver"
687 depends on DM_PMIC
688 help
689 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
690 typically to reboot the board in error condition.
691
692config FSL_IFC
693 bool
694
695config SL28CPLD
696 bool "Enable Kontron sl28cpld multi-function driver"
697 depends on DM_I2C
698 help
699 Support for the Kontron sl28cpld management controller. This is
700 the base driver which provides common access methods for the
701 sub-drivers.
702
703config SPL_SOCFPGA_DT_REG
704 bool "Enable register setting from device tree in SPL"
705 depends on SPL
706 help
707 Enable register setting from device tree. This also
708 provides user a clean interface and all register settings are
709 centralized in one place, device tree.
710endmenu