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"Das U-Boot" Source Tree
1.. SPDX-License-Identifier: GPL-2.0+
2.. Copyright 2024 NXP
3
4.. index::
5 single: cpu (command)
6
7cpu command
8===========
9
10Synopsis
11--------
12
13::
14
15 cpu list
16 cpu detail
17 cpu release <core ID> <addr>
18
19Description
20-----------
21
22The *cpu* command prints information about the CPUs, and release a CPU core
23to a given address to run applications.
24
25
26cpu list
27~~~~~~~~
28
29The 'list' subcommand lists and prints brief information of all the CPU cores,
30the CPU information is provided by vendors' CPU driver.
31
32cpu detail
33~~~~~~~~~~
34
35The 'detail' subcommand prints more details about the CPU cores, including
36CPU ID, core frequency and feature list.
37
38cpu release
39~~~~~~~~~~~
40
41The 'release' subcommand is used to release a CPU core to run a baremetal or
42RTOS applications.
43The parameter <core ID> is the sequence number of the CPU core to release.
44The parameter <addr> is the address to run of the specified core after release.
45
46
47Examples
48--------
49
50cpu list
51~~~~~~~~
52
53This example lists all the CPU cores On i.MX8M Plus EVK:
54::
55
56 u-boot=> cpu list
57 0: cpu@0 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
58 1: cpu@1 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30C
59 2: cpu@2 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
60 3: cpu@3 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
61
62cpu detail
63~~~~~~~~~~
64
65This example prints the details of the CPU cores On i.MX8M Plus EVK:
66::
67
68 u-boot=> cpu detail
69 0: cpu@0 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
70 ID = 0, freq = 1.2 GHz: L1 cache, MMU
71 1: cpu@1 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30C
72 ID = 0, freq = 1.2 GHz: L1 cache, MMU
73 2: cpu@2 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
74 ID = 0, freq = 1.2 GHz: L1 cache, MMU
75 3: cpu@3 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
76 ID = 0, freq = 1.2 GHz: L1 cache, MMU
77
78cpu release
79~~~~~~~~~~~
80
81This example shows release the LAST CPU core to run a RTOS application, on
82i.MX8M Plus EVK:
83::
84
85 u-boot=> load mmc 1:2 c0000000 /hello_world.bin
86 66008 bytes read in 5 ms (12.6 MiB/s)
87 u-boot=> dcache flush; icache flush
88 u-boot=> cpu release 3 c0000000
89 Released CPU core (mpidr: 0x3) to address 0xc0000000
90
91
92Configuration
93-------------
94
95The cpu command is available if CONFIG_CMD_CPU=y.
96
97Return code
98-----------
99
100The return value $? is set to 0 (true) if the command is successful,
1011 (false) otherwise.