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"Das U-Boot" Source Tree
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 */
5
6#ifndef __MICROBLAZE_CACHE_H__
7#define __MICROBLAZE_CACHE_H__
8
9/*
10 * The microblaze can have either a 4 or 16 byte cacheline depending on whether
11 * you are using OPB(4) or CacheLink(16). If the board config has not specified
12 * a cacheline size we assume the larger value of 16 bytes for DMA buffer
13 * alignment.
14 */
15#ifdef CONFIG_SYS_CACHELINE_SIZE
16#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
17#else
18#define ARCH_DMA_MINALIGN 16
19#endif
20
21/**
22 * flush_cache_all - flush the entire instruction/data caches
23 */
24void flush_cache_all(void);
25
26#endif /* __MICROBLAZE_CACHE_H__ */