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"Das U-Boot" Source Tree
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU208
4 *
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@amd.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17#include <dt-bindings/phy/phy.h>
18
19/ {
20 model = "ZynqMP ZCU208 RevA";
21 compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp";
22
23 aliases {
24 ethernet0 = &gem3;
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci1;
28 nvmem0 = &eeprom;
29 rtc0 = &rtc;
30 serial0 = &uart0;
31 serial1 = &dcc;
32 spi0 = &qspi;
33 usb0 = &usb0;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
39 };
40
41 memory@0 {
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44 };
45
46 gpio-keys {
47 compatible = "gpio-keys";
48 autorepeat;
49 switch-19 {
50 label = "sw19";
51 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
52 linux,code = <KEY_DOWN>;
53 wakeup-source;
54 autorepeat;
55 };
56 };
57
58 leds {
59 compatible = "gpio-leds";
60 heartbeat-led {
61 label = "heartbeat";
62 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "heartbeat";
64 };
65 };
66
67 ina226-vccint {
68 compatible = "iio-hwmon";
69 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
70 };
71 ina226-vccint-io-bram {
72 compatible = "iio-hwmon";
73 io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
74 };
75 ina226-vcc1v8 {
76 compatible = "iio-hwmon";
77 io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
78 };
79 ina226-vcc1v2 {
80 compatible = "iio-hwmon";
81 io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
82 };
83 ina226-vadj-fmc {
84 compatible = "iio-hwmon";
85 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
86 };
87 ina226-mgtavcc {
88 compatible = "iio-hwmon";
89 io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
90 };
91 ina226-mgt1v2 {
92 compatible = "iio-hwmon";
93 io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
94 };
95 ina226-mgt1v8 {
96 compatible = "iio-hwmon";
97 io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
98 };
99 ina226-vccint-ams {
100 compatible = "iio-hwmon";
101 io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
102 };
103 ina226-dac-avtt {
104 compatible = "iio-hwmon";
105 io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
106 };
107 ina226-dac-avccaux {
108 compatible = "iio-hwmon";
109 io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
110 };
111 ina226-adc-avcc {
112 compatible = "iio-hwmon";
113 io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
114 };
115 ina226-adc-avccaux {
116 compatible = "iio-hwmon";
117 io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
118 };
119 ina226-dac-avcc {
120 compatible = "iio-hwmon";
121 io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
122 };
123
124 /* 48MHz reference crystal */
125 ref48: ref48M {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <48000000>;
129 };
130};
131
132&dcc {
133 status = "okay";
134};
135
136&fpd_dma_chan1 {
137 status = "okay";
138};
139
140&fpd_dma_chan2 {
141 status = "okay";
142};
143
144&fpd_dma_chan3 {
145 status = "okay";
146};
147
148&fpd_dma_chan4 {
149 status = "okay";
150};
151
152&fpd_dma_chan5 {
153 status = "okay";
154};
155
156&fpd_dma_chan6 {
157 status = "okay";
158};
159
160&fpd_dma_chan7 {
161 status = "okay";
162};
163
164&fpd_dma_chan8 {
165 status = "okay";
166};
167
168&gem3 {
169 status = "okay";
170 phy-handle = <&phy0>;
171 phy-mode = "rgmii-id";
172 mdio: mdio {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 phy0: ethernet-phy@c {
176 #phy-cells = <1>;
177 compatible = "ethernet-phy-id2000.a231";
178 reg = <0xc>;
179 ti,rx-internal-delay = <0x8>;
180 ti,tx-internal-delay = <0xa>;
181 ti,fifo-depth = <0x1>;
182 ti,dp83867-rxctrl-strap-quirk;
183 reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>;
184 };
185 };
186};
187
188&gpio {
189 status = "okay";
190 gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
191 "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
192 "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
193 "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
194 "", "", "BUTTON", "LED", "", /* 20 - 24 */
195 "", "PMU_INPUT", "", "", "", /* 25 - 29 */
196 "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
197 "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
198 "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
199 "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
200 "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
201 "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
202 "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
203 "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
204 "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
205 "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
206 "", "", /* 78 - 79 */
207 "", "", "", "", "", /* 80 - 84 */
208 "", "", "", "", "", /* 85 - 89 */
209 "", "", "", "", "", /* 90 - 94 */
210 "", "", "", "", "", /* 95 - 99 */
211 "", "", "", "", "", /* 100 - 104 */
212 "", "", "", "", "", /* 105 - 109 */
213 "", "", "", "", "", /* 110 - 114 */
214 "", "", "", "", "", /* 115 - 119 */
215 "", "", "", "", "", /* 120 - 124 */
216 "", "", "", "", "", /* 125 - 129 */
217 "", "", "", "", "", /* 130 - 134 */
218 "", "", "", "", "", /* 135 - 139 */
219 "", "", "", "", "", /* 140 - 144 */
220 "", "", "", "", "", /* 145 - 149 */
221 "", "", "", "", "", /* 150 - 154 */
222 "", "", "", "", "", /* 155 - 159 */
223 "", "", "", "", "", /* 160 - 164 */
224 "", "", "", "", "", /* 165 - 169 */
225 "", "", "", ""; /* 170 - 173 */
226};
227
228&i2c0 {
229 status = "okay";
230 clock-frequency = <400000>;
231 pinctrl-names = "default", "gpio";
232 pinctrl-0 = <&pinctrl_i2c0_default>;
233 pinctrl-1 = <&pinctrl_i2c0_gpio>;
234 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
235 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
236
237 tca6416_u15: gpio@20 { /* u15 */
238 compatible = "ti,tca6416";
239 reg = <0x20>;
240 gpio-controller; /* interrupt not connected */
241 #gpio-cells = <2>;
242 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
243 "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
244 "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
245 "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
246 };
247
248 i2c-mux@75 { /* u17 */
249 compatible = "nxp,pca9544";
250 #address-cells = <1>;
251 #size-cells = <0>;
252 reg = <0x75>;
253 i2c@0 {
254 #address-cells = <1>;
255 #size-cells = <0>;
256 reg = <0>;
257 /* PS_PMBUS */
258 /* PMBUS_ALERT done via pca9544 */
259 vccint: ina226@40 { /* u65 */
260 compatible = "ti,ina226";
261 #io-channel-cells = <1>;
262 label = "ina226-vccint";
263 reg = <0x40>;
264 shunt-resistor = <5000>;
265 };
266 vccint_io_bram_ps: ina226@41 { /* u57 */
267 compatible = "ti,ina226";
268 #io-channel-cells = <1>;
269 label = "ina226-vccint-io-bram-ps";
270 reg = <0x41>;
271 shunt-resistor = <5000>;
272 };
273 vcc1v8: ina226@42 { /* u60 */
274 compatible = "ti,ina226";
275 #io-channel-cells = <1>;
276 label = "ina226-vcc1v8";
277 reg = <0x42>;
278 shunt-resistor = <2000>;
279 };
280 vcc1v2: ina226@43 { /* u58 */
281 compatible = "ti,ina226";
282 #io-channel-cells = <1>;
283 label = "ina226-vcc1v2";
284 reg = <0x43>;
285 shunt-resistor = <5000>;
286 };
287 vadj_fmc: ina226@45 { /* u62 */
288 compatible = "ti,ina226";
289 #io-channel-cells = <1>;
290 label = "ina226-vadj-fmc";
291 reg = <0x45>;
292 shunt-resistor = <5000>;
293 };
294 mgtavcc: ina226@46 { /* u67 */
295 compatible = "ti,ina226";
296 #io-channel-cells = <1>;
297 label = "ina226-mgtavcc";
298 reg = <0x46>;
299 shunt-resistor = <2000>;
300 };
301 mgt1v2: ina226@47 { /* u63 */
302 compatible = "ti,ina226";
303 #io-channel-cells = <1>;
304 label = "ina226-mgt1v2";
305 reg = <0x47>;
306 shunt-resistor = <5000>;
307 };
308 mgt1v8: ina226@48 { /* u64 */
309 compatible = "ti,ina226";
310 #io-channel-cells = <1>;
311 label = "ina226-mgt1v8";
312 reg = <0x48>;
313 shunt-resistor = <5000>;
314 };
315 vccint_ams: ina226@49 { /* u61 */
316 compatible = "ti,ina226";
317 #io-channel-cells = <1>;
318 label = "ina226-vccint-ams";
319 reg = <0x49>;
320 shunt-resistor = <5000>;
321 };
322 dac_avtt: ina226@4a { /* u59 */
323 compatible = "ti,ina226";
324 #io-channel-cells = <1>;
325 label = "ina226-dac-avtt";
326 reg = <0x4a>;
327 shunt-resistor = <5000>;
328 };
329 dac_avccaux: ina226@4b { /* u124 */
330 compatible = "ti,ina226";
331 #io-channel-cells = <1>;
332 label = "ina226-dac-avccaux";
333 reg = <0x4b>;
334 shunt-resistor = <5000>;
335 };
336 adc_avcc: ina226@4c { /* u75 */
337 compatible = "ti,ina226";
338 #io-channel-cells = <1>;
339 label = "ina226-adc-avcc";
340 reg = <0x4c>;
341 shunt-resistor = <5000>;
342 };
343 adc_avccaux: ina226@4d { /* u71 */
344 compatible = "ti,ina226";
345 #io-channel-cells = <1>;
346 label = "ina226-adc-avccaux";
347 reg = <0x4d>;
348 shunt-resistor = <5000>;
349 };
350 dac_avcc: ina226@4e { /* u77 */
351 compatible = "ti,ina226";
352 #io-channel-cells = <1>;
353 label = "ina226-dac-avcc";
354 reg = <0x4e>;
355 shunt-resistor = <5000>;
356 };
357 };
358 i2c@1 {
359 #address-cells = <1>;
360 #size-cells = <0>;
361 reg = <1>;
362 /* NC */
363 };
364 i2c@2 {
365 #address-cells = <1>;
366 #size-cells = <0>;
367 reg = <2>;
368 /* u104 - ir35215 0x10/0x40 */
369 /* u127 - ir38164 0x1b/0x4b */
370 /* u112 - ir38164 0x13/0x43 */
371 /* u123 - ir38164 0x1c/0x4c */
372
373 irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
374 compatible = "infineon,irps5401";
375 reg = <0x44>; /* i2c addr 0x14 */
376 };
377 irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
378 compatible = "infineon,irps5401";
379 reg = <0x45>; /* i2c addr 0x15 */
380 };
381 /* J21 header too */
382
383 };
384 i2c@3 {
385 #address-cells = <1>;
386 #size-cells = <0>;
387 reg = <3>;
388 /* SYSMON */
389 };
390 };
391 /* u38 MPS430 */
392};
393
394&i2c1 {
395 status = "okay";
396 clock-frequency = <400000>;
397 pinctrl-names = "default", "gpio";
398 pinctrl-0 = <&pinctrl_i2c1_default>;
399 pinctrl-1 = <&pinctrl_i2c1_gpio>;
400 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
401 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
402
403 i2c-mux@74 {
404 compatible = "nxp,pca9548"; /* u20 */
405 #address-cells = <1>;
406 #size-cells = <0>;
407 reg = <0x74>;
408 i2c-mux-idle-disconnect;
409 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
410 i2c_eeprom: i2c@0 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 reg = <0>;
414 /*
415 * IIC_EEPROM 1kB memory which uses 256B blocks
416 * where every block has different address.
417 * 0 - 256B address 0x54
418 * 256B - 512B address 0x55
419 * 512B - 768B address 0x56
420 * 768B - 1024B address 0x57
421 */
422 eeprom: eeprom@54 { /* u21 */
423 compatible = "atmel,24c128";
424 reg = <0x54>;
425 };
426 };
427 i2c_si5341: i2c@1 {
428 #address-cells = <1>;
429 #size-cells = <0>;
430 reg = <1>;
431 si5341: clock-generator@36 { /* SI5341 - u43 */
432 compatible = "silabs,si5341";
433 reg = <0x36>;
434 #clock-cells = <2>;
435 #address-cells = <1>;
436 #size-cells = <0>;
437 clocks = <&ref48>;
438 clock-names = "xtal";
439 clock-output-names = "si5341";
440
441 si5341_2: out@2 {
442 /* refclk2 for PS-GT, used for USB3 */
443 reg = <2>;
444 always-on;
445 };
446 si5341_3: out@3 {
447 /* refclk3 for PS-GT, used for SATA */
448 reg = <3>;
449 always-on;
450 };
451 si5341_5: out@5 {
452 /* refclk5 PL CLK100 */
453 reg = <5>;
454 always-on;
455 };
456 si5341_6: out@6 {
457 /* refclk6 PL CLK125 */
458 reg = <6>;
459 always-on;
460 };
461 si5341_9: out@9 {
462 /* refclk9 used for PS_REF_CLK 33.3 MHz */
463 reg = <9>;
464 always-on;
465 };
466 };
467 };
468 i2c_si570_user_c0: i2c@2 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 reg = <2>;
472 si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
473 #clock-cells = <0>;
474 compatible = "silabs,si570";
475 reg = <0x5d>;
476 temperature-stability = <50>;
477 factory-fout = <300000000>;
478 clock-frequency = <300000000>;
479 clock-output-names = "si570_user_c0";
480 };
481 };
482 i2c_si570_mgt: i2c@3 {
483 #address-cells = <1>;
484 #size-cells = <0>;
485 reg = <3>;
486 si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
487 #clock-cells = <0>;
488 compatible = "silabs,si570";
489 reg = <0x5d>;
490 temperature-stability = <50>;
491 factory-fout = <156250000>;
492 clock-frequency = <156250000>;
493 clock-output-names = "si570_mgt";
494 };
495 };
496 i2c_8a34001: i2c@4 {
497 #address-cells = <1>;
498 #size-cells = <0>;
499 reg = <4>;
500 idt_8a34001: phc@5b {
501 compatible = "idt,8a34001"; /* u409B */
502 reg = <0x5b>;
503 };
504 };
505 i2c_clk104: i2c@5 {
506 #address-cells = <1>;
507 #size-cells = <0>;
508 reg = <5>;
509 /* CLK104_SDA */
510 };
511 i2c@6 {
512 #address-cells = <1>;
513 #size-cells = <0>;
514 reg = <6>;
515 /* RFMCP connector */
516 };
517 /* 7 NC */
518 };
519
520 i2c-mux@75 {
521 compatible = "nxp,pca9548"; /* u22 */
522 #address-cells = <1>;
523 #size-cells = <0>;
524 reg = <0x75>;
525 i2c-mux-idle-disconnect;
526 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
527 i2c@0 {
528 #address-cells = <1>;
529 #size-cells = <0>;
530 reg = <0>;
531 /* FMCP_HSPC_IIC */
532 };
533 i2c_si570_user_c1: i2c@1 {
534 #address-cells = <1>;
535 #size-cells = <0>;
536 reg = <1>;
537 si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
538 #clock-cells = <0>;
539 compatible = "silabs,si570";
540 reg = <0x5d>;
541 temperature-stability = <50>;
542 factory-fout = <300000000>;
543 clock-frequency = <300000000>;
544 clock-output-names = "si570_user_c1";
545 };
546 };
547 i2c@2 {
548 #address-cells = <1>;
549 #size-cells = <0>;
550 reg = <2>;
551 /* SYSMON */
552 };
553 i2c@3 {
554 #address-cells = <1>;
555 #size-cells = <0>;
556 reg = <3>;
557 /* DDR4 SODIMM */
558 };
559 i2c@4 {
560 #address-cells = <1>;
561 #size-cells = <0>;
562 reg = <4>;
563 /* SFP3 */
564 };
565 i2c@5 {
566 #address-cells = <1>;
567 #size-cells = <0>;
568 reg = <5>;
569 /* SFP2 */
570 };
571 i2c@6 {
572 #address-cells = <1>;
573 #size-cells = <0>;
574 reg = <6>;
575 /* SFP1 */
576 };
577 i2c@7 {
578 #address-cells = <1>;
579 #size-cells = <0>;
580 reg = <7>;
581 /* SFP0 */
582 };
583 };
584 /* MSP430 */
585};
586
587&pinctrl0 {
588 status = "okay";
589 pinctrl_i2c0_default: i2c0-default {
590 mux {
591 groups = "i2c0_3_grp";
592 function = "i2c0";
593 };
594
595 conf {
596 groups = "i2c0_3_grp";
597 bias-pull-up;
598 slew-rate = <SLEW_RATE_SLOW>;
599 power-source = <IO_STANDARD_LVCMOS18>;
600 };
601 };
602
603 pinctrl_i2c0_gpio: i2c0-gpio-grp {
604 mux {
605 groups = "gpio0_14_grp", "gpio0_15_grp";
606 function = "gpio0";
607 };
608
609 conf {
610 groups = "gpio0_14_grp", "gpio0_15_grp";
611 slew-rate = <SLEW_RATE_SLOW>;
612 power-source = <IO_STANDARD_LVCMOS18>;
613 };
614 };
615
616 pinctrl_i2c1_default: i2c1-default {
617 mux {
618 groups = "i2c1_4_grp";
619 function = "i2c1";
620 };
621
622 conf {
623 groups = "i2c1_4_grp";
624 bias-pull-up;
625 slew-rate = <SLEW_RATE_SLOW>;
626 power-source = <IO_STANDARD_LVCMOS18>;
627 };
628 };
629
630 pinctrl_i2c1_gpio: i2c1-gpio-grp {
631 mux {
632 groups = "gpio0_16_grp", "gpio0_17_grp";
633 function = "gpio0";
634 };
635
636 conf {
637 groups = "gpio0_16_grp", "gpio0_17_grp";
638 slew-rate = <SLEW_RATE_SLOW>;
639 power-source = <IO_STANDARD_LVCMOS18>;
640 };
641 };
642};
643
644&qspi {
645 status = "okay";
646 num-cs = <2>;
647 flash@0 {
648 compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
649 #address-cells = <1>;
650 #size-cells = <1>;
651 reg = <0>, <1>;
652 parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
653 spi-tx-bus-width = <4>;
654 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
655 spi-max-frequency = <108000000>; /* Based on DC1 spec */
656 };
657};
658
659&psgtr {
660 status = "okay";
661 /* nc, nc, usb3, sata */
662 clocks = <&si5341 0 2>, <&si5341 0 3>;
663 clock-names = "ref2", "ref3";
664};
665
666&rtc {
667 status = "okay";
668};
669
670&sata {
671 status = "okay";
672 /* SATA OOB timing settings */
673 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
674 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
675 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
676 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
677 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
678 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
679 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
680 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
681 phy-names = "sata-phy";
682 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
683};
684
685/* SD1 with level shifter */
686&sdhci1 {
687 status = "okay";
688 disable-wp;
689 /*
690 * This property should be removed for supporting UHS mode
691 */
692 no-1-8-v;
693 xlnx,mio-bank = <1>;
694};
695
696&uart0 {
697 status = "okay";
698};
699
700/* ULPI SMSC USB3320 */
701&usb0 {
702 status = "okay";
703 phy-names = "usb3-phy";
704 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
705};
706
707&dwc3_0 {
708 status = "okay";
709 dr_mode = "host";
710 snps,usb3_lpm_capable;
711 maximum-speed = "super-speed";
712};