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"Das U-Boot" Source Tree
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u-boot / arch / Kconfig
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Tom Rini drivers/mmc/Kconfig: Make DM_MMC a hidden symbol
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1config ARCH_MAP_SYSMEM 2 depends on SANDBOX 3 def_bool y 4 5config CREATE_ARCH_SYMLINK 6 bool 7 8config HAVE_ARCH_IOREMAP 9 bool 10 11config HAVE_SETJMP 12 bool 13 help 14 The architecture supports setjmp() and longjmp(). 15 16config SUPPORT_BIG_ENDIAN 17 bool 18 19config SUPPORT_LITTLE_ENDIAN 20 bool 21 default y if !SUPPORT_BIG_ENDIAN 22 23config SYS_CACHE_SHIFT_4 24 bool 25 26config SYS_CACHE_SHIFT_5 27 bool 28 29config SYS_CACHE_SHIFT_6 30 bool 31 32config SYS_CACHE_SHIFT_7 33 bool 34 35config 32BIT 36 bool 37 38config 64BIT 39 bool 40 help 41 Indicates that U-Boot proper will be built for a 64 bit 42 architecture. 43 44config SPL_64BIT 45 bool 46 help 47 Indicates that SPL will be built for a 64 bit architecture. 48 49config SYS_CACHELINE_SIZE 50 int 51 default 128 if SYS_CACHE_SHIFT_7 52 default 64 if SYS_CACHE_SHIFT_6 53 default 32 if SYS_CACHE_SHIFT_5 54 default 16 if SYS_CACHE_SHIFT_4 55 # Fall-back for MIPS and RISC-V 56 default 64 if RISCV 57 default 32 if MIPS 58 59config LINKER_LIST_ALIGN 60 int 61 default 32 if SANDBOX 62 default 8 if ARM64 || X86 63 default 4 64 help 65 Force the each linker list to be aligned to this boundary. This 66 is required if ll_entry_get() is used, since otherwise the linker 67 may add padding into the table, thus breaking it. 68 See linker_lists.rst for full details. 69 70choice 71 prompt "Architecture select" 72 default SANDBOX 73 74config ARC 75 bool "ARC architecture" 76 select ARC_TIMER 77 select CLK 78 select DM 79 select HAVE_PRIVATE_LIBGCC 80 select SUPPORT_OF_CONTROL 81 select SYS_CACHE_SHIFT_7 82 select TIMER 83 select SUPPORT_BIG_ENDIAN 84 select SUPPORT_LITTLE_ENDIAN 85 select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN 86 select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN 87 88config ARM 89 bool "ARM architecture" 90 select HAVE_SETJMP 91 select ARCH_SUPPORTS_LTO 92 select CREATE_ARCH_SYMLINK 93 select HAVE_PRIVATE_LIBGCC if !ARM64 94 select SUPPORT_ACPI 95 select SUPPORT_LITTLE_ENDIAN 96 select SUPPORT_OF_CONTROL 97 98config M68K 99 bool "M68000 architecture" 100 select HAVE_PRIVATE_LIBGCC 101 select USE_PRIVATE_LIBGCC 102 select SYS_BOOT_GET_CMDLINE 103 select SYS_BOOT_GET_KBD 104 select SYS_CACHE_SHIFT_4 105 select SUPPORT_BIG_ENDIAN 106 select SUPPORT_OF_CONTROL 107 108config MICROBLAZE 109 bool "MicroBlaze architecture" 110 select SUPPORT_BIG_ENDIAN 111 select SUPPORT_LITTLE_ENDIAN 112 select SUPPORT_OF_CONTROL 113 imply CMD_TIMER 114 imply SPL_REGMAP if SPL 115 imply SPL_TIMER if SPL 116 imply TIMER 117 imply XILINX_TIMER 118 119config MIPS 120 bool "MIPS architecture" 121 select HAVE_ARCH_IOREMAP 122 select HAVE_PRIVATE_LIBGCC 123 select SUPPORT_OF_CONTROL 124 select SPL_SEPARATE_BSS if SPL 125 126config NIOS2 127 bool "Nios II architecture" 128 select CPU 129 select DM 130 select DM_EVENT 131 select OF_CONTROL 132 select SUPPORT_LITTLE_ENDIAN 133 select SUPPORT_OF_CONTROL 134 imply CMD_DM 135 136config PPC 137 bool "PowerPC architecture" 138 select HAVE_PRIVATE_LIBGCC 139 select SUPPORT_BIG_ENDIAN 140 select SUPPORT_OF_CONTROL 141 select SYS_BOOT_GET_CMDLINE 142 select SYS_BOOT_GET_KBD 143 144config RISCV 145 bool "RISC-V architecture" 146 select CREATE_ARCH_SYMLINK 147 select HAVE_SETJMP 148 select SUPPORT_ACPI 149 select SUPPORT_LITTLE_ENDIAN 150 select SUPPORT_OF_CONTROL 151 select OF_CONTROL 152 select DM 153 select DM_EVENT 154 imply SPL_SEPARATE_BSS if SPL 155 imply DM_SERIAL 156 imply DM_MMC 157 imply DM_SPI 158 imply DM_SPI_FLASH 159 imply BLK 160 imply CLK 161 imply MTD 162 imply TIMER 163 imply CMD_DM 164 imply SPL_DM 165 imply SPL_OF_CONTROL 166 imply SPL_LIBCOMMON_SUPPORT 167 imply SPL_LIBGENERIC_SUPPORT 168 imply SPL_SERIAL 169 imply SPL_TIMER 170 171config SANDBOX 172 bool "Sandbox" 173 select HAVE_SETJMP 174 select ARCH_SUPPORTS_LTO 175 select BOARD_LATE_INIT 176 select BZIP2 177 select CMD_POWEROFF if CMDLINE 178 select DM 179 select DM_EVENT 180 select DM_FUZZING_ENGINE 181 select DM_GPIO 182 select DM_I2C 183 select DM_KEYBOARD 184 select DM_SERIAL 185 select DM_SPI 186 select DM_SPI_FLASH 187 select GZIP_COMPRESSED 188 select IO_TRACE 189 select LZO 190 select MMC 191 select MTD 192 select OF_BOARD_SETUP 193 select PCI_ENDPOINT 194 select SPI 195 select SUPPORT_OF_CONTROL 196 select SUPPORT_BIG_ENDIAN 197 select SUPPORT_LITTLE_ENDIAN 198 select SYSRESET_CMD_POWEROFF if CMD_POWEROFF 199 select SYS_CACHE_SHIFT_4 200 select IRQ 201 select SUPPORT_EXTENSION_SCAN if CMDLINE 202 select SUPPORT_ACPI 203 imply BITREVERSE 204 select BLOBLIST 205 imply LTO 206 imply CMD_DM 207 imply CMD_EXCEPTION 208 imply CMD_GETTIME 209 imply CMD_HASH 210 imply CMD_IO 211 imply CMD_IOTRACE 212 imply CMD_LZMADEC 213 imply CMD_SF 214 imply CMD_SF_TEST 215 imply CRC32_VERIFY 216 imply FAT_WRITE 217 imply FIRMWARE 218 imply FUZZING_ENGINE_SANDBOX 219 imply HASH_VERIFY 220 imply LZMA 221 imply TEE 222 imply AVB_VERIFY 223 imply LIBAVB 224 imply CMD_AVB 225 imply PARTITION_TYPE_GUID 226 imply SCP03 227 imply CMD_SCP03 228 imply UDP_FUNCTION_FASTBOOT 229 imply VIRTIO_MMIO 230 imply VIRTIO_PCI 231 imply VIRTIO_SANDBOX 232 # Re-enable this when fully implemented 233 # imply VIRTIO_BLK 234 imply VIRTIO_NET 235 imply DM_SOUND 236 imply PCI_SANDBOX_EP 237 imply PCH 238 imply PHYLIB 239 imply DM_MDIO 240 imply DM_MDIO_MUX 241 imply ACPI 242 imply ACPI_PMC 243 imply ACPI_PMC_SANDBOX 244 imply CMD_PMC 245 imply CMD_CLONE 246 imply SILENT_CONSOLE 247 imply BOOTARGS_SUBST 248 imply PHY_FIXED 249 imply DM_DSA 250 imply CMD_EXTENSION 251 imply KEYBOARD 252 imply PHYSMEM 253 imply GENERATE_ACPI_TABLE 254 imply BINMAN 255 imply CMD_MBR 256 imply CMD_MMC 257 imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE 258 imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE 259 imply CMD_SYSBOOT if BOOTSTD_FULL 260 261config SH 262 bool "SuperH architecture" 263 select SUPPORT_LITTLE_ENDIAN 264 select HAVE_PRIVATE_LIBGCC 265 select SUPPORT_OF_CONTROL 266 267config X86 268 bool "x86 architecture" 269 select HAVE_SETJMP 270 select SUPPORT_SPL 271 select SUPPORT_TPL 272 select SUPPORT_LITTLE_ENDIAN 273 select CREATE_ARCH_SYMLINK 274 select DM 275 select HAVE_ARCH_IOMAP 276 select HAVE_PRIVATE_LIBGCC 277 select OF_CONTROL 278 select PCI 279 select SUPPORT_ACPI 280 select SUPPORT_OF_CONTROL 281 select SYS_CACHE_SHIFT_6 282 select TIMER 283 select USE_PRIVATE_LIBGCC 284 select X86_TSC_TIMER 285 select IRQ 286 imply HAS_ROM if X86_RESET_VECTOR 287 imply BLK 288 imply CMD_DM 289 imply CMD_FPGA_LOADMK 290 imply CMD_GETTIME 291 imply CMD_IO 292 imply CMD_IRQ 293 imply CMD_PCI 294 imply CMD_SF 295 imply CMD_SF_TEST 296 imply DM_GPIO 297 imply DM_KEYBOARD 298 imply DM_MMC 299 imply DM_RTC 300 imply SCSI 301 imply DM_SERIAL 302 imply MTD 303 imply DM_SPI 304 imply DM_SPI_FLASH 305 imply DM_USB 306 imply LAST_STAGE_INIT 307 imply VIDEO 308 imply SYSRESET 309 imply SPL_SYSRESET 310 imply SYSRESET_X86 311 imply USB_ETHER_ASIX 312 imply USB_ETHER_SMSC95XX 313 imply USB_HOST_ETHER 314 imply PCH 315 imply PHYSMEM 316 imply RTC_MC146818 317 imply ACPI 318 imply ACPIGEN if !QEMU && !EFI_APP 319 imply SYSINFO if GENERATE_SMBIOS_TABLE 320 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE 321 imply TIMESTAMP 322 323 # Thing to enable for when SPL/TPL are enabled: SPL 324 imply SPL_DM 325 imply SPL_OF_LIBFDT 326 imply SPL_DRIVERS_MISC 327 imply SPL_GPIO 328 imply SPL_PINCTRL 329 imply SPL_LIBCOMMON_SUPPORT 330 imply SPL_LIBGENERIC_SUPPORT 331 imply SPL_SERIAL 332 imply SPL_SPI_FLASH_SUPPORT 333 imply SPL_SPI 334 imply SPL_OF_CONTROL 335 imply SPL_TIMER 336 imply SPL_REGMAP 337 imply SPL_SYSCON 338 # TPL 339 imply TPL_DM 340 imply TPL_DRIVERS_MISC 341 imply TPL_GPIO 342 imply TPL_PINCTRL 343 imply TPL_LIBCOMMON_SUPPORT 344 imply TPL_LIBGENERIC_SUPPORT 345 imply TPL_SERIAL 346 imply TPL_OF_CONTROL 347 imply TPL_TIMER 348 imply TPL_REGMAP 349 imply TPL_SYSCON 350 351config XTENSA 352 bool "Xtensa architecture" 353 select CREATE_ARCH_SYMLINK 354 select SUPPORT_LITTLE_ENDIAN 355 select SUPPORT_OF_CONTROL 356 357endchoice 358 359config SYS_ARCH 360 string 361 help 362 This option should contain the architecture name to build the 363 appropriate arch/<CONFIG_SYS_ARCH> directory. 364 All the architectures should specify this option correctly. 365 366config SYS_CPU 367 string 368 help 369 This option should contain the CPU name to build the correct 370 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory. 371 372 This is optional. For those targets without the CPU directory, 373 leave this option empty. 374 375config SYS_SOC 376 string 377 help 378 This option should contain the SoC name to build the directory 379 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>. 380 381 This is optional. For those targets without the SoC directory, 382 leave this option empty. 383 384config SYS_VENDOR 385 string 386 help 387 This option should contain the vendor name of the target board. 388 If it is set and 389 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common 390 directory is compiled. 391 If CONFIG_SYS_BOARD is also set, the sources under 392 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled. 393 394 This is optional. For those targets without the vendor directory, 395 leave this option empty. 396 397config SYS_BOARD 398 string 399 help 400 This option should contain the name of the target board. 401 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> 402 or board/<CONFIG_SYS_BOARD> directory is compiled depending on 403 whether CONFIG_SYS_VENDOR is set or not. 404 405 This is optional. For those targets without the board directory, 406 leave this option empty. 407 408config SYS_CONFIG_NAME 409 string "Board header file" if ARCH_MESON || ARCH_VERSAL || \ 410 ARCH_VERSAL_NET || ARCH_ZYNQ || ARCH_ZYNQMP || \ 411 ARCH_ZYNQMP_R5 || MICROBLAZE || NIOS2 412 default "meson64" if ARCH_MESON 413 default "microblaze-generic" if MICROBLAZE 414 default "xilinx_versal" if ARCH_VERSAL 415 default "xilinx_versal_net" if ARCH_VERSAL_NET 416 default "xilinx_zynqmp" if ARCH_ZYNQMP 417 default "xilinx_zynqmp_r5" if ARCH_ZYNQMP_R5 418 default "zynq-common" if ARCH_ZYNQ 419 help 420 This option should contain the base name of board header file. 421 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h 422 should be included from include/config.h. 423 424config SYS_DISABLE_DCACHE_OPS 425 bool 426 help 427 This option disables dcache flush and dcache invalidation 428 operations. For example, on coherent systems where cache 429 operatios are not required, enable this option to avoid them. 430 Note that, its up to the individual architectures to implement 431 this functionality. 432 433config SYS_IMMR 434 hex "Address for the Internal Memory-Mapped Registers (IMMR) window" 435 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A 436 default 0xFF000000 if MPC8xx 437 default 0xF0000000 if ARCH_MPC8313 438 default 0xE0000000 if MPC83xx && !ARCH_MPC8313 439 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 440 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \ 441 ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \ 442 ARCH_P2020 443 default SYS_CCSRBAR_DEFAULT 444 help 445 Address for the Internal Memory-Mapped Registers (IMMR) window used 446 to configure the features of many Freescale / NXP SoCs. 447 448config MONITOR_IS_IN_RAM 449 bool "U-Boot is loaded in to RAM by a pre-loader" 450 depends on M68K || NIOS2 451 452menu "Skipping low level initialization functions" 453 depends on ARM || MIPS || RISCV 454 455config SKIP_LOWLEVEL_INIT 456 bool "Skip calls to certain low level initialization functions" 457 help 458 If enabled, then certain low level initializations (like setting up 459 the memory controller) are omitted and/or U-Boot does not relocate 460 itself into RAM. 461 Normally this variable MUST NOT be defined. The only exception is 462 when U-Boot is loaded (to RAM) by some other boot loader or by a 463 debugger which performs these initializations itself. 464 465config SPL_SKIP_LOWLEVEL_INIT 466 bool "Skip calls to certain low level initialization functions in SPL" 467 depends on SPL 468 help 469 If enabled, then certain low level initializations (like setting up 470 the memory controller) are omitted and/or U-Boot does not relocate 471 itself into RAM. 472 Normally this variable MUST NOT be defined. The only exception is 473 when U-Boot is loaded (to RAM) by some other boot loader or by a 474 debugger which performs these initializations itself. 475 476config TPL_SKIP_LOWLEVEL_INIT 477 bool "Skip calls to certain low level initialization functions in TPL" 478 depends on SPL && ARM 479 help 480 If enabled, then certain low level initializations (like setting up 481 the memory controller) are omitted and/or U-Boot does not relocate 482 itself into RAM. 483 Normally this variable MUST NOT be defined. The only exception is 484 when U-Boot is loaded (to RAM) by some other boot loader or by a 485 debugger which performs these initializations itself. 486 487config SKIP_LOWLEVEL_INIT_ONLY 488 bool "Skip call to lowlevel_init during early boot ONLY" 489 depends on ARM 490 help 491 This allows just the call to lowlevel_init() to be skipped. The 492 normal CP15 init (such as enabling the instruction cache) is still 493 performed. 494 495config SPL_SKIP_LOWLEVEL_INIT_ONLY 496 bool "Skip call to lowlevel_init during early SPL boot ONLY" 497 depends on SPL && ARM 498 help 499 This allows just the call to lowlevel_init() to be skipped. The 500 normal CP15 init (such as enabling the instruction cache) is still 501 performed. 502 503config TPL_SKIP_LOWLEVEL_INIT_ONLY 504 bool "Skip call to lowlevel_init during early TPL boot ONLY" 505 depends on TPL && ARM 506 help 507 This allows just the call to lowlevel_init() to be skipped. The 508 normal CP15 init (such as enabling the instruction cache) is still 509 performed. 510 511endmenu 512 513config SYS_HAS_NONCACHED_MEMORY 514 bool "Enable reserving a non-cached memory area for drivers" 515 depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH) 516 help 517 This is useful for drivers that would otherwise require a lot of 518 explicit cache maintenance. For some drivers it's also impossible to 519 properly maintain the cache. For example if the regions that need to 520 be flushed are not a multiple of the cache-line size, *and* padding 521 cannot be allocated between the regions to align them (i.e. if the 522 HW requires a contiguous array of regions, and the size of each 523 region is not cache-aligned), then a flush of one region may result 524 in overwriting data that hardware has written to another region in 525 the same cache-line. This can happen for example in network drivers 526 where descriptors for buffers are typically smaller than the CPU 527 cache-line (e.g. 16 bytes vs. 32 or 64 bytes). 528 529config SYS_NONCACHED_MEMORY 530 hex "Size in bytes of the non-cached memory area" 531 depends on SYS_HAS_NONCACHED_MEMORY 532 default 0x100000 533 help 534 Size of non-cached memory area. This area of memory will be typically 535 located right below the malloc() area and mapped uncached in the MMU. 536 537source "arch/arc/Kconfig" 538source "arch/arm/Kconfig" 539source "arch/m68k/Kconfig" 540source "arch/microblaze/Kconfig" 541source "arch/mips/Kconfig" 542source "arch/nios2/Kconfig" 543source "arch/powerpc/Kconfig" 544source "arch/sandbox/Kconfig" 545source "arch/sh/Kconfig" 546source "arch/x86/Kconfig" 547source "arch/xtensa/Kconfig" 548source "arch/riscv/Kconfig" 549 550if ARM || M68K || PPC 551 552source "arch/Kconfig.nxp" 553 554endif 555 556source "board/keymile/Kconfig" 557 558choice 559 prompt "Endianness selection" 560 default SYS_BIG_ENDIAN if MIPS || MICROBLAZE 561 default SYS_LITTLE_ENDIAN 562 help 563 Some boards can be configured for either little or big endian 564 byte order. These modes require different U-Boot images. In general there 565 is one preferred byteorder for a particular system but some systems are 566 just as commonly used in the one or the other endianness. 567 568config SYS_BIG_ENDIAN 569 bool "Big endian" 570 depends on SUPPORT_BIG_ENDIAN 571 572config SYS_LITTLE_ENDIAN 573 bool "Little endian" 574 depends on SUPPORT_LITTLE_ENDIAN 575endchoice