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Serenity Operating System
1/*
2 * Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <Kernel/Net/E1000NetworkAdapter.h>
28#include <Kernel/Thread.h>
29#include <LibBareMetal/IO.h>
30
31//#define E1000_DEBUG
32
33namespace Kernel {
34
35#define REG_CTRL 0x0000
36#define REG_STATUS 0x0008
37#define REG_EEPROM 0x0014
38#define REG_CTRL_EXT 0x0018
39#define REG_IMASK 0x00D0
40#define REG_RCTRL 0x0100
41#define REG_RXDESCLO 0x2800
42#define REG_RXDESCHI 0x2804
43#define REG_RXDESCLEN 0x2808
44#define REG_RXDESCHEAD 0x2810
45#define REG_RXDESCTAIL 0x2818
46#define REG_TCTRL 0x0400
47#define REG_TXDESCLO 0x3800
48#define REG_TXDESCHI 0x3804
49#define REG_TXDESCLEN 0x3808
50#define REG_TXDESCHEAD 0x3810
51#define REG_TXDESCTAIL 0x3818
52#define REG_RDTR 0x2820 // RX Delay Timer Register
53#define REG_RXDCTL 0x3828 // RX Descriptor Control
54#define REG_RADV 0x282C // RX Int. Absolute Delay Timer
55#define REG_RSRPD 0x2C00 // RX Small Packet Detect Interrupt
56#define REG_TIPG 0x0410 // Transmit Inter Packet Gap
57#define ECTRL_SLU 0x40 //set link up
58#define RCTL_EN (1 << 1) // Receiver Enable
59#define RCTL_SBP (1 << 2) // Store Bad Packets
60#define RCTL_UPE (1 << 3) // Unicast Promiscuous Enabled
61#define RCTL_MPE (1 << 4) // Multicast Promiscuous Enabled
62#define RCTL_LPE (1 << 5) // Long Packet Reception Enable
63#define RCTL_LBM_NONE (0 << 6) // No Loopback
64#define RCTL_LBM_PHY (3 << 6) // PHY or external SerDesc loopback
65#define RTCL_RDMTS_HALF (0 << 8) // Free Buffer Threshold is 1/2 of RDLEN
66#define RTCL_RDMTS_QUARTER (1 << 8) // Free Buffer Threshold is 1/4 of RDLEN
67#define RTCL_RDMTS_EIGHTH (2 << 8) // Free Buffer Threshold is 1/8 of RDLEN
68#define RCTL_MO_36 (0 << 12) // Multicast Offset - bits 47:36
69#define RCTL_MO_35 (1 << 12) // Multicast Offset - bits 46:35
70#define RCTL_MO_34 (2 << 12) // Multicast Offset - bits 45:34
71#define RCTL_MO_32 (3 << 12) // Multicast Offset - bits 43:32
72#define RCTL_BAM (1 << 15) // Broadcast Accept Mode
73#define RCTL_VFE (1 << 18) // VLAN Filter Enable
74#define RCTL_CFIEN (1 << 19) // Canonical Form Indicator Enable
75#define RCTL_CFI (1 << 20) // Canonical Form Indicator Bit Value
76#define RCTL_DPF (1 << 22) // Discard Pause Frames
77#define RCTL_PMCF (1 << 23) // Pass MAC Control Frames
78#define RCTL_SECRC (1 << 26) // Strip Ethernet CRC
79
80// Buffer Sizes
81#define RCTL_BSIZE_256 (3 << 16)
82#define RCTL_BSIZE_512 (2 << 16)
83#define RCTL_BSIZE_1024 (1 << 16)
84#define RCTL_BSIZE_2048 (0 << 16)
85#define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
86#define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
87#define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
88
89// Transmit Command
90
91#define CMD_EOP (1 << 0) // End of Packet
92#define CMD_IFCS (1 << 1) // Insert FCS
93#define CMD_IC (1 << 2) // Insert Checksum
94#define CMD_RS (1 << 3) // Report Status
95#define CMD_RPS (1 << 4) // Report Packet Sent
96#define CMD_VLE (1 << 6) // VLAN Packet Enable
97#define CMD_IDE (1 << 7) // Interrupt Delay Enable
98
99// TCTL Register
100
101#define TCTL_EN (1 << 1) // Transmit Enable
102#define TCTL_PSP (1 << 3) // Pad Short Packets
103#define TCTL_CT_SHIFT 4 // Collision Threshold
104#define TCTL_COLD_SHIFT 12 // Collision Distance
105#define TCTL_SWXOFF (1 << 22) // Software XOFF Transmission
106#define TCTL_RTLC (1 << 24) // Re-transmit on Late Collision
107
108#define TSTA_DD (1 << 0) // Descriptor Done
109#define TSTA_EC (1 << 1) // Excess Collisions
110#define TSTA_LC (1 << 2) // Late Collision
111#define LSTA_TU (1 << 3) // Transmit Underrun
112
113// STATUS Register
114
115#define STATUS_FD 0x01
116#define STATUS_LU 0x02
117#define STATUS_TXOFF 0x08
118#define STATUS_SPEED 0xC0
119#define STATUS_SPEED_10MB 0x00
120#define STATUS_SPEED_100MB 0x40
121#define STATUS_SPEED_1000MB1 0x80
122#define STATUS_SPEED_1000MB2 0xC0
123
124void E1000NetworkAdapter::detect(const PCI::Address& address)
125{
126 if (address.is_null())
127 return;
128 static const PCI::ID qemu_bochs_vbox_id = { 0x8086, 0x100e };
129 const PCI::ID id = PCI::get_id(address);
130 if (id != qemu_bochs_vbox_id)
131 return;
132 u8 irq = PCI::get_interrupt_line(address);
133 (void)adopt(*new E1000NetworkAdapter(address, irq)).leak_ref();
134}
135
136E1000NetworkAdapter::E1000NetworkAdapter(PCI::Address address, u8 irq)
137 : PCI::Device(address, irq)
138{
139 set_interface_name("e1k");
140
141 kprintf("E1000: Found at PCI address @ %w:%b:%b.%b\n", pci_address().seg(), pci_address().bus(), pci_address().slot(), pci_address().function());
142
143 enable_bus_mastering(pci_address());
144
145 size_t mmio_base_size = PCI::get_BAR_Space_Size(pci_address(), 0);
146 m_mmio_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of(PCI::get_BAR0(pci_address()))), PAGE_ROUND_UP(mmio_base_size), "E1000 MMIO", Region::Access::Read | Region::Access::Write, false, false);
147 m_mmio_base = m_mmio_region->vaddr();
148 m_use_mmio = true;
149 m_io_base = PCI::get_BAR1(pci_address()) & ~1;
150 m_interrupt_line = PCI::get_interrupt_line(pci_address());
151 kprintf("E1000: IO port base: %w\n", m_io_base);
152 kprintf("E1000: MMIO base: P%x\n", PCI::get_BAR0(pci_address()) & 0xfffffffc);
153 kprintf("E1000: MMIO base size: %u bytes\n", mmio_base_size);
154 kprintf("E1000: Interrupt line: %u\n", m_interrupt_line);
155 detect_eeprom();
156 kprintf("E1000: Has EEPROM? %u\n", m_has_eeprom);
157 read_mac_address();
158 const auto& mac = mac_address();
159 kprintf("E1000: MAC address: %b:%b:%b:%b:%b:%b\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
160
161 u32 flags = in32(REG_CTRL);
162 out32(REG_CTRL, flags | ECTRL_SLU);
163
164 initialize_rx_descriptors();
165 initialize_tx_descriptors();
166
167 out32(REG_IMASK, 0x1f6dc);
168 out32(REG_IMASK, 0xff & ~4);
169 in32(0xc0);
170
171 enable_irq();
172}
173
174E1000NetworkAdapter::~E1000NetworkAdapter()
175{
176}
177
178void E1000NetworkAdapter::handle_irq(RegisterState&)
179{
180 out32(REG_IMASK, 0x1);
181
182 u32 status = in32(0xc0);
183 if (status & 4) {
184 u32 flags = in32(REG_CTRL);
185 out32(REG_CTRL, flags | ECTRL_SLU);
186 }
187 if (status & 0x10) {
188 // Threshold OK?
189 }
190 if (status & 0x80) {
191 receive();
192 }
193
194 m_wait_queue.wake_all();
195}
196
197void E1000NetworkAdapter::detect_eeprom()
198{
199 out32(REG_EEPROM, 0x1);
200 for (volatile int i = 0; i < 999; ++i) {
201 u32 data = in32(REG_EEPROM);
202 if (data & 0x10) {
203 m_has_eeprom = true;
204 return;
205 }
206 }
207 m_has_eeprom = false;
208}
209
210u32 E1000NetworkAdapter::read_eeprom(u8 address)
211{
212 u16 data = 0;
213 u32 tmp = 0;
214 if (m_has_eeprom) {
215 out32(REG_EEPROM, ((u32)address << 8) | 1);
216 while (!((tmp = in32(REG_EEPROM)) & (1 << 4)))
217 ;
218 } else {
219 out32(REG_EEPROM, ((u32)address << 2) | 1);
220 while (!((tmp = in32(REG_EEPROM)) & (1 << 1)))
221 ;
222 }
223 data = (tmp >> 16) & 0xffff;
224 return data;
225}
226
227void E1000NetworkAdapter::read_mac_address()
228{
229 if (m_has_eeprom) {
230 u8 mac[6];
231 u32 tmp = read_eeprom(0);
232 mac[0] = tmp & 0xff;
233 mac[1] = tmp >> 8;
234 tmp = read_eeprom(1);
235 mac[2] = tmp & 0xff;
236 mac[3] = tmp >> 8;
237 tmp = read_eeprom(2);
238 mac[4] = tmp & 0xff;
239 mac[5] = tmp >> 8;
240 set_mac_address(mac);
241 } else {
242 ASSERT_NOT_REACHED();
243 }
244}
245
246bool E1000NetworkAdapter::link_up()
247{
248 return (in32(REG_STATUS) & STATUS_LU);
249}
250
251void E1000NetworkAdapter::initialize_rx_descriptors()
252{
253 auto ptr = (uintptr_t)kmalloc_eternal(sizeof(e1000_rx_desc) * number_of_rx_descriptors + 16);
254 // Make sure it's 16-byte aligned.
255 if (ptr % 16)
256 ptr = (ptr + 16) - (ptr % 16);
257 m_rx_descriptors = (e1000_rx_desc*)ptr;
258 for (int i = 0; i < number_of_rx_descriptors; ++i) {
259 auto& descriptor = m_rx_descriptors[i];
260 auto addr = (uintptr_t)kmalloc_eternal(8192 + 16);
261 if (addr % 16)
262 addr = (addr + 16) - (addr % 16);
263 descriptor.addr = addr - 0xc0000000;
264 descriptor.status = 0;
265 }
266
267 out32(REG_RXDESCLO, (u32)ptr - 0xc0000000);
268 out32(REG_RXDESCHI, 0);
269 out32(REG_RXDESCLEN, number_of_rx_descriptors * sizeof(e1000_rx_desc));
270 out32(REG_RXDESCHEAD, 0);
271 out32(REG_RXDESCTAIL, number_of_rx_descriptors - 1);
272
273 out32(REG_RCTRL, RCTL_EN | RCTL_SBP | RCTL_UPE | RCTL_MPE | RCTL_LBM_NONE | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_8192);
274}
275
276void E1000NetworkAdapter::initialize_tx_descriptors()
277{
278 auto ptr = (uintptr_t)kmalloc_eternal(sizeof(e1000_tx_desc) * number_of_tx_descriptors + 16);
279 // Make sure it's 16-byte aligned.
280 if (ptr % 16)
281 ptr = (ptr + 16) - (ptr % 16);
282 m_tx_descriptors = (e1000_tx_desc*)ptr;
283 for (int i = 0; i < number_of_tx_descriptors; ++i) {
284 auto& descriptor = m_tx_descriptors[i];
285 auto addr = (uintptr_t)kmalloc_eternal(8192 + 16);
286 if (addr % 16)
287 addr = (addr + 16) - (addr % 16);
288 descriptor.addr = addr - 0xc0000000;
289 descriptor.cmd = 0;
290 }
291
292 out32(REG_TXDESCLO, (u32)ptr - 0xc0000000);
293 out32(REG_TXDESCHI, 0);
294 out32(REG_TXDESCLEN, number_of_tx_descriptors * sizeof(e1000_tx_desc));
295 out32(REG_TXDESCHEAD, 0);
296 out32(REG_TXDESCTAIL, 0);
297
298 out32(REG_TCTRL, in32(REG_TCTRL) | TCTL_EN | TCTL_PSP);
299 out32(REG_TIPG, 0x0060200A);
300}
301
302void E1000NetworkAdapter::out8(u16 address, u8 data)
303{
304#ifdef E1000_DEBUG
305 dbgprintf("E1000: OUT @ 0x%x\n", address);
306#endif
307 if (m_use_mmio) {
308 auto* ptr = (volatile u8*)(m_mmio_base.get() + address);
309 *ptr = data;
310 return;
311 }
312 IO::out8(m_io_base + address, data);
313}
314
315void E1000NetworkAdapter::out16(u16 address, u16 data)
316{
317#ifdef E1000_DEBUG
318 dbgprintf("E1000: OUT @ 0x%x\n", address);
319#endif
320 if (m_use_mmio) {
321 auto* ptr = (volatile u16*)(m_mmio_base.get() + address);
322 *ptr = data;
323 return;
324 }
325 IO::out16(m_io_base + address, data);
326}
327
328void E1000NetworkAdapter::out32(u16 address, u32 data)
329{
330#ifdef E1000_DEBUG
331 dbgprintf("E1000: OUT @ 0x%x\n", address);
332#endif
333 if (m_use_mmio) {
334 auto* ptr = (volatile u32*)(m_mmio_base.get() + address);
335 *ptr = data;
336 return;
337 }
338 IO::out32(m_io_base + address, data);
339}
340
341u8 E1000NetworkAdapter::in8(u16 address)
342{
343#ifdef E1000_DEBUG
344 dbgprintf("E1000: IN @ 0x%x\n", address);
345#endif
346 if (m_use_mmio)
347 return *(volatile u8*)(m_mmio_base.get() + address);
348 return IO::in8(m_io_base + address);
349}
350
351u16 E1000NetworkAdapter::in16(u16 address)
352{
353#ifdef E1000_DEBUG
354 dbgprintf("E1000: IN @ 0x%x\n", address);
355#endif
356 if (m_use_mmio)
357 return *(volatile u16*)(m_mmio_base.get() + address);
358 return IO::in16(m_io_base + address);
359}
360
361u32 E1000NetworkAdapter::in32(u16 address)
362{
363#ifdef E1000_DEBUG
364 dbgprintf("E1000: IN @ 0x%x\n", address);
365#endif
366 if (m_use_mmio)
367 return *(volatile u32*)(m_mmio_base.get() + address);
368 return IO::in32(m_io_base + address);
369}
370
371void E1000NetworkAdapter::send_raw(const u8* data, size_t length)
372{
373 disable_irq();
374 u32 tx_current = in32(REG_TXDESCTAIL);
375#ifdef E1000_DEBUG
376 kprintf("E1000: Sending packet (%zu bytes)\n", length);
377#endif
378 auto& descriptor = m_tx_descriptors[tx_current];
379 ASSERT(length <= 8192);
380 auto* vptr = (void*)(descriptor.addr + 0xc0000000);
381 memcpy(vptr, data, length);
382 descriptor.length = length;
383 descriptor.status = 0;
384 descriptor.cmd = CMD_EOP | CMD_IFCS | CMD_RS;
385#ifdef E1000_DEBUG
386 kprintf("E1000: Using tx descriptor %d (head is at %d)\n", tx_current, in32(REG_TXDESCHEAD));
387#endif
388 tx_current = (tx_current + 1) % number_of_tx_descriptors;
389 out32(REG_TXDESCTAIL, tx_current);
390 cli();
391 enable_irq();
392 for (;;) {
393 if (descriptor.status) {
394 sti();
395 break;
396 }
397 Thread::current->wait_on(m_wait_queue);
398 }
399#ifdef E1000_DEBUG
400 kprintf("E1000: Sent packet, status is now %b!\n", descriptor.status);
401#endif
402}
403
404void E1000NetworkAdapter::receive()
405{
406 u32 rx_current;
407 for (;;) {
408 rx_current = in32(REG_RXDESCTAIL);
409 if (rx_current == in32(REG_RXDESCHEAD))
410 return;
411 rx_current = (rx_current + 1) % number_of_rx_descriptors;
412 if (!(m_rx_descriptors[rx_current].status & 1))
413 break;
414 auto* buffer = (u8*)(m_rx_descriptors[rx_current].addr + 0xc0000000);
415 u16 length = m_rx_descriptors[rx_current].length;
416#ifdef E1000_DEBUG
417 kprintf("E1000: Received 1 packet @ %p (%zu) bytes!\n", buffer, length);
418#endif
419 did_receive(buffer, length);
420 m_rx_descriptors[rx_current].status = 0;
421 out32(REG_RXDESCTAIL, rx_current);
422 }
423}
424
425}