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Serenity Operating System
1/*
2 * Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <AK/Assertions.h>
28#include <AK/Types.h>
29#include <Kernel/Arch/i386/CPU.h>
30#include <Kernel/Interrupts/APIC.h>
31#include <Kernel/VM/MemoryManager.h>
32#include <LibBareMetal/IO.h>
33
34#define IRQ_APIC_SPURIOUS 0x1f
35
36#define APIC_BASE_MSR 0x1b
37
38#define APIC_REG_EOI 0xb0
39#define APIC_REG_LD 0xd0
40#define APIC_REG_DF 0xe0
41#define APIC_REG_SIV 0xf0
42#define APIC_REG_ICR_LOW 0x300
43#define APIC_REG_ICR_HIGH 0x310
44#define APIC_REG_LVT_TIMER 0x320
45#define APIC_REG_LVT_THERMAL 0x330
46#define APIC_REG_LVT_PERFORMANCE_COUNTER 0x340
47#define APIC_REG_LVT_LINT0 0x350
48#define APIC_REG_LVT_LINT1 0x360
49#define APIC_REG_LVT_ERR 0x370
50
51namespace Kernel {
52
53extern "C" void apic_spurious_interrupt_entry();
54
55asm(
56 ".globl apic_spurious_interrupt_entry \n"
57 "apic_spurious_interrupt_entry: \n"
58 " iret\n");
59
60namespace APIC {
61
62 class ICRReg {
63 u32 m_reg { 0 };
64
65 public:
66 enum DeliveryMode {
67 Fixed = 0x0,
68 LowPriority = 0x1,
69 SMI = 0x2,
70 NMI = 0x4,
71 INIT = 0x5,
72 StartUp = 0x6,
73 };
74 enum DestinationMode {
75 Physical = 0x0,
76 Logical = 0x0,
77 };
78 enum Level {
79 DeAssert = 0x0,
80 Assert = 0x1
81 };
82 enum class TriggerMode {
83 Edge = 0x0,
84 Level = 0x1,
85 };
86 enum DestinationShorthand {
87 NoShorthand = 0x0,
88 Self = 0x1,
89 AllIncludingSelf = 0x2,
90 AllExcludingSelf = 0x3,
91 };
92
93 ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destination)
94 : m_reg(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination << 18))
95 {
96 }
97
98 u32 low() const { return m_reg; }
99 u32 high() const { return 0; }
100 };
101
102 static volatile u8* g_apic_base = nullptr;
103
104 static PhysicalAddress get_base()
105 {
106 u32 lo, hi;
107 MSR msr(APIC_BASE_MSR);
108 msr.get(lo, hi);
109 return PhysicalAddress(lo & 0xfffff000);
110 }
111
112 static void set_base(const PhysicalAddress& base)
113 {
114 u32 hi = 0;
115 u32 lo = base.get() | 0x800;
116 MSR msr(APIC_BASE_MSR);
117 msr.set(lo, hi);
118 }
119
120 static void write_register(u32 offset, u32 value)
121 {
122 auto lapic_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)g_apic_base)), PAGE_SIZE, "LAPIC Write Access", Region::Access::Read | Region::Access::Write, false, true);
123 auto* lapic = (u32*)lapic_region->vaddr().offset(offset_in_page((u32)g_apic_base)).offset(offset).as_ptr();
124 *lapic = value;
125 }
126
127 static u32 read_register(u32 offset)
128 {
129 auto lapic_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)g_apic_base)), PAGE_SIZE, "LAPIC Read Access", Region::Access::Read, false, true);
130 auto* lapic = (u32*)lapic_region->vaddr().offset(offset_in_page((u32)g_apic_base)).offset(offset).as_ptr();
131 return *lapic;
132 }
133
134 static void write_icr(const ICRReg& icr)
135 {
136 write_register(APIC_REG_ICR_HIGH, icr.high());
137 write_register(APIC_REG_ICR_LOW, icr.low());
138 }
139
140#define APIC_LVT_MASKED (1 << 16)
141#define APIC_LVT_TRIGGER_LEVEL (1 << 14)
142#define APIC_LVT(iv, dm) ((iv & 0xff) | ((dm & 0x7) << 8))
143
144 asm(
145 ".globl apic_ap_start \n"
146 ".type apic_ap_start, @function \n"
147 "apic_ap_start: \n"
148 ".set begin_apic_ap_start, . \n"
149 " jmp apic_ap_start\n" // TODO: implement
150 ".set end_apic_ap_start, . \n"
151 "\n"
152 ".globl apic_ap_start_size \n"
153 "apic_ap_start_size: \n"
154 ".word end_apic_ap_start - begin_apic_ap_start \n");
155
156 extern "C" void apic_ap_start(void);
157 extern "C" u16 apic_ap_start_size;
158
159 void eoi()
160 {
161 write_register(APIC_REG_EOI, 0x0);
162 }
163
164 bool init()
165 {
166 if (!MSR::have())
167 return false;
168
169 // check if we support local apic
170 CPUID id(1);
171 if ((id.edx() & (1 << 9)) == 0)
172 return false;
173
174 PhysicalAddress apic_base = get_base();
175 kprintf("Initializing APIC, base: P%x\n", apic_base);
176 set_base(apic_base);
177
178 g_apic_base = apic_base.as_ptr();
179
180 return true;
181 }
182
183 void enable_bsp()
184 {
185 // FIXME: Ensure this method can only be executed by the BSP.
186 enable(0);
187 }
188
189 void enable(u32 cpu)
190 {
191 kprintf("Enabling local APIC for cpu #%u\n", cpu);
192
193 // set spurious interrupt vector
194 write_register(APIC_REG_SIV, read_register(APIC_REG_SIV) | 0x100);
195
196 // local destination mode (flat mode)
197 write_register(APIC_REG_DF, 0xf0000000);
198
199 // set destination id (note that this limits it to 8 cpus)
200 write_register(APIC_REG_LD, (1 << cpu) << 24);
201
202 register_interrupt_handler(IRQ_APIC_SPURIOUS, apic_spurious_interrupt_entry);
203
204 write_register(APIC_REG_LVT_TIMER, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
205 write_register(APIC_REG_LVT_THERMAL, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
206 write_register(APIC_REG_LVT_PERFORMANCE_COUNTER, APIC_LVT(0xff, 0) | APIC_LVT_MASKED);
207 write_register(APIC_REG_LVT_LINT0, APIC_LVT(0x1f, 7) | APIC_LVT_MASKED);
208 write_register(APIC_REG_LVT_LINT1, APIC_LVT(0xff, 4) | APIC_LVT_TRIGGER_LEVEL); // nmi
209 write_register(APIC_REG_LVT_ERR, APIC_LVT(0xe3, 0) | APIC_LVT_MASKED);
210
211 if (cpu != 0) {
212 static volatile u32 foo = 0;
213
214 // INIT
215 write_icr(ICRReg(0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf));
216
217 for (foo = 0; foo < 0x800000; foo++)
218 ; // TODO: 10 millisecond delay
219
220 for (int i = 0; i < 2; i++) {
221 // SIPI
222 write_icr(ICRReg(0x08, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf)); // start execution at P8000
223
224 for (foo = 0; foo < 0x80000; foo++)
225 ; // TODO: 200 microsecond delay
226 }
227 }
228 }
229
230}
231
232}