jcs.org
Serenity Operating System
1/*
2 * Copyright (c) 2018-2021, Andreas Kling <kling@serenityos.org>
3 *
4 * SPDX-License-Identifier: BSD-2-Clause
5 */
6
7#include <AK/MACAddress.h>
8#include <Kernel/Bus/PCI/API.h>
9#include <Kernel/Bus/PCI/IDs.h>
10#include <Kernel/Debug.h>
11#include <Kernel/Net/Intel/E1000NetworkAdapter.h>
12#include <Kernel/Net/NetworkingManagement.h>
13#include <Kernel/Sections.h>
14
15namespace Kernel {
16
17#define REG_CTRL 0x0000
18#define REG_STATUS 0x0008
19#define REG_EEPROM 0x0014
20#define REG_CTRL_EXT 0x0018
21#define REG_INTERRUPT_CAUSE_READ 0x00C0
22#define REG_INTERRUPT_RATE 0x00C4
23#define REG_INTERRUPT_MASK_SET 0x00D0
24#define REG_INTERRUPT_MASK_CLEAR 0x00D8
25#define REG_RCTRL 0x0100
26#define REG_RXDESCLO 0x2800
27#define REG_RXDESCHI 0x2804
28#define REG_RXDESCLEN 0x2808
29#define REG_RXDESCHEAD 0x2810
30#define REG_RXDESCTAIL 0x2818
31#define REG_TCTRL 0x0400
32#define REG_TXDESCLO 0x3800
33#define REG_TXDESCHI 0x3804
34#define REG_TXDESCLEN 0x3808
35#define REG_TXDESCHEAD 0x3810
36#define REG_TXDESCTAIL 0x3818
37#define REG_RDTR 0x2820 // RX Delay Timer Register
38#define REG_RXDCTL 0x3828 // RX Descriptor Control
39#define REG_RADV 0x282C // RX Int. Absolute Delay Timer
40#define REG_RSRPD 0x2C00 // RX Small Packet Detect Interrupt
41#define REG_TIPG 0x0410 // Transmit Inter Packet Gap
42#define ECTRL_SLU 0x40 // set link up
43#define RCTL_EN (1 << 1) // Receiver Enable
44#define RCTL_SBP (1 << 2) // Store Bad Packets
45#define RCTL_UPE (1 << 3) // Unicast Promiscuous Enabled
46#define RCTL_MPE (1 << 4) // Multicast Promiscuous Enabled
47#define RCTL_LPE (1 << 5) // Long Packet Reception Enable
48#define RCTL_LBM_NONE (0 << 6) // No Loopback
49#define RCTL_LBM_PHY (3 << 6) // PHY or external SerDesc loopback
50#define RTCL_RDMTS_HALF (0 << 8) // Free Buffer Threshold is 1/2 of RDLEN
51#define RTCL_RDMTS_QUARTER (1 << 8) // Free Buffer Threshold is 1/4 of RDLEN
52#define RTCL_RDMTS_EIGHTH (2 << 8) // Free Buffer Threshold is 1/8 of RDLEN
53#define RCTL_MO_36 (0 << 12) // Multicast Offset - bits 47:36
54#define RCTL_MO_35 (1 << 12) // Multicast Offset - bits 46:35
55#define RCTL_MO_34 (2 << 12) // Multicast Offset - bits 45:34
56#define RCTL_MO_32 (3 << 12) // Multicast Offset - bits 43:32
57#define RCTL_BAM (1 << 15) // Broadcast Accept Mode
58#define RCTL_VFE (1 << 18) // VLAN Filter Enable
59#define RCTL_CFIEN (1 << 19) // Canonical Form Indicator Enable
60#define RCTL_CFI (1 << 20) // Canonical Form Indicator Bit Value
61#define RCTL_DPF (1 << 22) // Discard Pause Frames
62#define RCTL_PMCF (1 << 23) // Pass MAC Control Frames
63#define RCTL_SECRC (1 << 26) // Strip Ethernet CRC
64
65// Buffer Sizes
66#define RCTL_BSIZE_256 (3 << 16)
67#define RCTL_BSIZE_512 (2 << 16)
68#define RCTL_BSIZE_1024 (1 << 16)
69#define RCTL_BSIZE_2048 (0 << 16)
70#define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
71#define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
72#define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
73
74// Transmit Command
75
76#define CMD_EOP (1 << 0) // End of Packet
77#define CMD_IFCS (1 << 1) // Insert FCS
78#define CMD_IC (1 << 2) // Insert Checksum
79#define CMD_RS (1 << 3) // Report Status
80#define CMD_RPS (1 << 4) // Report Packet Sent
81#define CMD_VLE (1 << 6) // VLAN Packet Enable
82#define CMD_IDE (1 << 7) // Interrupt Delay Enable
83
84// TCTL Register
85
86#define TCTL_EN (1 << 1) // Transmit Enable
87#define TCTL_PSP (1 << 3) // Pad Short Packets
88#define TCTL_CT_SHIFT 4 // Collision Threshold
89#define TCTL_COLD_SHIFT 12 // Collision Distance
90#define TCTL_SWXOFF (1 << 22) // Software XOFF Transmission
91#define TCTL_RTLC (1 << 24) // Re-transmit on Late Collision
92
93#define TSTA_DD (1 << 0) // Descriptor Done
94#define TSTA_EC (1 << 1) // Excess Collisions
95#define TSTA_LC (1 << 2) // Late Collision
96#define LSTA_TU (1 << 3) // Transmit Underrun
97
98// STATUS Register
99
100#define STATUS_FD 0x01
101#define STATUS_LU 0x02
102#define STATUS_TXOFF 0x08
103#define STATUS_SPEED 0xC0
104#define STATUS_SPEED_10MB 0x00
105#define STATUS_SPEED_100MB 0x40
106#define STATUS_SPEED_1000MB1 0x80
107#define STATUS_SPEED_1000MB2 0xC0
108
109// Interrupt Masks
110
111#define INTERRUPT_TXDW (1 << 0)
112#define INTERRUPT_TXQE (1 << 1)
113#define INTERRUPT_LSC (1 << 2)
114#define INTERRUPT_RXSEQ (1 << 3)
115#define INTERRUPT_RXDMT0 (1 << 4)
116#define INTERRUPT_RXO (1 << 6)
117#define INTERRUPT_RXT0 (1 << 7)
118#define INTERRUPT_MDAC (1 << 9)
119#define INTERRUPT_RXCFG (1 << 10)
120#define INTERRUPT_PHYINT (1 << 12)
121#define INTERRUPT_TXD_LOW (1 << 15)
122#define INTERRUPT_SRPD (1 << 16)
123
124// https://www.intel.com/content/dam/doc/manual/pci-pci-x-family-gbe-controllers-software-dev-manual.pdf Section 5.2
125UNMAP_AFTER_INIT static bool is_valid_device_id(u16 device_id)
126{
127 // FIXME: It would be nice to distinguish which particular device it is.
128 // Especially since it's needed to determine which registers we can access.
129 // The reason I haven't done it now is because there's some IDs with multiple devices
130 // and some devices with multiple IDs.
131 switch (device_id) {
132 case 0x1019: // 82547EI-A0, 82547EI-A1, 82547EI-B0, 82547GI-B0
133 case 0x101A: // 82547EI-B0
134 case 0x1010: // 82546EB-A1
135 case 0x1012: // 82546EB-A1
136 case 0x101D: // 82546EB-A1
137 case 0x1079: // 82546GB-B0
138 case 0x107A: // 82546GB-B0
139 case 0x107B: // 82546GB-B0
140 case 0x100F: // 82545EM-A
141 case 0x1011: // 82545EM-A
142 case 0x1026: // 82545GM-B
143 case 0x1027: // 82545GM-B
144 case 0x1028: // 82545GM-B
145 case 0x1107: // 82544EI-A4
146 case 0x1112: // 82544GC-A4
147 case 0x1013: // 82541EI-A0, 82541EI-B0
148 case 0x1018: // 82541EI-B0
149 case 0x1076: // 82541GI-B1, 82541PI-C0
150 case 0x1077: // 82541GI-B1
151 case 0x1078: // 82541ER-C0
152 case 0x1017: // 82540EP-A
153 case 0x1016: // 82540EP-A
154 case 0x100E: // 82540EM-A
155 case 0x1015: // 82540EM-A
156 return true;
157 default:
158 return false;
159 }
160}
161
162UNMAP_AFTER_INIT ErrorOr<bool> E1000NetworkAdapter::probe(PCI::DeviceIdentifier const& pci_device_identifier)
163{
164 if (pci_device_identifier.hardware_id().vendor_id != PCI::VendorID::Intel)
165 return false;
166 return is_valid_device_id(pci_device_identifier.hardware_id().device_id);
167}
168
169UNMAP_AFTER_INIT ErrorOr<NonnullLockRefPtr<NetworkAdapter>> E1000NetworkAdapter::create(PCI::DeviceIdentifier const& pci_device_identifier)
170{
171 u8 irq = pci_device_identifier.interrupt_line().value();
172 auto interface_name = TRY(NetworkingManagement::generate_interface_name_from_pci_address(pci_device_identifier));
173 auto registers_io_window = TRY(IOWindow::create_for_pci_device_bar(pci_device_identifier, PCI::HeaderType0BaseRegister::BAR0));
174
175 auto rx_buffer_region = TRY(MM.allocate_contiguous_kernel_region(rx_buffer_size * number_of_rx_descriptors, "E1000 RX buffers"sv, Memory::Region::Access::ReadWrite));
176 auto tx_buffer_region = MM.allocate_contiguous_kernel_region(tx_buffer_size * number_of_tx_descriptors, "E1000 TX buffers"sv, Memory::Region::Access::ReadWrite).release_value();
177 auto rx_descriptors_region = TRY(MM.allocate_contiguous_kernel_region(TRY(Memory::page_round_up(sizeof(e1000_rx_desc) * number_of_rx_descriptors)), "E1000 RX Descriptors"sv, Memory::Region::Access::ReadWrite));
178 auto tx_descriptors_region = TRY(MM.allocate_contiguous_kernel_region(TRY(Memory::page_round_up(sizeof(e1000_tx_desc) * number_of_tx_descriptors)), "E1000 TX Descriptors"sv, Memory::Region::Access::ReadWrite));
179
180 return TRY(adopt_nonnull_lock_ref_or_enomem(new (nothrow) E1000NetworkAdapter(pci_device_identifier,
181 irq, move(registers_io_window),
182 move(rx_buffer_region),
183 move(tx_buffer_region),
184 move(rx_descriptors_region),
185 move(tx_descriptors_region),
186 move(interface_name))));
187}
188
189UNMAP_AFTER_INIT ErrorOr<void> E1000NetworkAdapter::initialize(Badge<NetworkingManagement>)
190{
191 dmesgln_pci(*this, "Found @ {}", device_identifier().address());
192
193 enable_bus_mastering(device_identifier());
194
195 dmesgln_pci(*this, "IO base: {}", m_registers_io_window);
196 dmesgln_pci(*this, "Interrupt line: {}", interrupt_number());
197 detect_eeprom();
198 dmesgln_pci(*this, "Has EEPROM? {}", m_has_eeprom);
199 read_mac_address();
200 auto const& mac = mac_address();
201 dmesgln_pci(*this, "MAC address: {}", mac.to_string());
202
203 initialize_rx_descriptors();
204 initialize_tx_descriptors();
205
206 setup_link();
207 setup_interrupts();
208
209 m_link_up = ((in32(REG_STATUS) & STATUS_LU) != 0);
210
211 return {};
212}
213
214UNMAP_AFTER_INIT void E1000NetworkAdapter::setup_link()
215{
216 u32 flags = in32(REG_CTRL);
217 out32(REG_CTRL, flags | ECTRL_SLU);
218}
219
220UNMAP_AFTER_INIT void E1000NetworkAdapter::setup_interrupts()
221{
222 out32(REG_INTERRUPT_RATE, 6000); // Interrupt rate of 1.536 milliseconds
223 out32(REG_INTERRUPT_MASK_SET, INTERRUPT_LSC | INTERRUPT_RXT0 | INTERRUPT_RXO);
224 in32(REG_INTERRUPT_CAUSE_READ);
225 enable_irq();
226}
227
228UNMAP_AFTER_INIT E1000NetworkAdapter::E1000NetworkAdapter(PCI::DeviceIdentifier const& device_identifier, u8 irq,
229 NonnullOwnPtr<IOWindow> registers_io_window, NonnullOwnPtr<Memory::Region> rx_buffer_region,
230 NonnullOwnPtr<Memory::Region> tx_buffer_region, NonnullOwnPtr<Memory::Region> rx_descriptors_region,
231 NonnullOwnPtr<Memory::Region> tx_descriptors_region, NonnullOwnPtr<KString> interface_name)
232 : NetworkAdapter(move(interface_name))
233 , PCI::Device(device_identifier)
234 , IRQHandler(irq)
235 , m_registers_io_window(move(registers_io_window))
236 , m_rx_descriptors_region(move(rx_descriptors_region))
237 , m_tx_descriptors_region(move(tx_descriptors_region))
238 , m_rx_buffer_region(move(rx_buffer_region))
239 , m_tx_buffer_region(move(tx_buffer_region))
240{
241}
242
243UNMAP_AFTER_INIT E1000NetworkAdapter::~E1000NetworkAdapter() = default;
244
245bool E1000NetworkAdapter::handle_irq(RegisterState const&)
246{
247 u32 status = in32(REG_INTERRUPT_CAUSE_READ);
248
249 m_entropy_source.add_random_event(status);
250
251 if (status == 0)
252 return false;
253
254 if (status & INTERRUPT_LSC) {
255 u32 flags = in32(REG_CTRL);
256 out32(REG_CTRL, flags | ECTRL_SLU);
257
258 m_link_up = ((in32(REG_STATUS) & STATUS_LU) != 0);
259 }
260 if (status & INTERRUPT_RXDMT0) {
261 // Threshold OK?
262 }
263 if (status & INTERRUPT_RXO) {
264 dbgln_if(E1000_DEBUG, "E1000: RX buffer overrun");
265 }
266 if (status & INTERRUPT_RXT0) {
267 receive();
268 }
269
270 m_wait_queue.wake_all();
271
272 out32(REG_INTERRUPT_CAUSE_READ, 0xffffffff);
273 return true;
274}
275
276UNMAP_AFTER_INIT void E1000NetworkAdapter::detect_eeprom()
277{
278 out32(REG_EEPROM, 0x1);
279 for (int i = 0; i < 999; ++i) {
280 u32 data = in32(REG_EEPROM);
281 if (data & 0x10) {
282 m_has_eeprom = true;
283 return;
284 }
285 }
286 m_has_eeprom = false;
287}
288
289UNMAP_AFTER_INIT u32 E1000NetworkAdapter::read_eeprom(u8 address)
290{
291 u16 data = 0;
292 u32 tmp = 0;
293 if (m_has_eeprom) {
294 out32(REG_EEPROM, ((u32)address << 8) | 1);
295 while (!((tmp = in32(REG_EEPROM)) & (1 << 4)))
296 ;
297 } else {
298 out32(REG_EEPROM, ((u32)address << 2) | 1);
299 while (!((tmp = in32(REG_EEPROM)) & (1 << 1)))
300 ;
301 }
302 data = (tmp >> 16) & 0xffff;
303 return data;
304}
305
306UNMAP_AFTER_INIT void E1000NetworkAdapter::read_mac_address()
307{
308 if (m_has_eeprom) {
309 MACAddress mac {};
310 u32 tmp = read_eeprom(0);
311 mac[0] = tmp & 0xff;
312 mac[1] = tmp >> 8;
313 tmp = read_eeprom(1);
314 mac[2] = tmp & 0xff;
315 mac[3] = tmp >> 8;
316 tmp = read_eeprom(2);
317 mac[4] = tmp & 0xff;
318 mac[5] = tmp >> 8;
319 set_mac_address(mac);
320 } else {
321 VERIFY_NOT_REACHED();
322 }
323}
324
325UNMAP_AFTER_INIT void E1000NetworkAdapter::initialize_rx_descriptors()
326{
327 auto* rx_descriptors = (e1000_tx_desc*)m_rx_descriptors_region->vaddr().as_ptr();
328 constexpr auto rx_buffer_page_count = rx_buffer_size / PAGE_SIZE;
329 for (size_t i = 0; i < number_of_rx_descriptors; ++i) {
330 auto& descriptor = rx_descriptors[i];
331 m_rx_buffers[i] = m_rx_buffer_region->vaddr().as_ptr() + rx_buffer_size * i;
332 descriptor.addr = m_rx_buffer_region->physical_page(rx_buffer_page_count * i)->paddr().get();
333 descriptor.status = 0;
334 }
335
336 out32(REG_RXDESCLO, m_rx_descriptors_region->physical_page(0)->paddr().get());
337 out32(REG_RXDESCHI, 0);
338 out32(REG_RXDESCLEN, number_of_rx_descriptors * sizeof(e1000_rx_desc));
339 out32(REG_RXDESCHEAD, 0);
340 out32(REG_RXDESCTAIL, number_of_rx_descriptors - 1);
341
342 out32(REG_RCTRL, RCTL_EN | RCTL_SBP | RCTL_UPE | RCTL_MPE | RCTL_LBM_NONE | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_8192);
343}
344
345UNMAP_AFTER_INIT void E1000NetworkAdapter::initialize_tx_descriptors()
346{
347 auto* tx_descriptors = (e1000_tx_desc*)m_tx_descriptors_region->vaddr().as_ptr();
348 constexpr auto tx_buffer_page_count = tx_buffer_size / PAGE_SIZE;
349
350 for (size_t i = 0; i < number_of_tx_descriptors; ++i) {
351 auto& descriptor = tx_descriptors[i];
352 m_tx_buffers[i] = m_tx_buffer_region->vaddr().as_ptr() + tx_buffer_size * i;
353 descriptor.addr = m_tx_buffer_region->physical_page(tx_buffer_page_count * i)->paddr().get();
354 descriptor.cmd = 0;
355 }
356
357 out32(REG_TXDESCLO, m_tx_descriptors_region->physical_page(0)->paddr().get());
358 out32(REG_TXDESCHI, 0);
359 out32(REG_TXDESCLEN, number_of_tx_descriptors * sizeof(e1000_tx_desc));
360 out32(REG_TXDESCHEAD, 0);
361 out32(REG_TXDESCTAIL, 0);
362
363 out32(REG_TCTRL, in32(REG_TCTRL) | TCTL_EN | TCTL_PSP);
364 out32(REG_TIPG, 0x0060200A);
365}
366
367void E1000NetworkAdapter::out8(u16 address, u8 data)
368{
369 dbgln_if(E1000_DEBUG, "E1000: OUT8 {:#02x} @ {:#04x}", data, address);
370 m_registers_io_window->write8(address, data);
371}
372
373void E1000NetworkAdapter::out16(u16 address, u16 data)
374{
375 dbgln_if(E1000_DEBUG, "E1000: OUT16 {:#04x} @ {:#04x}", data, address);
376 m_registers_io_window->write16(address, data);
377}
378
379void E1000NetworkAdapter::out32(u16 address, u32 data)
380{
381 dbgln_if(E1000_DEBUG, "E1000: OUT32 {:#08x} @ {:#04x}", data, address);
382 m_registers_io_window->write32(address, data);
383}
384
385u8 E1000NetworkAdapter::in8(u16 address)
386{
387 dbgln_if(E1000_DEBUG, "E1000: IN8 @ {:#04x}", address);
388 return m_registers_io_window->read8(address);
389}
390
391u16 E1000NetworkAdapter::in16(u16 address)
392{
393 dbgln_if(E1000_DEBUG, "E1000: IN16 @ {:#04x}", address);
394 return m_registers_io_window->read16(address);
395}
396
397u32 E1000NetworkAdapter::in32(u16 address)
398{
399 dbgln_if(E1000_DEBUG, "E1000: IN32 @ {:#04x}", address);
400 return m_registers_io_window->read32(address);
401}
402
403void E1000NetworkAdapter::send_raw(ReadonlyBytes payload)
404{
405 disable_irq();
406 size_t tx_current = in32(REG_TXDESCTAIL) % number_of_tx_descriptors;
407 dbgln_if(E1000_DEBUG, "E1000: Sending packet ({} bytes)", payload.size());
408 auto* tx_descriptors = (e1000_tx_desc*)m_tx_descriptors_region->vaddr().as_ptr();
409 auto& descriptor = tx_descriptors[tx_current];
410 VERIFY(payload.size() <= 8192);
411 auto* vptr = (void*)m_tx_buffers[tx_current];
412 memcpy(vptr, payload.data(), payload.size());
413 descriptor.length = payload.size();
414 descriptor.status = 0;
415 descriptor.cmd = CMD_EOP | CMD_IFCS | CMD_RS;
416 dbgln_if(E1000_DEBUG, "E1000: Using tx descriptor {} (head is at {})", tx_current, in32(REG_TXDESCHEAD));
417 tx_current = (tx_current + 1) % number_of_tx_descriptors;
418 Processor::disable_interrupts();
419 enable_irq();
420 out32(REG_TXDESCTAIL, tx_current);
421 for (;;) {
422 if (descriptor.status) {
423 Processor::enable_interrupts();
424 break;
425 }
426 m_wait_queue.wait_forever("E1000NetworkAdapter"sv);
427 }
428 dbgln_if(E1000_DEBUG, "E1000: Sent packet, status is now {:#02x}!", (u8)descriptor.status);
429}
430
431void E1000NetworkAdapter::receive()
432{
433 auto* rx_descriptors = (e1000_tx_desc*)m_rx_descriptors_region->vaddr().as_ptr();
434 u32 rx_current;
435 for (;;) {
436 rx_current = in32(REG_RXDESCTAIL) % number_of_rx_descriptors;
437 rx_current = (rx_current + 1) % number_of_rx_descriptors;
438 if (!(rx_descriptors[rx_current].status & 1))
439 break;
440 auto* buffer = m_rx_buffers[rx_current];
441 u16 length = rx_descriptors[rx_current].length;
442 VERIFY(length <= 8192);
443 dbgln_if(E1000_DEBUG, "E1000: Received 1 packet @ {:p} ({} bytes)", buffer, length);
444 did_receive({ buffer, length });
445 rx_descriptors[rx_current].status = 0;
446 out32(REG_RXDESCTAIL, rx_current);
447 }
448}
449
450i32 E1000NetworkAdapter::link_speed()
451{
452 if (!link_up())
453 return NetworkAdapter::LINKSPEED_INVALID;
454
455 u32 speed = in32(REG_STATUS) & STATUS_SPEED;
456 switch (speed) {
457 case STATUS_SPEED_10MB:
458 return 10;
459 case STATUS_SPEED_100MB:
460 return 100;
461 case STATUS_SPEED_1000MB1:
462 case STATUS_SPEED_1000MB2:
463 return 1000;
464 default:
465 return NetworkAdapter::LINKSPEED_INVALID;
466 }
467}
468
469bool E1000NetworkAdapter::link_full_duplex()
470{
471 u32 status = in32(REG_STATUS);
472 return !!(status & STATUS_FD);
473}
474
475}