jcs.org
Serenity Operating System
1/*
2 * Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
3 *
4 * SPDX-License-Identifier: BSD-2-Clause
5 */
6
7#pragma once
8
9#include <AK/RefPtr.h>
10#include <AK/Try.h>
11#include <AK/Types.h>
12#include <Kernel/Graphics/Intel/Transcoder/DisplayTranscoder.h>
13
14namespace Kernel {
15
16class IntelDisplayConnectorGroup;
17class IntelAnalogDisplayTranscoder final : public IntelDisplayTranscoder {
18public:
19 static ErrorOr<NonnullOwnPtr<IntelAnalogDisplayTranscoder>> create_with_physical_addresses(PhysicalAddress transcoder_registers_start_address,
20 PhysicalAddress pipe_registers_start_address, PhysicalAddress dpll_registers_start_address, PhysicalAddress dpll_control_registers_start_address);
21
22 virtual ErrorOr<void> set_dpll_settings(Badge<IntelDisplayConnectorGroup>, IntelGraphics::PLLSettings const& settings, size_t dac_multiplier) override;
23 virtual ErrorOr<void> enable_dpll_without_vga(Badge<IntelDisplayConnectorGroup>) override;
24 virtual ErrorOr<void> disable_dpll(Badge<IntelDisplayConnectorGroup>) override;
25
26private:
27 struct [[gnu::packed]] DPLLRegisters {
28 u32 divisor_a0;
29 u32 divisor_a1;
30 };
31
32 struct [[gnu::packed]] DPLLControlRegisters {
33 u32 control;
34 u32 padding; // On Gen4, this is the control register of DPLL B, don't touch this
35 u32 multiplier;
36 };
37
38 IntelAnalogDisplayTranscoder(Memory::TypedMapping<TranscoderRegisters volatile>, Memory::TypedMapping<PipeRegisters volatile>, Memory::TypedMapping<DPLLRegisters volatile>, Memory::TypedMapping<DPLLControlRegisters volatile>);
39 Memory::TypedMapping<DPLLRegisters volatile> m_dpll_registers;
40 Memory::TypedMapping<DPLLControlRegisters volatile> m_dpll_control_registers;
41};
42}