jcs.org
Serenity Operating System
1/*
2 * Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
3 *
4 * SPDX-License-Identifier: BSD-2-Clause
5 */
6
7#include <Kernel/Graphics/Intel/Plane/G33DisplayPlane.h>
8#include <Kernel/PhysicalAddress.h>
9
10namespace Kernel {
11
12ErrorOr<NonnullOwnPtr<IntelG33DisplayPlane>> IntelG33DisplayPlane::create_with_physical_address(PhysicalAddress plane_registers_start_address)
13{
14 auto registers_mapping = TRY(Memory::map_typed<PlaneRegisters volatile>(plane_registers_start_address, sizeof(PlaneRegisters), Memory::Region::Access::ReadWrite));
15 return adopt_nonnull_own_or_enomem(new (nothrow) IntelG33DisplayPlane(move(registers_mapping)));
16}
17
18IntelG33DisplayPlane::IntelG33DisplayPlane(Memory::TypedMapping<PlaneRegisters volatile> registers_mapping)
19 : IntelDisplayPlane(move(registers_mapping))
20{
21}
22
23ErrorOr<void> IntelG33DisplayPlane::enable(Badge<IntelDisplayConnectorGroup>)
24{
25 SpinlockLocker locker(m_access_lock);
26 VERIFY(((m_horizontal_active_pixels_count * 4) % 64 == 0));
27 VERIFY(((m_horizontal_stride) % 64 == 0));
28
29 u32 control_value = 0;
30
31 switch (m_pipe_select) {
32 case PipeSelect::PipeA:
33 control_value |= (0b00 << 24);
34 break;
35 case PipeSelect::PipeB:
36 control_value |= (0b01 << 24);
37 break;
38 case PipeSelect::PipeC:
39 control_value |= (0b10 << 24);
40 break;
41 case PipeSelect::PipeD:
42 control_value |= (0b11 << 24);
43 break;
44 }
45
46 // Note: Set the plane to work with 32 bit BGRX (Ignore Alpha channel).
47 // Note: Bit 31 is set to turn on the plane.
48 control_value |= (0b0110 << 26) | (1 << 31);
49
50 m_plane_registers->stride = m_horizontal_stride;
51 m_shadow_registers.stride = m_horizontal_stride;
52 m_plane_registers->linear_offset = 0;
53 m_shadow_registers.linear_offset = 0;
54 m_plane_registers->surface_base = m_aperture_start.get();
55 m_shadow_registers.surface_base = m_aperture_start.get();
56 m_plane_registers->control = control_value;
57 m_shadow_registers.control = control_value;
58 return {};
59}
60}