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Serenity Operating System
1/*
2 * Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#pragma once
28
29#include <AK/Function.h>
30#include <AK/LogStream.h>
31#include <AK/Types.h>
32
33namespace Kernel {
34
35#define PCI_VENDOR_ID 0x00 // word
36#define PCI_DEVICE_ID 0x02 // word
37#define PCI_COMMAND 0x04 // word
38#define PCI_STATUS 0x06 // word
39#define PCI_REVISION_ID 0x08 // byte
40#define PCI_PROG_IF 0x09 // byte
41#define PCI_SUBCLASS 0x0a // byte
42#define PCI_CLASS 0x0b // byte
43#define PCI_CACHE_LINE_SIZE 0x0c // byte
44#define PCI_LATENCY_TIMER 0x0d // byte
45#define PCI_HEADER_TYPE 0x0e // byte
46#define PCI_BIST 0x0f // byte
47#define PCI_BAR0 0x10 // u32
48#define PCI_BAR1 0x14 // u32
49#define PCI_BAR2 0x18 // u32
50#define PCI_BAR3 0x1C // u32
51#define PCI_BAR4 0x20 // u32
52#define PCI_BAR5 0x24 // u32
53#define PCI_SUBSYSTEM_ID 0x2C // u16
54#define PCI_SUBSYSTEM_VENDOR_ID 0x2E // u16
55#define PCI_CAPABILITIES_POINTER 0x34 // u8
56#define PCI_INTERRUPT_LINE 0x3C // byte
57#define PCI_SECONDARY_BUS 0x19 // byte
58#define PCI_HEADER_TYPE_DEVICE 0
59#define PCI_HEADER_TYPE_BRIDGE 1
60#define PCI_TYPE_BRIDGE 0x0604
61#define PCI_ADDRESS_PORT 0xCF8
62#define PCI_VALUE_PORT 0xCFC
63#define PCI_NONE 0xFFFF
64#define PCI_MAX_DEVICES_PER_BUS 32
65#define PCI_MAX_BUSES 256
66#define PCI_MAX_FUNCTIONS_PER_DEVICE 8
67
68//#define PCI_DEBUG 1
69
70namespace PCI {
71struct ID {
72 u16 vendor_id { 0 };
73 u16 device_id { 0 };
74
75 bool is_null() const { return !vendor_id && !device_id; }
76
77 bool operator==(const ID& other) const
78 {
79 return vendor_id == other.vendor_id && device_id == other.device_id;
80 }
81 bool operator!=(const ID& other) const
82 {
83 return vendor_id != other.vendor_id || device_id != other.device_id;
84 }
85};
86inline const LogStream& operator<<(const LogStream& stream, const ID value)
87{
88 return stream << "(" << String::format("%w", value.vendor_id) << ":" << String::format("%w", value.device_id) << ")";
89}
90struct Address {
91public:
92 Address() {}
93 Address(u16 seg)
94 : m_seg(seg)
95 , m_bus(0)
96 , m_slot(0)
97 , m_function(0)
98 {
99 }
100 Address(u16 seg, u8 bus, u8 slot, u8 function)
101 : m_seg(seg)
102 , m_bus(bus)
103 , m_slot(slot)
104 , m_function(function)
105 {
106 }
107
108 Address(const Address& address)
109 : m_seg(address.seg())
110 , m_bus(address.bus())
111 , m_slot(address.slot())
112 , m_function(address.function())
113 {
114 }
115
116 bool is_null() const { return !m_bus && !m_slot && !m_function; }
117 operator bool() const { return !is_null(); }
118
119 u16 seg() const { return m_seg; }
120 u8 bus() const { return m_bus; }
121 u8 slot() const { return m_slot; }
122 u8 function() const { return m_function; }
123
124 u32 io_address_for_field(u8 field) const
125 {
126 return 0x80000000u | (m_bus << 16u) | (m_slot << 11u) | (m_function << 8u) | (field & 0xfc);
127 }
128
129protected:
130 u32 m_seg { 0 };
131 u8 m_bus { 0 };
132 u8 m_slot { 0 };
133 u8 m_function { 0 };
134};
135
136inline const LogStream& operator<<(const LogStream& stream, const Address value)
137{
138 return stream << "PCI [" << String::format("%w", value.seg()) << ":" << String::format("%b", value.bus()) << ":" << String::format("%b", value.slot()) << "." << String::format("%b", value.function()) << "]";
139}
140
141struct ChangeableAddress : public Address {
142 ChangeableAddress()
143 : Address(0)
144 {
145 }
146 explicit ChangeableAddress(u16 seg)
147 : Address(seg)
148 {
149 }
150 ChangeableAddress(u16 seg, u8 bus, u8 slot, u8 function)
151 : Address(seg, bus, slot, function)
152 {
153 }
154 void set_seg(u16 seg) { m_seg = seg; }
155 void set_bus(u8 bus) { m_bus = bus; }
156 void set_slot(u8 slot) { m_slot = slot; }
157 void set_function(u8 function) { m_function = function; }
158 bool operator==(const Address& address)
159 {
160 if (m_seg == address.seg() && m_bus == address.bus() && m_slot == address.slot() && m_function == address.function())
161 return true;
162 else
163 return false;
164 }
165 const ChangeableAddress& operator=(const Address& address)
166 {
167 set_seg(address.seg());
168 set_bus(address.bus());
169 set_slot(address.slot());
170 set_function(address.function());
171 return *this;
172 }
173};
174
175ID get_id(PCI::Address);
176void enumerate_all(Function<void(Address, ID)> callback);
177void enable_interrupt_line(Address);
178void disable_interrupt_line(Address);
179u8 get_interrupt_line(Address);
180void raw_access(Address, u32, size_t, u32);
181u32 get_BAR0(Address);
182u32 get_BAR1(Address);
183u32 get_BAR2(Address);
184u32 get_BAR3(Address);
185u32 get_BAR4(Address);
186u32 get_BAR5(Address);
187u8 get_revision_id(Address);
188u8 get_subclass(Address);
189u8 get_class(Address);
190u16 get_subsystem_id(Address);
191u16 get_subsystem_vendor_id(Address);
192size_t get_BAR_space_size(Address, u8);
193void enable_bus_mastering(Address);
194void disable_bus_mastering(Address);
195
196class Access;
197class MMIOAccess;
198class IOAccess;
199class MMIOSegment;
200class Device;
201
202}
203
204}