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Serenity Operating System
1/*
2 * Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <Kernel/Net/E1000NetworkAdapter.h>
28#include <Kernel/Thread.h>
29#include <LibBareMetal/IO.h>
30
31//#define E1000_DEBUG
32
33namespace Kernel {
34
35#define REG_CTRL 0x0000
36#define REG_STATUS 0x0008
37#define REG_EEPROM 0x0014
38#define REG_CTRL_EXT 0x0018
39#define REG_INTERRUPT_CAUSE_READ 0x00C0
40#define REG_INTERRUPT_RATE 0x00C4
41#define REG_INTERRUPT_MASK_SET 0x00D0
42#define REG_INTERRUPT_MASK_CLEAR 0x00D8
43#define REG_RCTRL 0x0100
44#define REG_RXDESCLO 0x2800
45#define REG_RXDESCHI 0x2804
46#define REG_RXDESCLEN 0x2808
47#define REG_RXDESCHEAD 0x2810
48#define REG_RXDESCTAIL 0x2818
49#define REG_TCTRL 0x0400
50#define REG_TXDESCLO 0x3800
51#define REG_TXDESCHI 0x3804
52#define REG_TXDESCLEN 0x3808
53#define REG_TXDESCHEAD 0x3810
54#define REG_TXDESCTAIL 0x3818
55#define REG_RDTR 0x2820 // RX Delay Timer Register
56#define REG_RXDCTL 0x3828 // RX Descriptor Control
57#define REG_RADV 0x282C // RX Int. Absolute Delay Timer
58#define REG_RSRPD 0x2C00 // RX Small Packet Detect Interrupt
59#define REG_TIPG 0x0410 // Transmit Inter Packet Gap
60#define ECTRL_SLU 0x40 //set link up
61#define RCTL_EN (1 << 1) // Receiver Enable
62#define RCTL_SBP (1 << 2) // Store Bad Packets
63#define RCTL_UPE (1 << 3) // Unicast Promiscuous Enabled
64#define RCTL_MPE (1 << 4) // Multicast Promiscuous Enabled
65#define RCTL_LPE (1 << 5) // Long Packet Reception Enable
66#define RCTL_LBM_NONE (0 << 6) // No Loopback
67#define RCTL_LBM_PHY (3 << 6) // PHY or external SerDesc loopback
68#define RTCL_RDMTS_HALF (0 << 8) // Free Buffer Threshold is 1/2 of RDLEN
69#define RTCL_RDMTS_QUARTER (1 << 8) // Free Buffer Threshold is 1/4 of RDLEN
70#define RTCL_RDMTS_EIGHTH (2 << 8) // Free Buffer Threshold is 1/8 of RDLEN
71#define RCTL_MO_36 (0 << 12) // Multicast Offset - bits 47:36
72#define RCTL_MO_35 (1 << 12) // Multicast Offset - bits 46:35
73#define RCTL_MO_34 (2 << 12) // Multicast Offset - bits 45:34
74#define RCTL_MO_32 (3 << 12) // Multicast Offset - bits 43:32
75#define RCTL_BAM (1 << 15) // Broadcast Accept Mode
76#define RCTL_VFE (1 << 18) // VLAN Filter Enable
77#define RCTL_CFIEN (1 << 19) // Canonical Form Indicator Enable
78#define RCTL_CFI (1 << 20) // Canonical Form Indicator Bit Value
79#define RCTL_DPF (1 << 22) // Discard Pause Frames
80#define RCTL_PMCF (1 << 23) // Pass MAC Control Frames
81#define RCTL_SECRC (1 << 26) // Strip Ethernet CRC
82
83// Buffer Sizes
84#define RCTL_BSIZE_256 (3 << 16)
85#define RCTL_BSIZE_512 (2 << 16)
86#define RCTL_BSIZE_1024 (1 << 16)
87#define RCTL_BSIZE_2048 (0 << 16)
88#define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
89#define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
90#define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
91
92// Transmit Command
93
94#define CMD_EOP (1 << 0) // End of Packet
95#define CMD_IFCS (1 << 1) // Insert FCS
96#define CMD_IC (1 << 2) // Insert Checksum
97#define CMD_RS (1 << 3) // Report Status
98#define CMD_RPS (1 << 4) // Report Packet Sent
99#define CMD_VLE (1 << 6) // VLAN Packet Enable
100#define CMD_IDE (1 << 7) // Interrupt Delay Enable
101
102// TCTL Register
103
104#define TCTL_EN (1 << 1) // Transmit Enable
105#define TCTL_PSP (1 << 3) // Pad Short Packets
106#define TCTL_CT_SHIFT 4 // Collision Threshold
107#define TCTL_COLD_SHIFT 12 // Collision Distance
108#define TCTL_SWXOFF (1 << 22) // Software XOFF Transmission
109#define TCTL_RTLC (1 << 24) // Re-transmit on Late Collision
110
111#define TSTA_DD (1 << 0) // Descriptor Done
112#define TSTA_EC (1 << 1) // Excess Collisions
113#define TSTA_LC (1 << 2) // Late Collision
114#define LSTA_TU (1 << 3) // Transmit Underrun
115
116// STATUS Register
117
118#define STATUS_FD 0x01
119#define STATUS_LU 0x02
120#define STATUS_TXOFF 0x08
121#define STATUS_SPEED 0xC0
122#define STATUS_SPEED_10MB 0x00
123#define STATUS_SPEED_100MB 0x40
124#define STATUS_SPEED_1000MB1 0x80
125#define STATUS_SPEED_1000MB2 0xC0
126
127// Interrupt Masks
128
129#define INTERRUPT_TXDW (1 << 0)
130#define INTERRUPT_TXQE (1 << 1)
131#define INTERRUPT_LSC (1 << 2)
132#define INTERRUPT_RXSEQ (1 << 3)
133#define INTERRUPT_RXDMT0 (1 << 4)
134#define INTERRUPT_RXO (1 << 6)
135#define INTERRUPT_RXT0 (1 << 7)
136#define INTERRUPT_MDAC (1 << 9)
137#define INTERRUPT_RXCFG (1 << 10)
138#define INTERRUPT_PHYINT (1 << 12)
139#define INTERRUPT_TXD_LOW (1 << 15)
140#define INTERRUPT_SRPD (1 << 16)
141
142void E1000NetworkAdapter::detect(const PCI::Address& address)
143{
144 if (address.is_null())
145 return;
146 static const PCI::ID qemu_bochs_vbox_id = { 0x8086, 0x100e };
147 const PCI::ID id = PCI::get_id(address);
148 if (id != qemu_bochs_vbox_id)
149 return;
150 u8 irq = PCI::get_interrupt_line(address);
151 (void)adopt(*new E1000NetworkAdapter(address, irq)).leak_ref();
152}
153
154E1000NetworkAdapter::E1000NetworkAdapter(PCI::Address address, u8 irq)
155 : PCI::Device(address, irq)
156 , m_io_base(PCI::get_BAR1(pci_address()) & ~1)
157 , m_rx_descriptors_region(MM.allocate_contiguous_kernel_region(PAGE_ROUND_UP(sizeof(e1000_rx_desc) * number_of_rx_descriptors + 16), "E1000 RX", Region::Access::Read | Region::Access::Write))
158 , m_tx_descriptors_region(MM.allocate_contiguous_kernel_region(PAGE_ROUND_UP(sizeof(e1000_tx_desc) * number_of_tx_descriptors + 16), "E1000 TX", Region::Access::Read | Region::Access::Write))
159{
160 set_interface_name("e1k");
161
162 klog() << "E1000: Found @ " << pci_address();
163
164 enable_bus_mastering(pci_address());
165
166 size_t mmio_base_size = PCI::get_BAR_space_size(pci_address(), 0);
167 m_mmio_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of(PCI::get_BAR0(pci_address()))), PAGE_ROUND_UP(mmio_base_size), "E1000 MMIO", Region::Access::Read | Region::Access::Write, false, false);
168 m_mmio_base = m_mmio_region->vaddr();
169 m_use_mmio = true;
170 m_interrupt_line = PCI::get_interrupt_line(pci_address());
171 klog() << "E1000: port base: " << m_io_base;
172 klog() << "E1000: MMIO base: " << PhysicalAddress(PCI::get_BAR0(pci_address()) & 0xfffffffc);
173 klog() << "E1000: MMIO base size: " << mmio_base_size << " bytes";
174 klog() << "E1000: Interrupt line: " << m_interrupt_line;
175 detect_eeprom();
176 klog() << "E1000: Has EEPROM? " << m_has_eeprom;
177 read_mac_address();
178 const auto& mac = mac_address();
179 klog() << "E1000: MAC address: " << String::format("%b", mac[0]) << ":" << String::format("%b", mac[1]) << ":" << String::format("%b", mac[2]) << ":" << String::format("%b", mac[3]) << ":" << String::format("%b", mac[4]) << ":" << String::format("%b", mac[5]);
180
181 u32 flags = in32(REG_CTRL);
182 out32(REG_CTRL, flags | ECTRL_SLU);
183
184 out16(REG_INTERRUPT_RATE, 6000); // Interrupt rate of 1.536 milliseconds
185
186 initialize_rx_descriptors();
187 initialize_tx_descriptors();
188
189 out32(REG_INTERRUPT_MASK_SET, 0x1f6dc);
190 out32(REG_INTERRUPT_MASK_SET, INTERRUPT_LSC | INTERRUPT_RXT0);
191 in32(REG_INTERRUPT_CAUSE_READ);
192
193 enable_irq();
194}
195
196E1000NetworkAdapter::~E1000NetworkAdapter()
197{
198}
199
200void E1000NetworkAdapter::handle_irq(const RegisterState&)
201{
202 out32(REG_INTERRUPT_MASK_CLEAR, 0xffffffff);
203
204 u32 status = in32(REG_INTERRUPT_CAUSE_READ);
205 if (status & 4) {
206 u32 flags = in32(REG_CTRL);
207 out32(REG_CTRL, flags | ECTRL_SLU);
208 }
209 if (status & 0x80) {
210 receive();
211 }
212 if (status & 0x10) {
213 // Threshold OK?
214 }
215
216 m_wait_queue.wake_all();
217
218 out32(REG_INTERRUPT_MASK_SET, INTERRUPT_LSC | INTERRUPT_RXT0 | INTERRUPT_RXO);
219}
220
221void E1000NetworkAdapter::detect_eeprom()
222{
223 out32(REG_EEPROM, 0x1);
224 for (volatile int i = 0; i < 999; ++i) {
225 u32 data = in32(REG_EEPROM);
226 if (data & 0x10) {
227 m_has_eeprom = true;
228 return;
229 }
230 }
231 m_has_eeprom = false;
232}
233
234u32 E1000NetworkAdapter::read_eeprom(u8 address)
235{
236 u16 data = 0;
237 u32 tmp = 0;
238 if (m_has_eeprom) {
239 out32(REG_EEPROM, ((u32)address << 8) | 1);
240 while (!((tmp = in32(REG_EEPROM)) & (1 << 4)))
241 ;
242 } else {
243 out32(REG_EEPROM, ((u32)address << 2) | 1);
244 while (!((tmp = in32(REG_EEPROM)) & (1 << 1)))
245 ;
246 }
247 data = (tmp >> 16) & 0xffff;
248 return data;
249}
250
251void E1000NetworkAdapter::read_mac_address()
252{
253 if (m_has_eeprom) {
254 u8 mac[6];
255 u32 tmp = read_eeprom(0);
256 mac[0] = tmp & 0xff;
257 mac[1] = tmp >> 8;
258 tmp = read_eeprom(1);
259 mac[2] = tmp & 0xff;
260 mac[3] = tmp >> 8;
261 tmp = read_eeprom(2);
262 mac[4] = tmp & 0xff;
263 mac[5] = tmp >> 8;
264 set_mac_address(mac);
265 } else {
266 ASSERT_NOT_REACHED();
267 }
268}
269
270bool E1000NetworkAdapter::link_up()
271{
272 return (in32(REG_STATUS) & STATUS_LU);
273}
274
275void E1000NetworkAdapter::initialize_rx_descriptors()
276{
277 auto* rx_descriptors = (e1000_tx_desc*)m_rx_descriptors_region->vaddr().as_ptr();
278 for (int i = 0; i < number_of_rx_descriptors; ++i) {
279 auto& descriptor = rx_descriptors[i];
280 m_rx_buffers_regions.append(MM.allocate_contiguous_kernel_region(PAGE_ROUND_UP(8192), "E1000 RX buffer", Region::Access::Read | Region::Access::Write));
281 descriptor.addr = m_rx_buffers_regions[i]->vmobject().physical_pages()[0]->paddr().get();
282 descriptor.status = 0;
283 }
284
285 out32(REG_RXDESCLO, m_rx_descriptors_region->vmobject().physical_pages()[0]->paddr().get());
286 out32(REG_RXDESCHI, 0);
287 out32(REG_RXDESCLEN, number_of_rx_descriptors * sizeof(e1000_rx_desc));
288 out32(REG_RXDESCHEAD, 0);
289 out32(REG_RXDESCTAIL, number_of_rx_descriptors - 1);
290
291 out32(REG_RCTRL, RCTL_EN | RCTL_SBP | RCTL_UPE | RCTL_MPE | RCTL_LBM_NONE | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_8192);
292}
293
294void E1000NetworkAdapter::initialize_tx_descriptors()
295{
296 auto* tx_descriptors = (e1000_tx_desc*)m_tx_descriptors_region->vaddr().as_ptr();
297 for (int i = 0; i < number_of_tx_descriptors; ++i) {
298 auto& descriptor = tx_descriptors[i];
299 m_tx_buffers_regions.append(MM.allocate_contiguous_kernel_region(PAGE_ROUND_UP(8192), "E1000 TX buffer", Region::Access::Read | Region::Access::Write));
300 descriptor.addr = m_tx_buffers_regions[i]->vmobject().physical_pages()[0]->paddr().get();
301 descriptor.cmd = 0;
302 }
303
304 out32(REG_TXDESCLO, m_tx_descriptors_region->vmobject().physical_pages()[0]->paddr().get());
305 out32(REG_TXDESCHI, 0);
306 out32(REG_TXDESCLEN, number_of_tx_descriptors * sizeof(e1000_tx_desc));
307 out32(REG_TXDESCHEAD, 0);
308 out32(REG_TXDESCTAIL, 0);
309
310 out32(REG_TCTRL, in32(REG_TCTRL) | TCTL_EN | TCTL_PSP);
311 out32(REG_TIPG, 0x0060200A);
312}
313
314void E1000NetworkAdapter::out8(u16 address, u8 data)
315{
316#ifdef E1000_DEBUG
317 dbg() << "E1000: OUT @ 0x" << address;
318#endif
319 if (m_use_mmio) {
320 auto* ptr = (volatile u8*)(m_mmio_base.get() + address);
321 *ptr = data;
322 return;
323 }
324 m_io_base.offset(address).out(data);
325}
326
327void E1000NetworkAdapter::out16(u16 address, u16 data)
328{
329#ifdef E1000_DEBUG
330 dbg() << "E1000: OUT @ 0x" << address;
331#endif
332 if (m_use_mmio) {
333 auto* ptr = (volatile u16*)(m_mmio_base.get() + address);
334 *ptr = data;
335 return;
336 }
337 m_io_base.offset(address).out(data);
338}
339
340void E1000NetworkAdapter::out32(u16 address, u32 data)
341{
342#ifdef E1000_DEBUG
343 dbg() << "E1000: OUT @ 0x" << address;
344#endif
345 if (m_use_mmio) {
346 auto* ptr = (volatile u32*)(m_mmio_base.get() + address);
347 *ptr = data;
348 return;
349 }
350 m_io_base.offset(address).out(data);
351}
352
353u8 E1000NetworkAdapter::in8(u16 address)
354{
355#ifdef E1000_DEBUG
356 dbg() << "E1000: IN @ 0x" << address;
357#endif
358 if (m_use_mmio)
359 return *(volatile u8*)(m_mmio_base.get() + address);
360 return m_io_base.offset(address).in<u8>();
361}
362
363u16 E1000NetworkAdapter::in16(u16 address)
364{
365#ifdef E1000_DEBUG
366 dbg() << "E1000: IN @ 0x " << address;
367#endif
368 if (m_use_mmio)
369 return *(volatile u16*)(m_mmio_base.get() + address);
370 return m_io_base.offset(address).in<u16>();
371}
372
373u32 E1000NetworkAdapter::in32(u16 address)
374{
375#ifdef E1000_DEBUG
376 dbg() << "E1000: IN @ 0x" << address;
377#endif
378 if (m_use_mmio)
379 return *(volatile u32*)(m_mmio_base.get() + address);
380 return m_io_base.offset(address).in<u32>();
381}
382
383void E1000NetworkAdapter::send_raw(const u8* data, size_t length)
384{
385 disable_irq();
386 u32 tx_current = in32(REG_TXDESCTAIL);
387#ifdef E1000_DEBUG
388 klog() << "E1000: Sending packet (" << length << " bytes)";
389#endif
390 auto* tx_descriptors = (e1000_tx_desc*)m_tx_descriptors_region->vaddr().as_ptr();
391 auto& descriptor = tx_descriptors[tx_current];
392 ASSERT(length <= 8192);
393 auto* vptr = (void*)m_tx_buffers_regions[tx_current]->vaddr().as_ptr();
394 memcpy(vptr, data, length);
395 descriptor.length = length;
396 descriptor.status = 0;
397 descriptor.cmd = CMD_EOP | CMD_IFCS | CMD_RS;
398#ifdef E1000_DEBUG
399 klog() << "E1000: Using tx descriptor " << tx_current << " (head is at " << in32(REG_TXDESCHEAD) << ")";
400#endif
401 tx_current = (tx_current + 1) % number_of_tx_descriptors;
402 cli();
403 enable_irq();
404 out32(REG_TXDESCTAIL, tx_current);
405 for (;;) {
406 if (descriptor.status) {
407 sti();
408 break;
409 }
410 Thread::current->wait_on(m_wait_queue);
411 }
412#ifdef E1000_DEBUG
413 klog() << "E1000: Sent packet, status is now " << String::format("%b", descriptor.status) << "!";
414#endif
415}
416
417void E1000NetworkAdapter::receive()
418{
419 auto* rx_descriptors = (e1000_tx_desc*)m_rx_descriptors_region->vaddr().as_ptr();
420 u32 rx_current;
421 for (;;) {
422 rx_current = in32(REG_RXDESCTAIL);
423 if (rx_current == in32(REG_RXDESCHEAD))
424 return;
425 rx_current = (rx_current + 1) % number_of_rx_descriptors;
426 if (!(rx_descriptors[rx_current].status & 1))
427 break;
428 auto* buffer = m_rx_buffers_regions[rx_current]->vaddr().as_ptr();
429 u16 length = rx_descriptors[rx_current].length;
430#ifdef E1000_DEBUG
431 klog() << "E1000: Received 1 packet @ " << buffer << " (" << length << ") bytes!";
432#endif
433 did_receive(buffer, length);
434 rx_descriptors[rx_current].status = 0;
435 out32(REG_RXDESCTAIL, rx_current);
436 }
437}
438
439}