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Serenity Operating System
1/*
2 * Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <AK/Assertions.h>
28#include <AK/StringView.h>
29#include <AK/Types.h>
30#include <Kernel/Arch/i386/CPU.h>
31#include <Kernel/Interrupts/APIC.h>
32#include <Kernel/Interrupts/SpuriousInterruptHandler.h>
33#include <Kernel/VM/MemoryManager.h>
34#include <LibBareMetal/IO.h>
35
36#define IRQ_APIC_SPURIOUS 0x7f
37
38#define APIC_BASE_MSR 0x1b
39
40#define APIC_REG_EOI 0xb0
41#define APIC_REG_LD 0xd0
42#define APIC_REG_DF 0xe0
43#define APIC_REG_SIV 0xf0
44#define APIC_REG_TPR 0x80
45#define APIC_REG_ICR_LOW 0x300
46#define APIC_REG_ICR_HIGH 0x310
47#define APIC_REG_LVT_TIMER 0x320
48#define APIC_REG_LVT_THERMAL 0x330
49#define APIC_REG_LVT_PERFORMANCE_COUNTER 0x340
50#define APIC_REG_LVT_LINT0 0x350
51#define APIC_REG_LVT_LINT1 0x360
52#define APIC_REG_LVT_ERR 0x370
53
54namespace Kernel {
55
56namespace APIC {
57
58class ICRReg {
59 u32 m_reg { 0 };
60
61public:
62 enum DeliveryMode {
63 Fixed = 0x0,
64 LowPriority = 0x1,
65 SMI = 0x2,
66 NMI = 0x4,
67 INIT = 0x5,
68 StartUp = 0x6,
69 };
70 enum DestinationMode {
71 Physical = 0x0,
72 Logical = 0x0,
73 };
74 enum Level {
75 DeAssert = 0x0,
76 Assert = 0x1
77 };
78 enum class TriggerMode {
79 Edge = 0x0,
80 Level = 0x1,
81 };
82 enum DestinationShorthand {
83 NoShorthand = 0x0,
84 Self = 0x1,
85 AllIncludingSelf = 0x2,
86 AllExcludingSelf = 0x3,
87 };
88
89 ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destination)
90 : m_reg(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination << 18))
91 {
92 }
93
94 u32 low() const { return m_reg; }
95 u32 high() const { return 0; }
96};
97
98static volatile u8* g_apic_base = nullptr;
99
100static PhysicalAddress get_base()
101{
102 u32 lo, hi;
103 MSR msr(APIC_BASE_MSR);
104 msr.get(lo, hi);
105 return PhysicalAddress(lo & 0xfffff000);
106}
107
108static void set_base(const PhysicalAddress& base)
109{
110 u32 hi = 0;
111 u32 lo = base.get() | 0x800;
112 MSR msr(APIC_BASE_MSR);
113 msr.set(lo, hi);
114}
115
116static void write_register(u32 offset, u32 value)
117{
118 auto lapic_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)g_apic_base)), PAGE_SIZE, "LAPIC Write Access", Region::Access::Read | Region::Access::Write, false, true);
119 auto* lapic = (volatile u32*)lapic_region->vaddr().offset(offset_in_page((u32)g_apic_base)).offset(offset).as_ptr();
120 *lapic = value;
121}
122
123static u32 read_register(u32 offset)
124{
125 auto lapic_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)g_apic_base)), PAGE_SIZE, "LAPIC Read Access", Region::Access::Read, false, true);
126 auto* lapic = (volatile u32*)lapic_region->vaddr().offset(offset_in_page((u32)g_apic_base)).offset(offset).as_ptr();
127 return *lapic;
128}
129
130static void write_icr(const ICRReg& icr)
131{
132 write_register(APIC_REG_ICR_HIGH, icr.high());
133 write_register(APIC_REG_ICR_LOW, icr.low());
134}
135
136#define APIC_LVT_MASKED (1 << 16)
137#define APIC_LVT_TRIGGER_LEVEL (1 << 14)
138#define APIC_LVT(iv, dm) ((iv & 0xff) | ((dm & 0x7) << 8))
139
140asm(
141 ".globl apic_ap_start \n"
142 ".type apic_ap_start, @function \n"
143 "apic_ap_start: \n"
144 ".set begin_apic_ap_start, . \n"
145 " jmp apic_ap_start\n" // TODO: implement
146 ".set end_apic_ap_start, . \n"
147 "\n"
148 ".globl apic_ap_start_size \n"
149 "apic_ap_start_size: \n"
150 ".word end_apic_ap_start - begin_apic_ap_start \n");
151
152extern "C" void apic_ap_start(void);
153extern "C" u16 apic_ap_start_size;
154
155void eoi()
156{
157 write_register(APIC_REG_EOI, 0x0);
158}
159
160u8 spurious_interrupt_vector()
161{
162 return IRQ_APIC_SPURIOUS;
163}
164
165bool init()
166{
167 // FIXME: Use the ACPI MADT table
168 if (!MSR::have())
169 return false;
170
171 // check if we support local apic
172 CPUID id(1);
173 if ((id.edx() & (1 << 9)) == 0)
174 return false;
175
176 PhysicalAddress apic_base = get_base();
177 klog() << "Initializing APIC, base: " << apic_base;
178 set_base(apic_base);
179
180 g_apic_base = apic_base.as_ptr();
181
182 return true;
183}
184
185void enable_bsp()
186{
187 // FIXME: Ensure this method can only be executed by the BSP.
188 enable(0);
189}
190
191void enable(u32 cpu)
192{
193 klog() << "Enabling local APIC for cpu #" << cpu;
194
195 // dummy read, apparently to avoid a bug in old CPUs.
196 read_register(APIC_REG_SIV);
197 // set spurious interrupt vector
198 write_register(APIC_REG_SIV, (IRQ_APIC_SPURIOUS + IRQ_VECTOR_BASE) | 0x100);
199
200 // local destination mode (flat mode)
201 write_register(APIC_REG_DF, 0xf0000000);
202
203 // set destination id (note that this limits it to 8 cpus)
204 write_register(APIC_REG_LD, 0);
205
206 SpuriousInterruptHandler::initialize(IRQ_APIC_SPURIOUS);
207
208 write_register(APIC_REG_LVT_TIMER, APIC_LVT(0, 0) | APIC_LVT_MASKED);
209 write_register(APIC_REG_LVT_THERMAL, APIC_LVT(0, 0) | APIC_LVT_MASKED);
210 write_register(APIC_REG_LVT_PERFORMANCE_COUNTER, APIC_LVT(0, 0) | APIC_LVT_MASKED);
211 write_register(APIC_REG_LVT_LINT0, APIC_LVT(0, 7) | APIC_LVT_MASKED);
212 write_register(APIC_REG_LVT_LINT1, APIC_LVT(0, 0) | APIC_LVT_TRIGGER_LEVEL);
213 write_register(APIC_REG_LVT_ERR, APIC_LVT(0, 0) | APIC_LVT_MASKED);
214
215 write_register(APIC_REG_TPR, 0);
216
217 if (cpu != 0) {
218 static volatile u32 foo = 0;
219
220 // INIT
221 write_icr(ICRReg(0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf));
222
223 for (foo = 0; foo < 0x800000; foo++)
224 ; // TODO: 10 millisecond delay
225
226 for (int i = 0; i < 2; i++) {
227 // SIPI
228 write_icr(ICRReg(0x08, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf)); // start execution at P8000
229
230 for (foo = 0; foo < 0x80000; foo++)
231 ; // TODO: 200 microsecond delay
232 }
233 }
234}
235
236}
237
238}