jcs.org
fork of PCE focusing on macplus, supporting DaynaPort SCSI network emulation
1/*****************************************************************************
2 * pce *
3 *****************************************************************************/
4
5/*****************************************************************************
6 * File name: src/cpu/ppc405/opcode1f.c *
7 * Created: 2003-11-08 by Hampa Hug <hampa@hampa.ch> *
8 * Copyright: (C) 2003-2018 Hampa Hug <hampa@hampa.ch> *
9 * Copyright: (C) 2003-2006 Lukas Ruf <ruf@lpr.ch> *
10 *****************************************************************************/
11
12/*****************************************************************************
13 * This program is free software. You can redistribute it and / or modify it *
14 * under the terms of the GNU General Public License version 2 as published *
15 * by the Free Software Foundation. *
16 * *
17 * This program is distributed in the hope that it will be useful, but *
18 * WITHOUT ANY WARRANTY, without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General *
20 * Public License for more details. *
21 *****************************************************************************/
22
23/*****************************************************************************
24 * This software was developed at the Computer Engineering and Networks *
25 * Laboratory (TIK), Swiss Federal Institute of Technology (ETH) Zurich. *
26 *****************************************************************************/
27
28
29#include <stdlib.h>
30#include <stdio.h>
31
32#include "ppc405.h"
33#include "internal.h"
34
35
36/* 1F 000: cmp bf, ra, rb */
37static
38void op_1f_000 (p405_t *c)
39{
40 unsigned f;
41 uint32_t d, s1, s2;
42
43 s1 = p405_get_ra (c, c->ir) ^ 0x80000000;
44 s2 = p405_get_rb (c, c->ir) ^ 0x80000000;
45
46 f = (c->ir >> 23) & 0x07;
47
48 if (s1 < s2) {
49 d = P405_CR_LT;
50 }
51 else if (s1 > s2) {
52 d = P405_CR_GT;
53 }
54 else {
55 d = P405_CR_EQ;
56 }
57
58 if (p405_get_xer_so (c)) {
59 d |= P405_CR_SO;
60 }
61
62 f = 4 * (7 - f);
63
64 c->cr &= ~(0x0fUL << f);
65 c->cr |= d << f;
66
67 p405_set_clk (c, 4, 1);
68}
69
70/* 1F 008: subfc[.] rt, ra, rb */
71static
72void op_1f_008 (p405_t *c)
73{
74 uint32_t rt, s1, s2;
75
76 s1 = p405_get_rb (c, c->ir);
77 s2 = p405_get_ra (c, c->ir);
78
79 rt = (s1 - s2) & 0xffffffff;
80
81 p405_set_rt (c, c->ir, rt);
82
83 p405_set_xer_ca (c, rt <= s1);
84
85 if (p405_get_ir_rc (c->ir)) {
86 p405_set_cr0 (c, rt);
87 }
88
89 p405_set_clk (c, 4, 1);
90}
91
92/* 1F 00A: addc[.] rt, ra, rb */
93static
94void op_1f_00a (p405_t *c)
95{
96 uint32_t rt, s1, s2;
97
98 s1 = p405_get_ra (c, c->ir);
99 s2 = p405_get_rb (c, c->ir);
100
101 rt = (s1 + s2) & 0xffffffff;
102
103 p405_set_rt (c, c->ir, rt);
104
105 p405_set_xer_ca (c, rt < s1);
106
107 if (p405_get_ir_rc (c->ir)) {
108 p405_set_cr0 (c, rt);
109 }
110
111 p405_set_clk (c, 4, 1);
112}
113
114/* 1F 00B: mulhwu[.] rt, ra, rb */
115static
116void op_1f_00b (p405_t *c)
117{
118 uint64_t rt;
119
120 if (p405_check_reserved (c, 0x00000400UL)) {
121 return;
122 }
123
124 rt = (uint64_t) p405_get_ra (c, c->ir) * (uint64_t) p405_get_rb (c, c->ir);
125 rt = (rt >> 32) & 0xffffffffUL;
126
127 p405_set_rt (c, c->ir, rt);
128
129 if (p405_get_ir_rc (c->ir)) {
130 p405_set_cr0 (c, rt);
131 }
132
133 p405_set_clk (c, 4, 5);
134}
135
136/* 1F 013: mfcr rt */
137static
138void op_1f_013 (p405_t *c)
139{
140 if (p405_check_reserved (c, 0x001ff801UL)) {
141 return;
142 }
143
144 p405_set_rt (c, c->ir, p405_get_cr (c));
145
146 p405_set_clk (c, 4, 1);
147}
148
149/* 1F 014: lwarx rt, ra0, rb */
150static
151void op_1f_014 (p405_t *c)
152{
153 uint32_t rt, ea;
154
155 if (p405_get_ea (c, &ea, 1, 0)) {
156 return;
157 }
158
159 c->reserve = 1;
160
161 if (p405_dload32 (c, ea, &rt)) {
162 return;
163 }
164
165 p405_set_rt (c, c->ir, rt);
166
167 p405_set_clk (c, 4, 1);
168}
169
170/* 1F 017: lwzx rt, ra0, rb */
171static
172void op_1f_017 (p405_t *c)
173{
174 uint32_t rt, ea;
175
176 if (p405_get_ea (c, &ea, 1, 0)) {
177 return;
178 }
179
180 if (p405_dload32 (c, ea, &rt)) {
181 return;
182 }
183
184 p405_set_rt (c, c->ir, rt);
185
186 p405_set_clk (c, 4, 1);
187}
188
189/* 1F 018: slw[.] ra, rs, rb */
190static
191void op_1f_018 (p405_t *c)
192{
193 uint32_t ra, rb;
194
195 rb = p405_get_rb (c, c->ir);
196
197 if (rb & 0x20) {
198 ra = 0;
199 }
200 else {
201 ra = (p405_get_rs (c, c->ir) << (rb & 0x1f)) & 0xffffffffUL;
202 }
203
204 p405_set_ra (c, c->ir, ra);
205
206 if (p405_get_ir_rc (c->ir)) {
207 p405_set_cr0 (c, ra);
208 }
209
210 p405_set_clk (c, 4, 1);
211}
212
213/* 1F 01A: cntlzw[.] ra, rs */
214static
215void op_1f_01a (p405_t *c)
216{
217 uint32_t ra, rs, msk;
218
219 if (p405_check_reserved (c, 0x0000f800UL)) {
220 return;
221 }
222
223 rs = p405_get_rs (c, c->ir);
224 ra = 0;
225
226 if (rs != 0) {
227 msk = 0x80000000UL;
228 while ((rs & msk) == 0) {
229 ra += 1;
230 msk = msk >> 1;
231 }
232 }
233 else {
234 ra = 32;
235 }
236
237 p405_set_ra (c, c->ir, ra);
238
239 if (p405_get_ir_rc (c->ir)) {
240 p405_set_cr0 (c, ra);
241 }
242
243 p405_set_clk (c, 4, 1);
244}
245
246/* 1F 01C: and[.] ra, rs, rb */
247static
248void op_1f_01c (p405_t *c)
249{
250 uint32_t rt, s1, s2;
251
252 s1 = p405_get_rs (c, c->ir);
253 s2 = p405_get_rb (c, c->ir);
254
255 rt = s1 & s2;
256
257 p405_set_ra (c, c->ir, rt);
258
259 if (p405_get_ir_rc (c->ir)) {
260 p405_set_cr0 (c, rt);
261 }
262
263 p405_set_clk (c, 4, 1);
264}
265
266/* 1F 020: cmpl bf, ra, rb */
267static
268void op_1f_020 (p405_t *c)
269{
270 unsigned f;
271 uint32_t d, s1, s2;
272
273 s1 = p405_get_ra (c, c->ir);
274 s2 = p405_get_rb (c, c->ir);
275
276 f = (c->ir >> 23) & 0x07;
277
278 if (s1 < s2) {
279 d = P405_CR_LT;
280 }
281 else if (s1 > s2) {
282 d = P405_CR_GT;
283 }
284 else {
285 d = P405_CR_EQ;
286 }
287
288 if (c->xer & P405_XER_SO) {
289 d = P405_CR_SO;
290 }
291
292 f = 4 * (7 - f);
293
294 c->cr &= ~(0x0fUL << f);
295 c->cr |= d << f;
296
297 p405_set_clk (c, 4, 1);
298}
299
300/* 1F 028: subf[.] rt, ra, rb */
301static
302void op_1f_028 (p405_t *c)
303{
304 uint32_t rt, s1, s2;
305
306 s1 = p405_get_rb (c, c->ir);
307 s2 = p405_get_ra (c, c->ir);
308
309 rt = (s1 - s2) & 0xffffffff;
310
311 p405_set_rt (c, c->ir, rt);
312
313 if (p405_get_ir_rc (c->ir)) {
314 p405_set_cr0 (c, rt);
315 }
316
317 p405_set_clk (c, 4, 1);
318}
319
320/* 1F 036: dcbst ra0, rb */
321static
322void op_1f_036 (p405_t *c)
323{
324 if (p405_check_reserved (c, 0x03e00001UL)) {
325 return;
326 }
327
328 p405_set_clk (c, 4, 1);
329}
330
331/* 1F 037: lwzux rt, ra, rb */
332static
333void op_1f_037 (p405_t *c)
334{
335 uint32_t rt, ea;
336
337 if (p405_get_ea (c, &ea, 1, 1)) {
338 return;
339 }
340
341 if (p405_dload32 (c, ea, &rt)) {
342 return;
343 }
344
345 p405_set_ra (c, c->ir, ea);
346 p405_set_rt (c, c->ir, rt);
347
348 p405_set_clk (c, 4, 1);
349}
350
351/* 1F 03C: andc[.] ra, rs, rb */
352static
353void op_1f_03c (p405_t *c)
354{
355 uint32_t rt, s1, s2;
356
357 s1 = p405_get_rs (c, c->ir);
358 s2 = p405_get_rb (c, c->ir);
359
360 rt = s1 & ~s2;
361
362 p405_set_ra (c, c->ir, rt);
363
364 if (p405_get_ir_rc (c->ir)) {
365 p405_set_cr0 (c, rt);
366 }
367
368 p405_set_clk (c, 4, 1);
369}
370
371/* 1F 04B: mulhw[.] rt, ra, rb */
372static
373void op_1f_04b (p405_t *c)
374{
375 uint64_t rt;
376
377 if (p405_check_reserved (c, 0x00000400UL)) {
378 return;
379 }
380
381 rt = p405_mul (p405_get_ra (c, c->ir), p405_get_rb (c, c->ir));
382 rt = (rt >> 32) & 0xffffffffUL;
383
384 p405_set_rt (c, c->ir, rt);
385
386 if (p405_get_ir_rc (c->ir)) {
387 p405_set_cr0 (c, rt);
388 }
389
390 p405_set_clk (c, 4, 5);
391}
392
393/* 1F 053: mfmsr rt */
394static
395void op_1f_053 (p405_t *c)
396{
397 if (p405_check_reserved (c, 0x001ff801UL)) {
398 return;
399 }
400
401 p405_set_rt (c, c->ir, p405_get_msr (c));
402
403 p405_set_clk (c, 4, 1);
404}
405
406/* 1F 056: dcbf ra0, rb */
407static
408void op_1f_056 (p405_t *c)
409{
410 if (p405_check_reserved (c, 0x03e00001UL)) {
411 return;
412 }
413
414 p405_set_clk (c, 4, 1);
415}
416
417/* 1F 057: lbzx rt, ra0, rb */
418static
419void op_1f_057 (p405_t *c)
420{
421 uint8_t rt;
422 uint32_t ea;
423
424 if (p405_get_ea (c, &ea, 1, 0)) {
425 return;
426 }
427
428 if (p405_dload8 (c, ea, &rt)) {
429 return;
430 }
431
432 p405_set_rt (c, c->ir, p405_uext (rt, 8));
433
434 p405_set_clk (c, 4, 1);
435}
436
437/* 1F 068: neg[.] rt, ra */
438static
439void op_1f_068 (p405_t *c)
440{
441 uint32_t rt;
442
443 if (p405_check_reserved (c, 0x0000f800)) {
444 return;
445 }
446
447 rt = -p405_get_ra (c, c->ir) & 0xffffffff;
448
449 p405_set_rt (c, c->ir, rt);
450
451 if (p405_get_ir_rc (c->ir)) {
452 p405_set_cr0 (c, rt);
453 }
454
455 p405_set_clk (c, 4, 1);
456}
457
458/* 1F 077: lbzux rt, ra, rb */
459static
460void op_1f_077 (p405_t *c)
461{
462 uint8_t rt;
463 uint32_t ea;
464
465 if (p405_get_ea (c, &ea, 1, 1)) {
466 return;
467 }
468
469 if (p405_dload8 (c, ea, &rt)) {
470 return;
471 }
472
473 p405_set_ra (c, c->ir, ea);
474 p405_set_rt (c, c->ir, p405_uext (rt, 8));
475
476 p405_set_clk (c, 4, 1);
477}
478
479/* 1F 07c: nor[.] ra, rs, rb */
480static
481void op_1f_07c (p405_t *c)
482{
483 uint32_t ra;
484
485 ra = ~(p405_get_rs (c, c->ir) | p405_get_rb (c, c->ir)) & 0xffffffffUL;
486
487 p405_set_ra (c, c->ir, ra);
488
489 if (p405_get_ir_rc (c->ir)) {
490 p405_set_cr0 (c, ra);
491 }
492
493 p405_set_clk (c, 4, 1);
494}
495
496/* 1F 083: wrtee rs */
497static
498void op_1f_083 (p405_t *c)
499{
500 if (p405_check_reserved (c, 0x001ff801UL)) {
501 return;
502 }
503
504 if (p405_check_privilege (c)) {
505 return;
506 }
507
508 p405_set_msr_ee (c, p405_get_rs (c, c->ir) & 0x8000UL);
509
510 p405_set_clk (c, 4, 1);
511}
512
513/* 1F 086: dcbf ra0, rb */
514static
515void op_1f_086 (p405_t *c)
516{
517 if (p405_check_reserved (c, 0x03e00001UL)) {
518 return;
519 }
520
521 p405_set_clk (c, 4, 1);
522}
523
524/* 1F 088: subfe[.] rt, ra, rb */
525static
526void op_1f_088 (p405_t *c)
527{
528 uint32_t rt, s1, s2, s3;
529
530 s1 = p405_get_rb (c, c->ir);
531 s2 = ~p405_get_ra (c, c->ir);
532 s3 = p405_get_xer_ca (c);
533
534 rt = (s1 + s2 + s3) & 0xffffffff;
535
536 p405_set_rt (c, c->ir, rt);
537
538 p405_set_xer_ca (c, (rt < s1) || ((rt == s1) && s3));
539
540 if (p405_get_ir_rc (c->ir)) {
541 p405_set_cr0 (c, rt);
542 }
543
544 p405_set_clk (c, 4, 1);
545}
546
547/* 1F 08A: adde[.] rt, ra, rb */
548static
549void op_1f_08a (p405_t *c)
550{
551 uint32_t rt, s1, s2, s3;
552
553 s1 = p405_get_ra (c, c->ir);
554 s2 = p405_get_rb (c, c->ir);
555 s3 = p405_get_xer_ca (c);
556
557 rt = (s1 + s2 + s3) & 0xffffffff;
558
559 p405_set_rt (c, c->ir, rt);
560
561 p405_set_xer_ca (c, (rt < s1) || ((rt == s1) && s3));
562
563 if (p405_get_ir_rc (c->ir)) {
564 p405_set_cr0 (c, rt);
565 }
566
567 p405_set_clk (c, 4, 1);
568}
569
570/* 1F 090: mtcrf fxm, rs */
571static
572void op_1f_090 (p405_t *c)
573{
574 unsigned i, fxm;
575 uint32_t rs, msk;
576
577 if (p405_check_reserved (c, 0x00100801UL)) {
578 return;
579 }
580
581 rs = p405_get_rs (c, c->ir);
582 fxm = (c->ir >> 12) & 0xff;
583
584 msk = 0;
585
586 for (i = 0; i < 8; i++) {
587 if (fxm & (0x80 >> i)) {
588 msk |= 0xf0000000UL >> (4 * i);
589 }
590 }
591
592 p405_set_cr (c, (p405_get_cr (c) & ~msk) | (rs & msk));
593
594 p405_set_clk (c, 4, 1);
595}
596
597/* 1F 092: mtmsr rs */
598static
599void op_1f_092 (p405_t *c)
600{
601 if (p405_check_reserved (c, 0x001ff801UL)) {
602 return;
603 }
604
605 p405_set_msr (c, p405_get_rs (c, c->ir));
606
607 p405_set_clk (c, 4, 1);
608}
609
610/* 1F 096: stwcx. rs, ra0, rb */
611static
612void op_1f_096 (p405_t *c)
613{
614 uint32_t ea;
615
616 if (p405_get_ea (c, &ea, 1, 0)) {
617 return;
618 }
619
620 p405_set_crf (c, 0, 0);
621 p405_set_cr_so (c, 0, p405_get_xer_ov (c));
622
623 if (c->reserve) {
624 if (p405_dstore32 (c, ea, p405_get_rs (c, c->ir))) {
625 return;
626 }
627
628 c->reserve = 0;
629
630 p405_set_cr_eq (c, 0, 1);
631 }
632
633 p405_set_clk (c, 4, 1);
634}
635
636/* 1F 097: stwx rs, ra0, rb */
637static
638void op_1f_097 (p405_t *c)
639{
640 uint32_t ea;
641
642 if (p405_check_reserved (c, 0x01)) {
643 return;
644 }
645
646 if (p405_get_ea (c, &ea, 1, 0)) {
647 return;
648 }
649
650 if (p405_dstore32 (c, ea, p405_get_rs (c, c->ir))) {
651 return;
652 }
653
654 p405_set_clk (c, 4, 1);
655}
656
657/* 1F 0A3: wrteei e */
658static
659void op_1f_0a3 (p405_t *c)
660{
661 if (p405_check_reserved (c, 0x03ff7801UL)) {
662 return;
663 }
664
665 if (p405_check_privilege (c)) {
666 return;
667 }
668
669 p405_set_msr_ee (c, c->ir & 0x8000UL);
670
671 p405_set_clk (c, 4, 1);
672}
673
674/* 1F 0B7: stwux rs, ra, rb */
675static
676void op_1f_0b7 (p405_t *c)
677{
678 uint32_t ea;
679
680 if (p405_check_reserved (c, 0x01)) {
681 return;
682 }
683
684 if (p405_get_ea (c, &ea, 1, 1)) {
685 return;
686 }
687
688 if (p405_dstore32 (c, ea, p405_get_rs (c, c->ir))) {
689 return;
690 }
691
692 p405_set_ra (c, c->ir, ea);
693
694 p405_set_clk (c, 4, 1);
695}
696
697/* 1F 0C8: subfze[.] rt, ra */
698static
699void op_1f_0c8 (p405_t *c)
700{
701 uint32_t rt, s2, s3;
702
703 if (p405_check_reserved (c, 0x0000f800)) {
704 return;
705 }
706
707 s2 = ~p405_get_ra (c, c->ir);
708 s3 = p405_get_xer_ca (c);
709
710 rt = (0 + s2 + s3) & 0xffffffff;
711
712 p405_set_rt (c, c->ir, rt);
713
714 p405_set_xer_ca (c, (rt == 0) && s3);
715
716 if (p405_get_ir_rc (c->ir)) {
717 p405_set_cr0 (c, rt);
718 }
719
720 p405_set_clk (c, 4, 1);
721}
722
723/* 1F 0CA: addze[.] rt, ra */
724static
725void op_1f_0ca (p405_t *c)
726{
727 uint32_t rt, s1, s2;
728
729 if (p405_check_reserved (c, 0x0000f800)) {
730 return;
731 }
732
733 s1 = p405_get_ra (c, c->ir);
734 s2 = p405_get_xer_ca (c);
735
736 rt = (s1 + s2) & 0xffffffff;
737
738 p405_set_rt (c, c->ir, rt);
739
740 p405_set_xer_ca (c, rt < s1);
741
742 if (p405_get_ir_rc (c->ir)) {
743 p405_set_cr0 (c, rt);
744 }
745
746 p405_set_clk (c, 4, 1);
747}
748
749/* 1F 0D7: stbx rs, ra0, rb */
750static
751void op_1f_0d7 (p405_t *c)
752{
753 uint32_t ea;
754
755 if (p405_check_reserved (c, 0x01)) {
756 return;
757 }
758
759 if (p405_get_ea (c, &ea, 1, 0)) {
760 return;
761 }
762
763 if (p405_dstore8 (c, ea, p405_uext (p405_get_rs (c, c->ir), 8))) {
764 return;
765 }
766
767 p405_set_clk (c, 4, 1);
768}
769
770/* 1F 0E8: subfme[.] rt, ra */
771static
772void op_1f_0e8 (p405_t *c)
773{
774 uint32_t rt, s2, s3;
775
776 if (p405_check_reserved (c, 0x0000f800)) {
777 return;
778 }
779
780 s2 = ~p405_get_ra (c, c->ir);
781 s3 = p405_get_xer_ca (c);
782
783 rt = (0xffffffff + s2 + s3) & 0xffffffff;
784
785 p405_set_rt (c, c->ir, rt);
786
787 p405_set_xer_ca (c, s2 || s3);
788
789 if (p405_get_ir_rc (c->ir)) {
790 p405_set_cr0 (c, rt);
791 }
792
793 p405_set_clk (c, 4, 1);
794}
795
796/* 1F 0EA: addme[.] rt, ra */
797static
798void op_1f_0ea (p405_t *c)
799{
800 uint32_t rt, s1, s2;
801
802 if (p405_check_reserved (c, 0x0000f800)) {
803 return;
804 }
805
806 s1 = p405_get_ra (c, c->ir);
807 s2 = p405_get_xer_ca (c);
808
809 rt = (s1 + s2 - 1) & 0xffffffff;
810
811 p405_set_rt (c, c->ir, rt);
812
813 p405_set_xer_ca (c, (s1 > 0) || (s2 > 0));
814
815 if (p405_get_ir_rc (c->ir)) {
816 p405_set_cr0 (c, rt);
817 }
818
819 p405_set_clk (c, 4, 1);
820}
821
822/* 1F 0EB: mullw[.] rt, ra, rb */
823static
824void op_1f_0eb (p405_t *c)
825{
826 uint32_t rt, s1, s2;
827
828 s1 = p405_get_ra (c, c->ir);
829 s2 = p405_get_rb (c, c->ir);
830
831 rt = s1 * s2;
832
833 p405_set_rt (c, c->ir, rt);
834
835 if (p405_get_ir_rc (c->ir)) {
836 p405_set_cr0 (c, rt);
837 }
838
839 p405_set_clk (c, 4, 5);
840}
841
842/* 1F 0F6: dcbtst ra0, rb */
843static
844void op_1f_0f6 (p405_t *c)
845{
846 if (p405_check_reserved (c, 0x03e00001UL)) {
847 return;
848 }
849
850 p405_set_clk (c, 4, 1);
851}
852
853/* 1F 0F7: stbux rs, ra, rb */
854static
855void op_1f_0f7 (p405_t *c)
856{
857 uint32_t ea;
858
859 if (p405_check_reserved (c, 0x01)) {
860 return;
861 }
862
863 if (p405_get_ea (c, &ea, 1, 1)) {
864 return;
865 }
866
867 if (p405_dstore8 (c, ea, p405_uext (p405_get_rs (c, c->ir), 8))) {
868 return;
869 }
870
871 p405_set_ra (c, c->ir, ea);
872
873 p405_set_clk (c, 4, 1);
874}
875
876/* 1F 106: icbt ra, rb */
877static
878void op_1f_106 (p405_t *c)
879{
880 if (p405_check_reserved (c, 0x03e00001UL)) {
881 return;
882 }
883
884 p405_set_clk (c, 4, 1);
885}
886
887/* 1F 10A: add[.] rt, ra, rb */
888static
889void op_1f_10a (p405_t *c)
890{
891 uint32_t rt, s1, s2;
892
893 s1 = p405_get_ra (c, c->ir);
894 s2 = p405_get_rb (c, c->ir);
895
896 rt = (s1 + s2) & 0xffffffff;
897
898 p405_set_rt (c, c->ir, rt);
899
900 if (p405_get_ir_rc (c->ir)) {
901 p405_set_cr0 (c, rt);
902 }
903
904 p405_set_clk (c, 4, 1);
905}
906
907/* 1F 116: dcbt ra0, rb */
908static
909void op_1f_116 (p405_t *c)
910{
911 if (p405_check_reserved (c, 0x03e00001UL)) {
912 return;
913 }
914
915 p405_set_clk (c, 4, 1);
916}
917
918/* 1F 117: lhzx rt, ra0, rb */
919static
920void op_1f_117 (p405_t *c)
921{
922 uint16_t rt;
923 uint32_t ea;
924
925 if (p405_get_ea (c, &ea, 1, 0)) {
926 return;
927 }
928
929 if (p405_dload16 (c, ea, &rt)) {
930 return;
931 }
932
933 p405_set_rt (c, c->ir, p405_uext (rt, 16));
934
935 p405_set_clk (c, 4, 1);
936}
937
938/* 1F 11C: eqv[.] ra, rs, rb */
939static
940void op_1f_11c (p405_t *c)
941{
942 uint32_t rs, ra, rb;
943
944 rs = p405_get_rs (c, c->ir);
945 rb = p405_get_rb (c, c->ir);
946 ra = ~(rs ^ rb) & 0xffffffffUL;
947 p405_set_ra (c, c->ir, ra);
948
949 if (c->ir & P405_IR_RC) {
950 p405_set_cr0 (c, ra);
951 }
952
953 p405_set_clk (c, 4, 1);
954}
955
956/* 1F 137: lhzux rt, ra, rb */
957static
958void op_1f_137 (p405_t *c)
959{
960 uint16_t rt;
961 uint32_t ea;
962
963 if (p405_get_ea (c, &ea, 1, 1)) {
964 return;
965 }
966
967 if (p405_dload16 (c, ea, &rt)) {
968 return;
969 }
970
971 p405_set_ra (c, c->ir, ea);
972 p405_set_rt (c, c->ir, p405_uext (rt, 16));
973
974 p405_set_clk (c, 4, 1);
975}
976
977/* 1F 13C: xor[.] ra, rs, rb */
978static
979void op_1f_13c (p405_t *c)
980{
981 uint32_t rs, ra, rb;
982
983 rs = p405_get_rs (c, c->ir);
984 rb = p405_get_rb (c, c->ir);
985 ra = rs ^ rb;
986 p405_set_ra (c, c->ir, ra);
987
988 if (p405_get_ir_rc (c->ir)) {
989 p405_set_cr0 (c, ra);
990 }
991
992 p405_set_clk (c, 4, 1);
993}
994
995/* 1F 143: mfdcr rt, dcrn */
996static
997void op_1f_143 (p405_t *c)
998{
999 unsigned dcrf, dcrn;
1000
1001 if (p405_check_privilege (c)) {
1002 return;
1003 }
1004
1005 dcrf = (c->ir >> 11) & 0x3ff;
1006 dcrn = ((dcrf & 0x1f) << 5) | ((dcrf >> 5) & 0x1f);
1007
1008 p405_set_rt (c, c->ir, p405_get_dcr (c, dcrn));
1009
1010 p405_set_clk (c, 4, 1);
1011}
1012
1013/* 1F 153: mfspr rt, sprn */
1014static
1015void op_1f_153 (p405_t *c)
1016{
1017 unsigned sprf, sprn;
1018 uint32_t rt;
1019
1020 sprf = (c->ir >> 11) & 0x3ff;
1021
1022 if (sprf & 0x200) {
1023 if (p405_check_privilege (c)) {
1024 return;
1025 }
1026 }
1027
1028 sprn = ((sprf & 0x1f) << 5) | ((sprf >> 5) & 0x1f);
1029
1030 rt = 0;
1031
1032 switch (sprn) {
1033 case P405_SPRN_CTR:
1034 rt = p405_get_ctr (c);
1035 break;
1036
1037 case P405_SPRN_DBCR0:
1038 rt = p405_get_dbcr0 (c);
1039 break;
1040
1041 case P405_SPRN_DBCR1:
1042 rt = p405_get_dbcr1 (c);
1043 break;
1044
1045 case P405_SPRN_DBSR:
1046 rt = p405_get_dbsr (c);
1047 break;
1048
1049 case P405_SPRN_DCCR:
1050 rt = p405_get_dccr (c);
1051 break;
1052
1053 case P405_SPRN_DCWR:
1054 rt = p405_get_dcwr (c);
1055 break;
1056
1057 case P405_SPRN_DEAR:
1058 rt = p405_get_dear (c);
1059 break;
1060
1061 case P405_SPRN_ESR:
1062 rt = p405_get_esr (c);
1063 break;
1064
1065 case P405_SPRN_EVPR:
1066 rt = p405_get_evpr (c);
1067 break;
1068
1069 case P405_SPRN_ICCR:
1070 rt = p405_get_iccr (c);
1071 break;
1072
1073 case P405_SPRN_LR:
1074 rt = p405_get_lr (c);
1075 break;
1076
1077 case P405_SPRN_PID:
1078 rt = p405_get_pid (c);
1079 break;
1080
1081 case P405_SPRN_PIT:
1082 rt = p405_get_pit (c, 0);
1083 break;
1084
1085 case P405_SPRN_PVR:
1086 rt = p405_get_pvr (c);
1087 break;
1088
1089 case P405_SPRN_SPRG0:
1090 rt = p405_get_sprg (c, 0);
1091 break;
1092
1093 case P405_SPRN_SPRG1:
1094 rt = p405_get_sprg (c, 1);
1095 break;
1096
1097 case P405_SPRN_SPRG2:
1098 rt = p405_get_sprg (c, 2);
1099 break;
1100
1101 case P405_SPRN_SPRG3:
1102 rt = p405_get_sprg (c, 3);
1103 break;
1104
1105 case P405_SPRN_SPRG4:
1106 rt = p405_get_sprg (c, 4);
1107 break;
1108
1109 case P405_SPRN_SPRG5:
1110 rt = p405_get_sprg (c, 5);
1111 break;
1112
1113 case P405_SPRN_SPRG6:
1114 rt = p405_get_sprg (c, 6);
1115 break;
1116
1117 case P405_SPRN_SPRG7:
1118 rt = p405_get_sprg (c, 7);
1119 break;
1120
1121 case P405_SPRN_SPRG4R:
1122 rt = p405_get_sprg (c, 4);
1123 break;
1124
1125 case P405_SPRN_SPRG5R:
1126 rt = p405_get_sprg (c, 5);
1127 break;
1128
1129 case P405_SPRN_SPRG6R:
1130 rt = p405_get_sprg (c, 6);
1131 break;
1132
1133 case P405_SPRN_SPRG7R:
1134 rt = p405_get_sprg (c, 7);
1135 break;
1136
1137 case P405_SPRN_SRR0:
1138 rt = p405_get_srr (c, 0);
1139 break;
1140
1141 case P405_SPRN_SRR1:
1142 rt = p405_get_srr (c, 1);
1143 break;
1144
1145 case P405_SPRN_SRR2:
1146 rt = p405_get_srr (c, 2);
1147 break;
1148
1149 case P405_SPRN_SRR3:
1150 rt = p405_get_srr (c, 3);
1151 break;
1152
1153 case P405_SPRN_TBL:
1154 case P405_SPRN_TBLU:
1155 rt = p405_get_tbl (c);
1156 break;
1157
1158 case P405_SPRN_TBU:
1159 case P405_SPRN_TBUU:
1160 rt = p405_get_tbu (c);
1161 break;
1162
1163 case P405_SPRN_TCR:
1164 rt = p405_get_tcr (c);
1165 break;
1166
1167 case P405_SPRN_XER:
1168 rt = p405_get_xer (c);
1169 break;
1170
1171 case P405_SPRN_ZPR:
1172 rt = p405_get_zpr (c);
1173 break;
1174
1175 default:
1176 p405_op_undefined (c);
1177 return;
1178 }
1179
1180 p405_set_rt (c, c->ir, rt);
1181
1182 p405_set_clk (c, 4, 1);
1183}
1184
1185/* 1F 157: lhax rt, ra, rb */
1186static
1187void op_1f_157 (p405_t *c)
1188{
1189 uint16_t rt;
1190 uint32_t ea;
1191
1192 if (p405_get_ea (c, &ea, 1, 0)) {
1193 return;
1194 }
1195
1196 if (p405_dload16 (c, ea, &rt)) {
1197 return;
1198 }
1199
1200 p405_set_rt (c, c->ir, p405_sext (rt, 16));
1201
1202 p405_set_clk (c, 4, 1);
1203}
1204
1205/* 1F 172: tlbia */
1206static
1207void op_1f_172 (p405_t *c)
1208{
1209 if (p405_check_reserved (c, 0x03fff801UL)) {
1210 return;
1211 }
1212
1213 p405_tlb_invalidate_all (c);
1214
1215 p405_set_clk (c, 4, 1);
1216}
1217
1218/* 1F 173: mftb rt, tbrn */
1219static
1220void op_1f_173 (p405_t *c)
1221{
1222 unsigned tbrf, tbrn;
1223
1224 tbrf = (c->ir >> 11) & 0x3ff;
1225 tbrn = ((tbrf & 0x1f) << 5) | ((tbrf >> 5) & 0x1f);
1226
1227 switch (tbrn) {
1228 case P405_TBRN_TBL:
1229 p405_set_rt (c, c->ir, p405_get_tbl (c));
1230 break;
1231
1232 case P405_TBRN_TBU:
1233 p405_set_rt (c, c->ir, p405_get_tbu (c));
1234 break;
1235 }
1236
1237 p405_set_clk (c, 4, 1);
1238}
1239
1240/* 1F 177: lhaux rt, ra, rb */
1241static
1242void op_1f_177 (p405_t *c)
1243{
1244 uint16_t rt;
1245 uint32_t ea;
1246
1247 if (p405_get_ea (c, &ea, 1, 1)) {
1248 return;
1249 }
1250
1251 if (p405_dload16 (c, ea, &rt)) {
1252 return;
1253 }
1254
1255 p405_set_ra (c, c->ir, ea);
1256 p405_set_rt (c, c->ir, p405_sext (rt, 16));
1257
1258 p405_set_clk (c, 4, 1);
1259}
1260
1261/* 1F 197: sthx rs, ra0, rb */
1262static
1263void op_1f_197 (p405_t *c)
1264{
1265 uint32_t ea;
1266
1267 if (p405_check_reserved (c, 0x01)) {
1268 return;
1269 }
1270
1271 if (p405_get_ea (c, &ea, 1, 0)) {
1272 return;
1273 }
1274
1275 if (p405_dstore16 (c, ea, p405_uext (p405_get_rs (c, c->ir), 16))) {
1276 return;
1277 }
1278
1279 p405_set_clk (c, 4, 1);
1280}
1281
1282/* 1F 19C: orc[.] ra, rs, rb */
1283static
1284void op_1f_19c (p405_t *c)
1285{
1286 uint32_t ra;
1287
1288 ra = (p405_get_rs (c, c->ir) | ~p405_get_rb (c, c->ir)) & 0xffffffffUL;
1289
1290 p405_set_ra (c, c->ir, ra);
1291
1292 if (p405_get_ir_rc (c->ir)) {
1293 p405_set_cr0 (c, ra);
1294 }
1295
1296 p405_set_clk (c, 4, 1);
1297}
1298
1299/* 1F 1B7: sthux rs, ra, rb */
1300static
1301void op_1f_1b7 (p405_t *c)
1302{
1303 uint32_t ea;
1304
1305 if (p405_check_reserved (c, 0x01)) {
1306 return;
1307 }
1308
1309 if (p405_get_ea (c, &ea, 1, 1)) {
1310 return;
1311 }
1312
1313 if (p405_dstore16 (c, ea, p405_uext (p405_get_rs (c, c->ir), 16))) {
1314 return;
1315 }
1316
1317 p405_set_ra (c, c->ir, ea);
1318
1319 p405_set_clk (c, 4, 1);
1320}
1321
1322/* 1F 1BC: or[.] ra, rs, rb */
1323static
1324void op_1f_1bc (p405_t *c)
1325{
1326 uint32_t rs, ra, rb;
1327
1328 rs = p405_get_rs (c, c->ir);
1329 rb = p405_get_rb (c, c->ir);
1330 ra = rs | rb;
1331 p405_set_ra (c, c->ir, ra);
1332
1333 if (p405_get_ir_rc (c->ir)) {
1334 p405_set_cr0 (c, ra);
1335 }
1336
1337 p405_set_clk (c, 4, 1);
1338}
1339
1340/* 1F 1C3: mtdcr dcrn, rs */
1341static
1342void op_1f_1c3 (p405_t *c)
1343{
1344 unsigned dcrf, dcrn;
1345
1346 if (p405_check_privilege (c)) {
1347 return;
1348 }
1349
1350 dcrf = (c->ir >> 11) & 0x3ff;
1351 dcrn = ((dcrf & 0x1f) << 5) | ((dcrf >> 5) & 0x1f);
1352
1353 p405_set_dcr (c, dcrn, p405_get_rs (c, c->ir));
1354
1355 p405_set_clk (c, 4, 1);
1356}
1357
1358/* 1F 1C6: dccci ra0, rb */
1359static
1360void op_1f_1c6 (p405_t *c)
1361{
1362 if (p405_check_reserved (c, 0x03e00001UL)) {
1363 return;
1364 }
1365
1366 p405_set_clk (c, 4, 1);
1367}
1368
1369/* 1F 1CB: divwu[.] rt, ra, rb */
1370static
1371void op_1f_1cb (p405_t *c)
1372{
1373 uint32_t rt, ra, rb;
1374
1375 ra = p405_get_ra (c, c->ir);
1376 rb = p405_get_rb (c, c->ir);
1377
1378 if (rb == 0) {
1379 p405_set_clk (c, 4, 1);
1380 return;
1381 }
1382
1383 rt = ra / rb;
1384
1385 p405_set_rt (c, c->ir, rt);
1386
1387 if (p405_get_ir_rc (c->ir)) {
1388 p405_set_cr0 (c, rt);
1389 }
1390
1391 p405_set_clk (c, 4, 35);
1392}
1393
1394/* 1F 1D3: mtspr sprn, rs */
1395static
1396void op_1f_1d3 (p405_t *c)
1397{
1398 unsigned sprf, sprn;
1399 uint32_t rs;
1400
1401 sprf = (c->ir >> 11) & 0x3ff;
1402
1403 if (sprf & 0x200) {
1404 if (p405_check_privilege (c)) {
1405 return;
1406 }
1407 }
1408
1409 sprn = ((sprf & 0x1f) << 5) | ((sprf >> 5) & 0x1f);
1410
1411 rs = p405_get_rs (c, c->ir);
1412
1413 switch (sprn) {
1414 case P405_SPRN_CTR:
1415 p405_set_ctr (c, rs);
1416 break;
1417
1418 case P405_SPRN_DBCR0:
1419 p405_set_dbcr0 (c, rs);
1420 break;
1421
1422 case P405_SPRN_DBCR1:
1423 p405_set_dbcr1 (c, rs);
1424 break;
1425
1426 case P405_SPRN_DBSR:
1427 p405_set_dbsr (c, p405_get_dbsr (c) & ~rs);
1428 break;
1429
1430 case P405_SPRN_DCCR:
1431 p405_set_dccr (c, rs);
1432 break;
1433
1434 case P405_SPRN_DCWR:
1435 p405_set_dcwr (c, rs);
1436 break;
1437
1438 case P405_SPRN_DEAR:
1439 p405_set_dear (c, rs);
1440 break;
1441
1442 case P405_SPRN_ESR:
1443 p405_set_esr (c, rs);
1444 break;
1445
1446 case P405_SPRN_EVPR:
1447 p405_set_evpr (c, rs);
1448 break;
1449
1450 case P405_SPRN_ICCR:
1451 p405_set_iccr (c, rs);
1452 break;
1453
1454 case P405_SPRN_LR:
1455 p405_set_lr (c, rs);
1456 break;
1457
1458 case P405_SPRN_PID:
1459 p405_set_pid (c, rs);
1460 p405_tbuf_clear (c);
1461 break;
1462
1463 case P405_SPRN_PIT:
1464 p405_set_pit (c, 0, rs);
1465 p405_set_pit (c, 1, rs);
1466 break;
1467
1468 case P405_SPRN_PVR:
1469 /* p405_set_pvr (c, rs); */
1470 break;
1471
1472 case P405_SPRN_SPRG0:
1473 p405_set_sprg (c, 0, rs);
1474 break;
1475
1476 case P405_SPRN_SPRG1:
1477 p405_set_sprg (c, 1, rs);
1478 break;
1479
1480 case P405_SPRN_SPRG2:
1481 p405_set_sprg (c, 2, rs);
1482 break;
1483
1484 case P405_SPRN_SPRG3:
1485 p405_set_sprg (c, 3, rs);
1486 break;
1487
1488 case P405_SPRN_SPRG4:
1489 p405_set_sprg (c, 4, rs);
1490 break;
1491
1492 case P405_SPRN_SPRG5:
1493 p405_set_sprg (c, 5, rs);
1494 break;
1495
1496 case P405_SPRN_SPRG6:
1497 p405_set_sprg (c, 6, rs);
1498 break;
1499
1500 case P405_SPRN_SPRG7:
1501 p405_set_sprg (c, 7, rs);
1502 break;
1503
1504 case P405_SPRN_SPRG4R:
1505 p405_set_sprg (c, 4, rs);
1506 break;
1507
1508 case P405_SPRN_SPRG5R:
1509 p405_set_sprg (c, 5, rs);
1510 break;
1511
1512 case P405_SPRN_SPRG6R:
1513 p405_set_sprg (c, 6, rs);
1514 break;
1515
1516 case P405_SPRN_SPRG7R:
1517 p405_set_sprg (c, 7, rs);
1518 break;
1519
1520 case P405_SPRN_SRR0:
1521 p405_set_srr (c, 0, rs);
1522 break;
1523
1524 case P405_SPRN_SRR1:
1525 p405_set_srr (c, 1, rs);
1526 break;
1527
1528 case P405_SPRN_SRR2:
1529 p405_set_srr (c, 2, rs);
1530 break;
1531
1532 case P405_SPRN_SRR3:
1533 p405_set_srr (c, 3, rs);
1534 break;
1535
1536 case P405_SPRN_TBL:
1537 p405_set_tbl (c, rs);
1538 break;
1539
1540 case P405_SPRN_TCR:
1541 p405_set_tcr (c, rs);
1542 break;
1543
1544 case P405_SPRN_TBU:
1545 p405_set_tbu (c, rs);
1546 break;
1547
1548 case P405_SPRN_TSR:
1549 p405_set_tsr (c, p405_get_tsr (c) & ~rs);
1550 break;
1551
1552 case P405_SPRN_XER:
1553 p405_set_xer (c, rs);
1554 break;
1555
1556 case P405_SPRN_ZPR:
1557 p405_set_zpr (c, rs);
1558 p405_tbuf_clear (c);
1559 break;
1560
1561 default:
1562 p405_op_undefined (c);
1563 return;
1564 }
1565
1566 p405_set_clk (c, 4, 1);
1567}
1568
1569/* 1F 1D6: dcbi ra0, rb */
1570static
1571void op_1f_1d6 (p405_t *c)
1572{
1573 if (p405_check_reserved (c, 0x03e00001UL)) {
1574 return;
1575 }
1576
1577 p405_set_clk (c, 4, 1);
1578}
1579
1580/* 1F 1DC: nand[.] ra, rs, rb */
1581static
1582void op_1f_1dc (p405_t *c)
1583{
1584 uint32_t ra;
1585
1586 ra = ~(p405_get_rs (c, c->ir) & p405_get_rb (c, c->ir)) & 0xffffffffUL;
1587
1588 p405_set_ra (c, c->ir, ra);
1589
1590 if (p405_get_ir_rc (c->ir)) {
1591 p405_set_cr0 (c, ra);
1592 }
1593
1594 p405_set_clk (c, 4, 1);
1595}
1596
1597/* 1F 1EB: divw[.] rt, ra, rb */
1598static
1599void op_1f_1eb (p405_t *c)
1600{
1601 int sa, sb;
1602 uint32_t rt, ra, rb;
1603
1604 ra = p405_get_ra (c, c->ir);
1605 rb = p405_get_rb (c, c->ir);
1606
1607 if ((rb == 0) || ((ra == 0x80000000) && (rb == 0xffffffff))) {
1608 p405_set_clk (c, 4, 1);
1609 return;
1610 }
1611
1612 sa = (ra & 0x80000000) != 0;
1613 sb = (rb & 0x80000000) != 0;
1614
1615 if (sa) {
1616 ra = -ra & 0xffffffff;
1617 }
1618
1619 if (sb) {
1620 rb = -rb & 0xffffffff;
1621 }
1622
1623 rt = ra / rb;
1624
1625 if (sa != sb) {
1626 rt = -rt & 0xffffffff;
1627 }
1628
1629 p405_set_rt (c, c->ir, rt);
1630
1631 if (p405_get_ir_rc (c->ir)) {
1632 p405_set_cr0 (c, rt);
1633 }
1634
1635 p405_set_clk (c, 4, 35);
1636}
1637
1638/* 1F 200: mcrxr bf */
1639static
1640void op_1f_200 (p405_t *c)
1641{
1642 unsigned bf;
1643
1644 if (p405_check_reserved (c, 0x007ff801UL)) {
1645 return;
1646 }
1647
1648 bf = p405_get_ir_rt (c->ir) >> 2;
1649
1650 p405_set_crf (c, bf, (p405_get_xer (c) >> 28) & 0x0f);
1651 p405_set_xer (c, p405_get_xer (c) & 0x0fffffffUL);
1652
1653 p405_set_clk (c, 4, 1);
1654}
1655
1656/* 1F 208: subfco[.] rt, ra, rb */
1657static
1658void op_1f_208 (p405_t *c)
1659{
1660 uint32_t rt, s1, s2;
1661
1662 s1 = p405_get_rb (c, c->ir);
1663 s2 = p405_get_ra (c, c->ir);
1664
1665 rt = (s1 - s2) & 0xffffffff;
1666
1667 p405_set_rt (c, c->ir, rt);
1668
1669 p405_set_xer_oflow (c, (rt ^ s1) & (rt ^ s2) & 0x80000000);
1670 p405_set_xer_ca (c, rt <= s1);
1671
1672 if (p405_get_ir_rc (c->ir)) {
1673 p405_set_cr0 (c, rt);
1674 }
1675
1676 p405_set_clk (c, 4, 1);
1677}
1678
1679/* 1F 20A: addco[.] rt, ra, rb */
1680static
1681void op_1f_20a (p405_t *c)
1682{
1683 uint32_t rt, s1, s2;
1684
1685 s1 = p405_get_ra (c, c->ir);
1686 s2 = p405_get_rb (c, c->ir);
1687
1688 rt = (s1 + s2) & 0xffffffff;
1689
1690 p405_set_rt (c, c->ir, rt);
1691
1692 p405_set_xer_oflow (c, (rt ^ s1) & (rt ^ s2) & 0x80000000);
1693 p405_set_xer_ca (c, rt < s1);
1694
1695 if (p405_get_ir_rc (c->ir)) {
1696 p405_set_cr0 (c, rt);
1697 }
1698
1699 p405_set_clk (c, 4, 1);
1700}
1701
1702/* 1F 215: lswx rt, ra0, rb */
1703static
1704void op_1f_215 (p405_t *c)
1705{
1706 p405_op_lsw (c,
1707 p405_get_ir_rt (c->ir), p405_get_ir_ra (c->ir), p405_get_ir_rb (c->ir),
1708 p405_get_ra0 (c, c->ir) + p405_get_rb (c, c->ir), p405_get_xer (c) & 0x7f
1709 );
1710}
1711
1712/* 1F 216: lwbrx rt, ra0, rb */
1713static
1714void op_1f_216 (p405_t *c)
1715{
1716 uint32_t rt, ea;
1717
1718 if (p405_get_ea (c, &ea, 1, 0)) {
1719 return;
1720 }
1721
1722 if (p405_dload32 (c, ea, &rt)) {
1723 return;
1724 }
1725
1726 p405_set_rt (c, c->ir, p405_br32 (rt));
1727
1728 p405_set_clk (c, 4, 1);
1729}
1730
1731/* 1F 217: lfsx */
1732static
1733void op_1f_217 (p405_t *c)
1734{
1735 p405_set_clk (c, 0, 1);
1736 p405_exception_program_fpu (c);
1737}
1738
1739/* 1F 218: srw[.] ra, rs, rb */
1740static
1741void op_1f_218 (p405_t *c)
1742{
1743 uint32_t ra, rb;
1744
1745 rb = p405_get_rb (c, c->ir);
1746
1747 if (rb & 0x20) {
1748 ra = 0;
1749 }
1750 else {
1751 ra = p405_get_rs (c, c->ir) >> (rb & 0x1f);
1752 }
1753
1754 p405_set_ra (c, c->ir, ra);
1755
1756 if (p405_get_ir_rc (c->ir)) {
1757 p405_set_cr0 (c, ra);
1758 }
1759
1760 p405_set_clk (c, 4, 1);
1761}
1762
1763/* 1F 228: subfo[.] rt, ra, rb */
1764static
1765void op_1f_228 (p405_t *c)
1766{
1767 uint32_t rt, s1, s2;
1768
1769 s1 = p405_get_rb (c, c->ir);
1770 s2 = p405_get_ra (c, c->ir);
1771
1772 rt = (s1 - s2) & 0xffffffff;
1773
1774 p405_set_rt (c, c->ir, rt);
1775
1776 p405_set_xer_oflow (c, (rt ^ s1) & (rt ^ s2) & 0x80000000);
1777
1778 if (p405_get_ir_rc (c->ir)) {
1779 p405_set_cr0 (c, rt);
1780 }
1781
1782 p405_set_clk (c, 4, 1);
1783}
1784
1785/* 1F 236: tlbsync */
1786static
1787void op_1f_236 (p405_t *c)
1788{
1789 if (p405_check_reserved (c, 0x03fff801UL)) {
1790 return;
1791 }
1792
1793 p405_set_clk (c, 4, 1);
1794}
1795
1796/* 1F 237: lfsux */
1797static
1798void op_1f_237 (p405_t *c)
1799{
1800 p405_set_clk (c, 0, 1);
1801 p405_exception_program_fpu (c);
1802}
1803
1804/* 1F 255: lswi rt, ra0, nb */
1805static
1806void op_1f_255 (p405_t *c)
1807{
1808 unsigned nb;
1809
1810 nb = p405_get_ir_rb (c->ir);
1811
1812 p405_op_lsw (c,
1813 p405_get_ir_rt (c->ir), p405_get_ir_ra (c->ir), p405_get_ir_ra (c->ir),
1814 p405_get_ra0 (c, c->ir), (nb == 0) ? 32 : nb
1815 );
1816}
1817
1818/* 1F 256: sync */
1819static
1820void op_1f_256 (p405_t *c)
1821{
1822 p405_set_clk (c, 4, 1);
1823}
1824
1825/* 1F 257: lfdx */
1826static
1827void op_1f_257 (p405_t *c)
1828{
1829 p405_set_clk (c, 0, 1);
1830 p405_exception_program_fpu (c);
1831}
1832
1833/* 1F 268: nego[.] rt, ra */
1834static
1835void op_1f_268 (p405_t *c)
1836{
1837 uint32_t rt;
1838
1839 if (p405_check_reserved (c, 0x0000f800)) {
1840 return;
1841 }
1842
1843 rt = -p405_get_ra (c, c->ir) & 0xffffffff;
1844
1845 p405_set_rt (c, c->ir, rt);
1846
1847 p405_set_xer_oflow (c, rt == 0x80000000);
1848
1849 if (p405_get_ir_rc (c->ir)) {
1850 p405_set_cr0 (c, rt);
1851 }
1852
1853 p405_set_clk (c, 4, 1);
1854}
1855
1856/* 1F 277: lfdux */
1857static
1858void op_1f_277 (p405_t *c)
1859{
1860 p405_set_clk (c, 0, 1);
1861 p405_exception_program_fpu (c);
1862}
1863
1864/* 1F 288: subfeo[.] rt, ra, rb */
1865static
1866void op_1f_288 (p405_t *c)
1867{
1868 uint32_t rt, s1, s2, s3;
1869
1870 s1 = p405_get_rb (c, c->ir);
1871 s2 = ~p405_get_ra (c, c->ir);
1872 s3 = p405_get_xer_ca (c);
1873
1874 rt = (s1 + s2 + s3) & 0xffffffff;
1875
1876 p405_set_rt (c, c->ir, rt);
1877
1878 p405_set_xer_oflow (c, (rt ^ s1) & (rt ^ s2) & 0x80000000);
1879 p405_set_xer_ca (c, (rt < s1) || ((rt == s1) && s3));
1880
1881 if (p405_get_ir_rc (c->ir)) {
1882 p405_set_cr0 (c, rt);
1883 }
1884
1885 p405_set_clk (c, 4, 1);
1886}
1887
1888/* 1F 28A: addeo[.] rt, ra, rb */
1889static
1890void op_1f_28a (p405_t *c)
1891{
1892 uint32_t rt, s1, s2, s3;
1893
1894 s1 = p405_get_ra (c, c->ir);
1895 s2 = p405_get_rb (c, c->ir);
1896 s3 = p405_get_xer_ca (c);
1897
1898 rt = (s1 + s2 + s3) & 0xffffffff;
1899
1900 p405_set_rt (c, c->ir, rt);
1901
1902 p405_set_xer_oflow (c, (rt ^ s1) & (rt ^ s2) & 0x80000000);
1903 p405_set_xer_ca (c, (rt < s1) || ((rt == s1) && (s3 > 0)));
1904
1905 if (p405_get_ir_rc (c->ir)) {
1906 p405_set_cr0 (c, rt);
1907 }
1908
1909 p405_set_clk (c, 4, 1);
1910}
1911
1912/* 1F 295: stswx rs, ra0, rb */
1913static
1914void op_1f_295 (p405_t *c)
1915{
1916 p405_op_stsw (c, p405_get_ir_rt (c->ir),
1917 p405_get_ra0 (c, c->ir) + p405_get_rb (c, c->ir), p405_get_xer (c) & 0x7f
1918 );
1919}
1920
1921/* 1F 296: stwbrx rs, ra0, rb */
1922static
1923void op_1f_296 (p405_t *c)
1924{
1925 uint32_t ea;
1926
1927 if (p405_check_reserved (c, 0x01)) {
1928 return;
1929 }
1930
1931 if (p405_get_ea (c, &ea, 1, 0)) {
1932 return;
1933 }
1934
1935 if (p405_dstore32 (c, ea, p405_br32 (p405_get_rs (c, c->ir)))) {
1936 return;
1937 }
1938
1939 p405_set_clk (c, 4, 1);
1940}
1941
1942/* 1F 297: stfsx */
1943static
1944void op_1f_297 (p405_t *c)
1945{
1946 p405_set_clk (c, 0, 1);
1947 p405_exception_program_fpu (c);
1948}
1949
1950/* 1F 2B7: stfsux */
1951static
1952void op_1f_2b7 (p405_t *c)
1953{
1954 p405_set_clk (c, 0, 1);
1955 p405_exception_program_fpu (c);
1956}
1957
1958/* 1F 2C8: subfzeo[.] rt, ra */
1959static
1960void op_1f_2c8 (p405_t *c)
1961{
1962 uint32_t rt, s2, s3;
1963
1964 if (p405_check_reserved (c, 0x0000f800)) {
1965 return;
1966 }
1967
1968 s2 = ~p405_get_ra (c, c->ir);
1969 s3 = p405_get_xer_ca (c);
1970
1971 rt = (0 + s2 + s3) & 0xffffffff;
1972
1973 p405_set_rt (c, c->ir, rt);
1974
1975 p405_set_xer_oflow (c, rt & (rt ^ s2) & 0x80000000);
1976 p405_set_xer_ca (c, (rt == 0) && s3);
1977
1978 if (p405_get_ir_rc (c->ir)) {
1979 p405_set_cr0 (c, rt);
1980 }
1981
1982 p405_set_clk (c, 4, 1);
1983}
1984
1985/* 1F 2CA: addzeo[.] rt, ra */
1986static
1987void op_1f_2ca (p405_t *c)
1988{
1989 uint32_t rt, s1, s2;
1990
1991 if (p405_check_reserved (c, 0x0000f800)) {
1992 return;
1993 }
1994
1995 s1 = p405_get_ra (c, c->ir);
1996 s2 = p405_get_xer_ca (c);
1997
1998 rt = (s1 + s2) & 0xffffffff;
1999
2000 p405_set_rt (c, c->ir, rt);
2001
2002 p405_set_xer_oflow (c, (rt ^ s1) & rt & 0x80000000);
2003 p405_set_xer_ca (c, rt < s1);
2004
2005 if (p405_get_ir_rc (c->ir)) {
2006 p405_set_cr0 (c, rt);
2007 }
2008
2009 p405_set_clk (c, 4, 1);
2010}
2011
2012/* 1F 2D5: stswi rs, ra0, nb */
2013static
2014void op_1f_2d5 (p405_t *c)
2015{
2016 unsigned nb;
2017
2018 nb = p405_get_ir_rb (c->ir);
2019
2020 p405_op_stsw (c, p405_get_ir_rt (c->ir), p405_get_ra0 (c, c->ir),
2021 (nb == 0) ? 32 : nb
2022 );
2023}
2024
2025/* 1F 2D7: stfdx */
2026static
2027void op_1f_2d7 (p405_t *c)
2028{
2029 p405_set_clk (c, 0, 1);
2030 p405_exception_program_fpu (c);
2031}
2032
2033/* 1F 2E8: subfmeo[.] rt, ra */
2034static
2035void op_1f_2e8 (p405_t *c)
2036{
2037 uint32_t rt, s2, s3;
2038
2039 if (p405_check_reserved (c, 0x0000f800)) {
2040 return;
2041 }
2042
2043 s2 = ~p405_get_ra (c, c->ir);
2044 s3 = p405_get_xer_ca (c);
2045
2046 rt = (0xffffffff + s2 + s3) & 0xffffffff;
2047
2048 p405_set_rt (c, c->ir, rt);
2049
2050 p405_set_xer_oflow (c, ~rt & (rt ^ s2) & 0x80000000);
2051 p405_set_xer_ca (c, s2 || s3);
2052
2053 if (p405_get_ir_rc (c->ir)) {
2054 p405_set_cr0 (c, rt);
2055 }
2056
2057 p405_set_clk (c, 4, 1);
2058}
2059
2060/* 1F 2EA: addmeo[.] rt, ra */
2061static
2062void op_1f_2ea (p405_t *c)
2063{
2064 uint32_t rt, s1, s2;
2065
2066 if (p405_check_reserved (c, 0xf800UL)) {
2067 return;
2068 }
2069
2070 s1 = p405_get_ra (c, c->ir);
2071 s2 = p405_get_xer_ca (c);
2072
2073 rt = (s1 + s2 - 1) & 0xffffffff;
2074
2075 p405_set_rt (c, c->ir, rt);
2076
2077 p405_set_xer_oflow (c, (rt ^ s1) & ~rt & 0x80000000);
2078 p405_set_xer_ca (c, (s1 > 0) || (s2 > 0));
2079
2080 if (p405_get_ir_rc (c->ir)) {
2081 p405_set_cr0 (c, rt);
2082 }
2083
2084 p405_set_clk (c, 4, 1);
2085}
2086
2087/* 1F 2EB: mullwo[.] rt, ra, rb */
2088static
2089void op_1f_2eb (p405_t *c)
2090{
2091 uint32_t rt;
2092 uint64_t val1, val2;
2093
2094 val1 = p405_mul (p405_get_ra (c, c->ir), p405_get_rb (c, c->ir));
2095 rt = val1 & 0xffffffff;
2096
2097 p405_set_rt (c, c->ir, rt);
2098
2099 val2 = (rt & 0x80000000) ? (val1 | 0xffffffff00000000ULL) : rt;
2100
2101 p405_set_xer_oflow (c, val1 != val2);
2102
2103 if (p405_get_ir_rc (c->ir)) {
2104 p405_set_cr0 (c, rt);
2105 }
2106
2107 p405_set_clk (c, 4, 5);
2108}
2109
2110/* 1F 2F6: dcba ra0, rb */
2111static
2112void op_1f_2f6 (p405_t *c)
2113{
2114 if (p405_check_reserved (c, 0x03e00001UL)) {
2115 return;
2116 }
2117
2118 p405_set_clk (c, 4, 1);
2119}
2120
2121/* 1F 2F7: stfdux */
2122static
2123void op_1f_2f7 (p405_t *c)
2124{
2125 p405_set_clk (c, 0, 1);
2126 p405_exception_program_fpu (c);
2127}
2128
2129/* 1F 30A: addo[.] rt, ra, rb */
2130static
2131void op_1f_30a (p405_t *c)
2132{
2133 uint32_t rt, s1, s2;
2134
2135 s1 = p405_get_ra (c, c->ir);
2136 s2 = p405_get_rb (c, c->ir);
2137
2138 rt = (s1 + s2) & 0xffffffff;
2139
2140 p405_set_rt (c, c->ir, rt);
2141
2142 p405_set_xer_oflow (c, (rt ^ s1) & (rt ^ s2) & 0x80000000);
2143
2144 if (p405_get_ir_rc (c->ir)) {
2145 p405_set_cr0 (c, rt);
2146 }
2147
2148 p405_set_clk (c, 4, 1);
2149}
2150
2151/* 1F 316: lhbrx rt, ra0, rb */
2152static
2153void op_1f_316 (p405_t *c)
2154{
2155 uint16_t rt;
2156 uint32_t ea;
2157
2158 if (p405_get_ea (c, &ea, 1, 0)) {
2159 return;
2160 }
2161
2162 if (p405_dload16 (c, ea, &rt)) {
2163 return;
2164 }
2165
2166 p405_set_rt (c, c->ir, p405_br16 (rt));
2167
2168 p405_set_clk (c, 4, 1);
2169}
2170
2171/* 1F 318: sraw[.] ra, rs, rb */
2172static
2173void op_1f_318 (p405_t *c)
2174{
2175 unsigned sh;
2176 uint32_t ra, rs, rb;
2177
2178 rs = p405_get_rs (c, c->ir);
2179 rb = p405_get_rb (c, c->ir);
2180
2181 sh = rb & 0x1f;
2182
2183 if (rb & 0x20) {
2184 if (rs & 0x80000000UL) {
2185 ra = 0xffffffffUL;
2186 p405_set_xer_ca (c, 1);
2187 }
2188 else {
2189 ra = 0;
2190 p405_set_xer_ca (c, 0);
2191 }
2192 }
2193 else {
2194 if (rs & 0x80000000UL) {
2195 ra = ((0xffffffff00000000ULL | rs) >> sh) & 0xffffffffUL;
2196 p405_set_xer_ca (c, ((ra << sh) & 0xffffffffUL) != rs);
2197 }
2198 else {
2199 ra = rs >> sh;
2200 p405_set_xer_ca (c, 0);
2201 }
2202 }
2203
2204 p405_set_ra (c, c->ir, ra);
2205
2206 if (p405_get_ir_rc (c->ir)) {
2207 p405_set_cr0 (c, ra);
2208 }
2209
2210 p405_set_clk (c, 4, 1);
2211}
2212
2213/* 1F 338: srawi[.] ra, rs, sh */
2214static
2215void op_1f_338 (p405_t *c)
2216{
2217 unsigned sh;
2218 uint32_t ra, rs;
2219
2220 rs = p405_get_rs (c, c->ir);
2221 sh = p405_get_ir_rb (c->ir);
2222
2223 if (rs & 0x80000000UL) {
2224 ra = ((0xffffffff00000000ULL | rs) >> sh) & 0xffffffffUL;
2225 p405_set_xer_ca (c, ((ra << sh) & 0xffffffffUL) != rs);
2226 }
2227 else {
2228 ra = rs >> sh;
2229 p405_set_xer_ca (c, 0);
2230 }
2231
2232 p405_set_ra (c, c->ir, ra);
2233
2234 if (p405_get_ir_rc (c->ir)) {
2235 p405_set_cr0 (c, ra);
2236 }
2237
2238 p405_set_clk (c, 4, 1);
2239}
2240
2241/* 1F 356: eieio */
2242static
2243void op_1f_356 (p405_t *c)
2244{
2245 if (p405_check_reserved (c, 0x03fff800UL)) {
2246 return;
2247 }
2248
2249 p405_set_clk (c, 4, 1);
2250}
2251
2252/* 1F 392: tlbsx rt, ra0, rb */
2253static
2254void op_1f_392 (p405_t *c)
2255{
2256 int rc;
2257 uint32_t rt, ea;
2258 p405_tlbe_t *ent;
2259
2260 ea = (p405_get_ra0 (c, c->ir) + p405_get_rb (c, c->ir)) & 0xffffffffUL;
2261
2262 rc = p405_get_ir_rc (c->ir);
2263 rt = p405_get_tlb_index (c, ea);
2264 ent = p405_get_tlb_entry_idx (c, rt);
2265
2266 if (rc) {
2267 p405_set_crf (c, 0, p405_get_xer_so (c) ? P405_CR_SO : 0);
2268 }
2269
2270 if ((ent != NULL) && p405_get_tlbe_v (ent)) {
2271 p405_set_rt (c, c->ir, rt);
2272
2273 if (rc) {
2274 p405_set_cr_eq (c, 0, 1);
2275 }
2276 }
2277
2278 p405_set_clk (c, 4, 1);
2279}
2280
2281/* 1F 396: sthbrx rs, ra0, rb */
2282static
2283void op_1f_396 (p405_t *c)
2284{
2285 uint32_t ea;
2286
2287 if (p405_check_reserved (c, 0x01)) {
2288 return;
2289 }
2290
2291 if (p405_get_ea (c, &ea, 1, 0)) {
2292 return;
2293 }
2294
2295 if (p405_dstore16 (c, ea, p405_br16 (p405_get_rs (c, c->ir)))) {
2296 return;
2297 }
2298
2299 p405_set_clk (c, 4, 1);
2300}
2301
2302/* 1F 39A: extsh[.] ra, rs */
2303static
2304void op_1f_39a (p405_t *c)
2305{
2306 uint32_t ra;
2307
2308 if (p405_check_reserved (c, 0xf800UL)) {
2309 return;
2310 }
2311
2312 ra = p405_sext (p405_get_rs (c, c->ir), 16);
2313 p405_set_ra (c, c->ir, ra);
2314
2315 if (c->ir & P405_IR_RC) {
2316 p405_set_cr0 (c, ra);
2317 }
2318
2319 p405_set_clk (c, 4, 1);
2320}
2321
2322/* 1F 3B2: tlbre rt, ra, ws */
2323static
2324void op_1f_3b2 (p405_t *c)
2325{
2326 unsigned ws, ra;
2327
2328 if (p405_check_reserved (c, 0x01)) {
2329 return;
2330 }
2331
2332 if (p405_check_privilege (c)) {
2333 return;
2334 }
2335
2336 ws = p405_get_ir_rb (c->ir);
2337 ra = p405_get_ra (c, c->ir);
2338
2339 if (ws == 1) {
2340 p405_set_rt (c, c->ir, p405_get_tlb_entry_lo (c, ra));
2341 }
2342 else if (ws == 0) {
2343 p405_set_rt (c, c->ir, p405_get_tlb_entry_hi (c, ra) & 0xfffffff0);
2344 p405_set_pid (c, p405_get_tlb_entry_tid (c, ra));
2345 }
2346 else {
2347 p405_op_undefined (c);
2348 return;
2349 }
2350
2351 p405_set_clk (c, 4, 1);
2352}
2353
2354/* 1F 3BA: extsb[.] ra, rs */
2355static
2356void op_1f_3ba (p405_t *c)
2357{
2358 uint32_t ra;
2359
2360 if (p405_check_reserved (c, 0xf800UL)) {
2361 return;
2362 }
2363
2364 ra = p405_sext (p405_get_rs (c, c->ir), 8);
2365 p405_set_ra (c, c->ir, ra);
2366
2367 if (c->ir & P405_IR_RC) {
2368 p405_set_cr0 (c, ra);
2369 }
2370
2371 p405_set_clk (c, 4, 1);
2372}
2373
2374/* 1F 3C6: iccci ra, rb */
2375static
2376void op_1f_3c6 (p405_t *c)
2377{
2378 if (p405_check_reserved (c, 0x03e00001UL)) {
2379 return;
2380 }
2381
2382 p405_set_clk (c, 4, 1);
2383}
2384
2385/* 1F 3CB: divwuo[.] rt, ra, rb */
2386static
2387void op_1f_3cb (p405_t *c)
2388{
2389 uint32_t rt, ra, rb;
2390
2391 ra = p405_get_ra (c, c->ir);
2392 rb = p405_get_rb (c, c->ir);
2393
2394 if (rb == 0) {
2395 p405_set_xer_oflow (c, 1);
2396 p405_set_clk (c, 4, 1);
2397 return;
2398 }
2399
2400 rt = ra / rb;
2401
2402 p405_set_rt (c, c->ir, rt);
2403
2404 p405_set_xer_oflow (c, 0);
2405
2406 if (p405_get_ir_rc (c->ir)) {
2407 p405_set_cr0 (c, rt);
2408 }
2409
2410 p405_set_clk (c, 4, 35);
2411}
2412
2413/* 1F 3D2: tlbwe rs, ra, ws */
2414static
2415void op_1f_3d2 (p405_t *c)
2416{
2417 unsigned ws, rs, ra;
2418
2419 if (p405_check_reserved (c, 0x01)) {
2420 return;
2421 }
2422
2423 if (p405_check_privilege (c)) {
2424 return;
2425 }
2426
2427 ws = p405_get_ir_rb (c->ir);
2428 ra = p405_get_ra (c, c->ir);
2429 rs = p405_get_rs (c, c->ir);
2430
2431 if (ws == 1) {
2432 p405_set_tlb_entry_lo (c, ra, rs);
2433 }
2434 else if (ws == 0) {
2435 p405_set_tlb_entry_hi (c, ra, rs, p405_get_pid (c));
2436 }
2437 else {
2438 p405_op_undefined (c);
2439 return;
2440 }
2441
2442 p405_set_clk (c, 4, 1);
2443}
2444
2445/* 1F 3D6: icbi ra, rb */
2446static
2447void op_1f_3d6 (p405_t *c)
2448{
2449 if (p405_check_reserved (c, 0x03e00001UL)) {
2450 return;
2451 }
2452
2453 p405_set_clk (c, 4, 1);
2454}
2455
2456/* 1F 3EB: divwo[.] rt, ra, rb */
2457static
2458void op_1f_3eb (p405_t *c)
2459{
2460 int sa, sb;
2461 uint32_t rt, ra, rb;
2462
2463 ra = p405_get_ra (c, c->ir);
2464 rb = p405_get_rb (c, c->ir);
2465
2466 if ((rb == 0) || ((ra == 0x80000000) && (rb == 0xffffffff))) {
2467 p405_set_xer_oflow (c, 1);
2468 p405_set_clk (c, 4, 1);
2469 return;
2470 }
2471
2472 sa = (ra & 0x80000000) != 0;
2473 sb = (rb & 0x80000000) != 0;
2474
2475 if (sa) {
2476 ra = -ra & 0xffffffff;
2477 }
2478
2479 if (sb) {
2480 rb = -rb & 0xffffffff;
2481 }
2482
2483 rt = ra / rb;
2484
2485 if (sa != sb) {
2486 rt = -rt & 0xffffffff;
2487 }
2488
2489 p405_set_rt (c, c->ir, rt);
2490
2491 p405_set_xer_oflow (c, 0);
2492
2493 if (p405_get_ir_rc (c->ir)) {
2494 p405_set_cr0 (c, rt);
2495 }
2496
2497 p405_set_clk (c, 4, 35);
2498}
2499
2500/* 1F 3F6: dcbz ra0, rb */
2501static
2502void op_1f_3f6 (p405_t *c)
2503{
2504 unsigned i;
2505 uint32_t ea;
2506
2507 if (p405_check_reserved (c, 0x03e00001UL)) {
2508 return;
2509 }
2510
2511 /* alignment exception if cache block non-cacheable or write-through */
2512
2513 if (p405_get_ea (c, &ea, 1, 0)) {
2514 return;
2515 }
2516
2517 ea &= ~(unsigned long) (P405_CACHE_LINE_SIZE - 1);
2518
2519 i = 0;
2520 while (i < P405_CACHE_LINE_SIZE) {
2521 if (p405_dstore32 (c, ea + i, 0)) {
2522 return;
2523 }
2524
2525 i += 4;
2526 }
2527
2528 p405_set_clk (c, 4, 1);
2529}
2530
2531/* 1F: */
2532static
2533void op_1f (p405_t *c)
2534{
2535 unsigned op2;
2536
2537 op2 = (c->ir >> 1) & 0x3ff;
2538
2539 c->opcodes.op1f[op2] (c);
2540}
2541
2542
2543static
2544p405_opcode_list_t p405_opcodes_1f[] = {
2545 { 0x000, op_1f_000 },
2546 { 0x008, op_1f_008 },
2547 { 0x00a, op_1f_00a },
2548 { 0x00b, op_1f_00b },
2549 { 0x013, op_1f_013 },
2550 { 0x014, op_1f_014 },
2551 { 0x017, op_1f_017 },
2552 { 0x018, op_1f_018 },
2553 { 0x01a, op_1f_01a },
2554 { 0x01c, op_1f_01c },
2555 { 0x020, op_1f_020 },
2556 { 0x028, op_1f_028 },
2557 { 0x036, op_1f_036 },
2558 { 0x037, op_1f_037 },
2559 { 0x03c, op_1f_03c },
2560 { 0x04b, op_1f_04b },
2561 { 0x053, op_1f_053 },
2562 { 0x056, op_1f_056 },
2563 { 0x057, op_1f_057 },
2564 { 0x068, op_1f_068 },
2565 { 0x077, op_1f_077 },
2566 { 0x07c, op_1f_07c },
2567 { 0x083, op_1f_083 },
2568 { 0x086, op_1f_086 },
2569 { 0x088, op_1f_088 },
2570 { 0x08a, op_1f_08a },
2571 { 0x090, op_1f_090 },
2572 { 0x092, op_1f_092 },
2573 { 0x096, op_1f_096 },
2574 { 0x097, op_1f_097 },
2575 { 0x0a3, op_1f_0a3 },
2576 { 0x0b7, op_1f_0b7 },
2577 { 0x0c8, op_1f_0c8 },
2578 { 0x0ca, op_1f_0ca },
2579 { 0x0d7, op_1f_0d7 },
2580 { 0x0e8, op_1f_0e8 },
2581 { 0x0ea, op_1f_0ea },
2582 { 0x0eb, op_1f_0eb },
2583 { 0x0f6, op_1f_0f6 },
2584 { 0x0f7, op_1f_0f7 },
2585 { 0x106, op_1f_106 },
2586 { 0x10a, op_1f_10a },
2587 { 0x116, op_1f_116 },
2588 { 0x117, op_1f_117 },
2589 { 0x11c, op_1f_11c },
2590 { 0x137, op_1f_137 },
2591 { 0x13c, op_1f_13c },
2592 { 0x143, op_1f_143 },
2593 { 0x153, op_1f_153 },
2594 { 0x157, op_1f_157 },
2595 { 0x172, op_1f_172 },
2596 { 0x173, op_1f_173 },
2597 { 0x177, op_1f_177 },
2598 { 0x197, op_1f_197 },
2599 { 0x19c, op_1f_19c },
2600 { 0x1b7, op_1f_1b7 },
2601 { 0x1bc, op_1f_1bc },
2602 { 0x1c3, op_1f_1c3 },
2603 { 0x1c6, op_1f_1c6 },
2604 { 0x1cb, op_1f_1cb },
2605 { 0x1d3, op_1f_1d3 },
2606 { 0x1d6, op_1f_1d6 },
2607 { 0x1dc, op_1f_1dc },
2608 { 0x1eb, op_1f_1eb },
2609 { 0x200, op_1f_200 },
2610 { 0x208, op_1f_208 },
2611 { 0x20a, op_1f_20a },
2612 { 0x215, op_1f_215 },
2613 { 0x216, op_1f_216 },
2614 { 0x217, op_1f_217 },
2615 { 0x218, op_1f_218 },
2616 { 0x228, op_1f_228 },
2617 { 0x236, op_1f_236 },
2618 { 0x237, op_1f_237 },
2619 { 0x255, op_1f_255 },
2620 { 0x256, op_1f_256 },
2621 { 0x257, op_1f_257 },
2622 { 0x268, op_1f_268 },
2623 { 0x277, op_1f_277 },
2624 { 0x288, op_1f_288 },
2625 { 0x28a, op_1f_28a },
2626 { 0x295, op_1f_295 },
2627 { 0x296, op_1f_296 },
2628 { 0x297, op_1f_297 },
2629 { 0x2b7, op_1f_2b7 },
2630 { 0x2c8, op_1f_2c8 },
2631 { 0x2ca, op_1f_2ca },
2632 { 0x2d5, op_1f_2d5 },
2633 { 0x2d7, op_1f_2d7 },
2634 { 0x2e8, op_1f_2e8 },
2635 { 0x2ea, op_1f_2ea },
2636 { 0x2eb, op_1f_2eb },
2637 { 0x2f6, op_1f_2f6 },
2638 { 0x2f7, op_1f_2f7 },
2639 { 0x30a, op_1f_30a },
2640 { 0x316, op_1f_316 },
2641 { 0x318, op_1f_318 },
2642 { 0x338, op_1f_338 },
2643 { 0x356, op_1f_356 },
2644 { 0x392, op_1f_392 },
2645 { 0x396, op_1f_396 },
2646 { 0x39a, op_1f_39a },
2647 { 0x3b2, op_1f_3b2 },
2648 { 0x3ba, op_1f_3ba },
2649 { 0x3c6, op_1f_3c6 },
2650 { 0x3cb, op_1f_3cb },
2651 { 0x3d2, op_1f_3d2 },
2652 { 0x3d6, op_1f_3d6 },
2653 { 0x3eb, op_1f_3eb },
2654 { 0x3f6, op_1f_3f6 },
2655 { 0x000, NULL}
2656};
2657
2658void p405_set_opcode1f (p405_t *c)
2659{
2660 unsigned i;
2661 p405_opcode_list_t *lst;
2662 p405_opcode_f *p;
2663
2664 c->opcodes.op[0x1f] = op_1f;
2665
2666 p = c->opcodes.op1f;
2667
2668 for (i = 0; i < 1024; i++) {
2669 p[i] = p405_op_undefined;
2670 }
2671
2672 lst = p405_opcodes_1f;
2673
2674 while (lst->fct != NULL) {
2675 p[lst->op] = lst->fct;
2676 lst += 1;
2677 }
2678}