fork of PCE focusing on macplus, supporting DaynaPort SCSI network emulation
at master 20 lines 477 B view raw
1# src/chipset/clock/Makefile.inc 2 3rel := src/chipset/clock 4 5DIRS += $(rel) 6DIST += $(rel)/Makefile.inc 7 8CS_CLK_BAS := \ 9 ds1743 \ 10 mc146818a 11 12CS_CLK_SRC := $(foreach f,$(CS_CLK_BAS),$(rel)/$(f).c) 13CS_CLK_OBJ := $(foreach f,$(CS_CLK_BAS),$(rel)/$(f).o) 14CS_CLK_HDR := $(foreach f,$(CS_CLK_BAS),$(rel)/$(f).h) 15 16CLN += $(CS_CLK_OBJ) 17DIST += $(CS_CLK_SRC) $(CS_CLK_HDR) 18 19$(rel)/ds1743.o: $(rel)/ds1743.c $(rel)/ds1743.h 20$(rel)/mc146818a.o: $(rel)/mc146818a.c $(rel)/mc146818a.h