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1/* $OpenBSD: adwmcode.h,v 1.4 2008/06/26 05:42:16 ray Exp $ */
2/* $NetBSD: adwmcode.h,v 1.5 2000/05/27 18:24:51 dante Exp $ */
3
4/*
5 * Generic driver definitions and exported functions for the Advanced
6 * Systems Inc. SCSI controllers
7 *
8 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
9 * All rights reserved.
10 *
11 * Author: Baldassare Dante Profeta <dante@mclink.it>
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef ADW_MCODE_H
36#define ADW_MCODE_H
37
38/******************************************************************************/
39
40#define ADW_MAX_CARRIER 253 /* Max. number of host commands (253) */
41
42/*
43 * ADW_CARRIER must be exactly 16 BYTES
44 * Every adw_carrier structure _MUST_ always be aligned on a 16 bytes boundary
45 */
46struct adw_carrier {
47/* ---------- the microcode wants the field below ---------- */
48 u_int32_t carr_id; /* Carrier ID */
49 u_int32_t carr_ba; /* Carrier Bus Address */
50 u_int32_t areq_ba; /* ADW_SCSI_REQ_Q Bus Address */
51 /*
52 * next_ba [31:4] Carrier Physical Next Pointer
53 *
54 * next_ba [3:1] Reserved Bits
55 * next_ba [0] Done Flag set in Response Queue.
56 */
57 u_int32_t next_ba; /* see next_ba flags below */
58/* ---------- ---------- */
59};
60
61typedef struct adw_carrier ADW_CARRIER;
62
63/*
64 * next_ba flags
65 */
66#define ADW_RQ_DONE 0x00000001
67#define ADW_RQ_GOOD 0x00000002
68#define ADW_CQ_STOPPER 0x00000000
69
70/*
71 * Mask used to eliminate low 4 bits of carrier 'next_ba' field.
72 */
73#define ADW_NEXT_BA_MASK 0xFFFFFFF0
74#define ADW_GET_CARRP(carrp) ((carrp) & ADW_NEXT_BA_MASK)
75
76/*
77 * Bus Address of a Carrier.
78 * ba = base_ba + v_address - base_va
79 */
80#define ADW_CARRIER_BADDR(dmamap, carriers, x) ((dmamap)->dm_segs[0].ds_addr +\
81 (((u_long)x) - ((u_long)(carriers))))
82/*
83 * Virtual Address of a Carrier.
84 * va = base_va + bus_address - base_ba
85 */
86#define ADW_CARRIER_VADDR(sc, x) ((ADW_CARRIER *) \
87 (((u_int8_t *)(sc)->sc_control->carriers) + \
88 ((u_long)x) - \
89 (sc)->sc_dmamap_carrier->dm_segs[0].ds_addr))
90
91/******************************************************************************/
92
93struct adw_mcode {
94 const u_int8_t *mcode_data;
95 const u_int32_t mcode_chksum;
96 const u_int16_t mcode_size;
97};
98
99
100/******************************************************************************/
101
102/*
103 * Fixed locations of microcode operating variables.
104 */
105#define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
106#define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */
107#define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
108#define ADW_MC_VERSION_DATE 0x0038 /* microcode version */
109#define ADW_MC_VERSION_NUM 0x003A /* microcode number */
110#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
111#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
112#define ADW_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
113#define ADW_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
114
115#define ADW_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
116#define ADW_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
117#define ADW_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
118#define ADW_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
119 /*
120 * 4-bit speed SDTR speed name
121 * =========== ===============
122 * 0000b (0x0) SDTR disabled
123 * 0001b (0x1) 5 MHz
124 * 0010b (0x2) 10 MHz
125 * 0011b (0x3) 20 MHz (Ultra)
126 * 0100b (0x4) 40 MHz (LVD/Ultra2)
127 * 0101b (0x5) 80 MHz (LVD2/Ultra3)
128 * 0110b (0x6) Undefined
129 * ...
130 * 1111b (0xF) Undefined
131 */
132#define ADW_MC_CHIP_TYPE 0x009A
133#define ADW_MC_INTRB_CODE 0x009B
134#define ADW_MC_WDTR_ABLE 0x009C
135#define ADW_MC_SDTR_ABLE 0x009E
136#define ADW_MC_TAGQNG_ABLE 0x00A0
137#define ADW_MC_DISC_ENABLE 0x00A2
138#define ADW_MC_IDLE_CMD_STATUS 0x00A4
139#define ADW_MC_IDLE_CMD 0x00A6
140#define ADW_MC_IDLE_CMD_PARAMETER 0x00A8
141#define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC
142#define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE
143#define ADW_MC_DEFAULT_MEM_CFG 0x00B0
144#define ADW_MC_DEFAULT_SEL_MASK 0x00B2
145#define ADW_MC_SDTR_DONE 0x00B6
146#define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0
147#define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0
148#define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100
149#define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
150#define ADW_MC_WDTR_DONE 0x0124
151#define ADW_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
152#define ADW_MC_ICQ 0x0160
153#define ADW_MC_IRQ 0x0164
154#define ADW_MC_PPR_ABLE 0x017A
155
156
157/*
158 * Microcode Control Flags
159 *
160 * Flags set by the Adw Library in RISC variable 'control_flag' (0x122)
161 * and handled by the microcode.
162 */
163#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
164#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
165
166
167/*
168 * ADW_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
169 */
170#define HSHK_CFG_WIDE_XFR 0x8000
171#define HSHK_CFG_RATE 0x0F00
172#define HSHK_CFG_OFFSET 0x001F
173
174#define ADW_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
175#define ADW_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
176#define ADW_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
177#define ADW_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
178
179#define ADW_QC_DATA_CHECK 0x01 /* Require ADW_QC_DATA_OUT set or clear. */
180#define ADW_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
181#define ADW_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
182#define ADW_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
183#define ADW_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request.XXX TBD*/
184
185#define ADW_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
186#define ADW_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
187#define ADW_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
188#define ADW_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
189#define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
190/*
191 * Note: If a Tag Message is to be sent and neither ADW_QSC_HEAD_TAG or
192 * ADW_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
193 */
194#define ADW_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
195#define ADW_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
196
197
198/******************************************************************************/
199
200ADW_CARRIER *AdwInitCarriers(bus_dmamap_t, ADW_CARRIER *);
201
202extern const struct adw_mcode adw_asc3550_mcode_data;
203extern const struct adw_mcode adw_asc38C0800_mcode_data;
204extern const struct adw_mcode adw_asc38C1600_mcode_data;
205/******************************************************************************/
206
207#endif /* ADW_MCODE_H */