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1/* $OpenBSD: if_ure.c,v 1.37 2025/06/04 00:06:17 jsg Exp $ */
2/*-
3 * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org>
4 * Copyright (c) 2020 Jonathon Fletcher <jonathon.fletcher@gmail.com>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include "bpfilter.h"
30#include "vlan.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/sockio.h>
35#include <sys/rwlock.h>
36#include <sys/mbuf.h>
37#include <sys/device.h>
38
39#include <machine/bus.h>
40
41#include <net/if.h>
42#include <net/if_media.h>
43
44#if NBPFILTER > 0
45#include <net/bpf.h>
46#endif
47
48#include <netinet/in.h>
49#include <netinet/if_ether.h>
50
51#include <dev/mii/mii.h>
52#include <dev/mii/miivar.h>
53
54#include <dev/usb/usb.h>
55#include <dev/usb/usbdi.h>
56#include <dev/usb/usbdi_util.h>
57#include <dev/usb/usbdivar.h>
58#include <dev/usb/usbdevs.h>
59
60#include <dev/ic/rtl81x9reg.h>
61#include <dev/usb/if_urereg.h>
62
63#ifdef URE_DEBUG
64#define DPRINTF(x) do { if (uredebug) printf x; } while (0)
65#define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0)
66int uredebug = 0;
67#else
68#define DPRINTF(x)
69#define DPRINTFN(n,x)
70#endif
71
72const struct usb_devno ure_devs[] = {
73 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8156 },
74 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8152B },
75 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8153 },
76 { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB3GIGV1 },
77 { USB_VENDOR_CLEVO, USB_PRODUCT_CLEVO_RTL8153B },
78 { USB_VENDOR_CLUB3D, USB_PRODUCT_CLUB3D_RTL8153 },
79 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_1 },
80 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_2 },
81 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_1 },
82 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_2 },
83 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8153B },
84 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8156B },
85 { USB_VENDOR_IOI, USB_PRODUCT_IOI_RTL8153 },
86 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_DOCK_ETHERNET },
87 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINK },
88 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPLUS },
89 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPRO },
90 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_1 },
91 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_2 },
92 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_3 },
93 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_4 },
94 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_5 },
95 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_6 },
96 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_7 },
97 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_8 },
98 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_9 },
99 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_1 },
100 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_2 },
101 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_3 },
102 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TABLETDOCK },
103 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCK },
104 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCKGEN2 },
105 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3GFXDOCK },
106 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_USBCDOCKGEN2 },
107 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_WIGIGDOCK },
108 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153 },
109 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153B },
110 { USB_VENDOR_LUXSHARE, USB_PRODUCT_LUXSHARE_RTL8153 },
111 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH },
112 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH2 },
113 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_SURFETH },
114 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_WINDEVETH },
115 { USB_VENDOR_NVIDIA, USB_PRODUCT_NVIDIA_TEGRAETH },
116 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8152B },
117 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8153B },
118 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 },
119 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152B },
120 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 },
121 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8156 },
122 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8157 },
123 { USB_VENDOR_SAMSUNG2, USB_PRODUCT_SAMSUNG2_RTL8153 },
124 { USB_VENDOR_TOSHIBA, USB_PRODUCT_TOSHIBA_RTL8153B },
125 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_EU300 },
126 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_1 },
127 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_2 },
128 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8156 },
129 { USB_VENDOR_TTL, USB_PRODUCT_TTL_RTL8153 },
130 { USB_VENDOR_TWINHEAD, USB_PRODUCT_TWINHEAD_RTL8153B },
131 { USB_VENDOR_XIAOMI, USB_PRODUCT_XIAOMI_RTL8152B },
132};
133
134int ure_match(struct device *, void *, void *);
135void ure_attach(struct device *, struct device *, void *);
136int ure_detach(struct device *, int);
137
138struct cfdriver ure_cd = {
139 NULL, "ure", DV_IFNET
140};
141
142const struct cfattach ure_ca = {
143 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach
144};
145
146int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
147 void *, int);
148int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
149 int);
150int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
151 int);
152uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t);
153uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
154uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
155int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
156int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
157int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
158uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
159void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
160uint16_t ure_rtl8157_ocp_reg_read(struct ure_softc *, uint16_t);
161void ure_rtl8157_ocp_reg_write(struct ure_softc *, uint16_t,
162 uint16_t);
163uint32_t ure_ocp_cmd_read(struct ure_softc *, uint16_t, int);
164void ure_ocp_cmd_write(struct ure_softc *, uint16_t, int, uint32_t);
165
166void ure_init(void *);
167void ure_stop(struct ure_softc *);
168void ure_start(struct ifnet *);
169void ure_reset(struct ure_softc *);
170void ure_watchdog(struct ifnet *);
171
172void ure_miibus_statchg(struct device *);
173int ure_miibus_readreg(struct device *, int, int);
174void ure_miibus_writereg(struct device *, int, int, int);
175void ure_lock_mii(struct ure_softc *);
176void ure_unlock_mii(struct ure_softc *);
177
178void ure_decap(struct ure_softc *, struct ure_chain *, uint32_t);
179int ure_encap_txpkt(struct ure_softc *, struct mbuf *, char *,
180 uint32_t);
181int ure_encap_xfer(struct ifnet *, struct ure_softc *,
182 struct ure_chain *);
183void ure_rxcsum(struct ure_rxpkt *, struct mbuf *);
184void ure_rxcsum_v2(struct ure_rxpkt_v2 *, struct mbuf *);
185void ure_rxeof(struct usbd_xfer *, void *, usbd_status);
186void ure_txeof(struct usbd_xfer *, void *, usbd_status);
187int ure_xfer_list_init(struct ure_softc *, struct ure_chain *,
188 uint32_t, int);
189void ure_xfer_list_free(struct ure_softc *, struct ure_chain *, int);
190
191void ure_tick_task(void *);
192void ure_tick(void *);
193
194void ure_ifmedia_init(struct ifnet *);
195int ure_ifmedia_upd(struct ifnet *);
196void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *);
197void ure_add_media_types(struct ure_softc *);
198void ure_link_state(struct ure_softc *);
199int ure_get_link_status(struct ure_softc *);
200void ure_iff(struct ure_softc *);
201void ure_rxvlan(struct ure_softc *);
202int ure_ioctl(struct ifnet *, u_long, caddr_t);
203void ure_rtl8152_init(struct ure_softc *);
204int ure_rtl8153_init(struct ure_softc *);
205int ure_rtl8153b_init(struct ure_softc *);
206int ure_rtl8157_init(struct ure_softc *);
207int ure_rtl8152_nic_reset(struct ure_softc *);
208int ure_rtl8153_nic_reset(struct ure_softc *);
209uint16_t ure_rtl8153_phy_status(struct ure_softc *, int);
210int ure_wait_for_flash(struct ure_softc *);
211void ure_reset_bmu(struct ure_softc *);
212void ure_disable_teredo(struct ure_softc *);
213
214#define URE_SETBIT_1(sc, reg, index, x) \
215 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x))
216#define URE_SETBIT_2(sc, reg, index, x) \
217 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x))
218#define URE_SETBIT_4(sc, reg, index, x) \
219 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x))
220
221#define URE_CLRBIT_1(sc, reg, index, x) \
222 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x))
223#define URE_CLRBIT_2(sc, reg, index, x) \
224 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x))
225#define URE_CLRBIT_4(sc, reg, index, x) \
226 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x))
227
228#define URE_OCP_CMD_SETBIT(sc, addr, type, x) \
229 ure_ocp_cmd_write(sc, addr, type, \
230 ure_ocp_cmd_read(sc, addr, type) | (x))
231
232#define URE_OCP_CMD_CLRBIT(sc, addr, type, x) \
233 ure_ocp_cmd_write(sc, addr, type, \
234 ure_ocp_cmd_read(sc, addr, type) & ~(x))
235
236int
237ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
238 void *buf, int len)
239{
240 usb_device_request_t req;
241 usbd_status err;
242
243 if (usbd_is_dying(sc->ure_udev))
244 return 0;
245
246 if (rw == URE_CTL_WRITE)
247 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
248 else
249 req.bmRequestType = UT_READ_VENDOR_DEVICE;
250 req.bRequest = UR_SET_ADDRESS;
251 USETW(req.wValue, val);
252 USETW(req.wIndex, index);
253 USETW(req.wLength, len);
254
255 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n",
256 rw, val, index, len));
257 err = usbd_do_request(sc->ure_udev, &req, buf);
258 if (err) {
259 DPRINTF(("ure_ctl: error %d\n", err));
260 return -1;
261 }
262
263 return 0;
264}
265
266int
267ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
268 void *buf, int len)
269{
270 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
271}
272
273int
274ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
275 void *buf, int len)
276{
277 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
278}
279
280uint8_t
281ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
282{
283 uint32_t val;
284 uint8_t temp[4];
285 uint8_t shift;
286
287 shift = (reg & 3) << 3;
288 reg &= ~3;
289
290 ure_read_mem(sc, reg, index, &temp, 4);
291 val = UGETDW(temp);
292 val >>= shift;
293
294 return (val & 0xff);
295}
296
297uint16_t
298ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
299{
300 uint32_t val;
301 uint8_t temp[4];
302 uint8_t shift;
303
304 shift = (reg & 2) << 3;
305 reg &= ~3;
306
307 ure_read_mem(sc, reg, index, &temp, 4);
308 val = UGETDW(temp);
309 val >>= shift;
310
311 return (val & 0xffff);
312}
313
314uint32_t
315ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
316{
317 uint8_t temp[4];
318
319 ure_read_mem(sc, reg, index, &temp, 4);
320 return (UGETDW(temp));
321}
322
323int
324ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
325{
326 uint16_t byen;
327 uint8_t temp[4];
328 uint8_t shift;
329
330 byen = URE_BYTE_EN_BYTE;
331 shift = reg & 3;
332 val &= 0xff;
333
334 if (reg & 3) {
335 byen <<= shift;
336 val <<= (shift << 3);
337 reg &= ~3;
338 }
339
340 USETDW(temp, val);
341 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
342}
343
344int
345ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
346{
347 uint16_t byen;
348 uint8_t temp[4];
349 uint8_t shift;
350
351 byen = URE_BYTE_EN_WORD;
352 shift = reg & 2;
353 val &= 0xffff;
354
355 if (reg & 2) {
356 byen <<= shift;
357 val <<= (shift << 3);
358 reg &= ~3;
359 }
360
361 USETDW(temp, val);
362 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
363}
364
365int
366ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
367{
368 uint8_t temp[4];
369
370 USETDW(temp, val);
371 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
372}
373
374static inline uint16_t
375ure_phy_read(struct ure_softc *sc, uint16_t addr)
376{
377 return sc->ure_phy_read(sc, addr);
378}
379
380static inline void
381ure_phy_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
382{
383 return sc->ure_phy_write(sc, addr, data);
384}
385
386uint16_t
387ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
388{
389 uint16_t reg;
390
391 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
392 reg = (addr & 0x0fff) | 0xb000;
393
394 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
395}
396
397void
398ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
399{
400 uint16_t reg;
401
402 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
403 reg = (addr & 0x0fff) | 0xb000;
404
405 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
406}
407
408uint16_t
409ure_rtl8157_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
410{
411 int i;
412
413 for (i = 0; i < 10; i++) {
414 if (!(ure_read_2(sc, URE_USB_TGPHY_CMD, URE_MCU_TYPE_USB) &
415 URE_TGPHY_CMD_BUSY))
416 break;
417 usbd_delay_ms(sc->ure_udev, 1);
418 }
419 if (i == 10) {
420 printf("%s: PHY read timeout\n", sc->ure_dev.dv_xname);
421 return (0xffff);
422 }
423
424 ure_write_2(sc, URE_USB_TGPHY_ADDR, URE_MCU_TYPE_USB, addr);
425 ure_write_2(sc, URE_USB_TGPHY_CMD, URE_MCU_TYPE_USB,
426 URE_TGPHY_CMD_BUSY);
427
428 for (i = 0; i < 10; i++) {
429 if (!(ure_read_2(sc, URE_USB_TGPHY_CMD, URE_MCU_TYPE_USB) &
430 URE_TGPHY_CMD_BUSY))
431 break;
432 usbd_delay_ms(sc->ure_udev, 1);
433 }
434 if (i == 10) {
435 printf("%s: PHY read timeout\n", sc->ure_dev.dv_xname);
436 return (0xffff);
437 }
438
439 return (ure_read_2(sc, URE_USB_TGPHY_DATA, URE_MCU_TYPE_USB));
440}
441
442void
443ure_rtl8157_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
444{
445 int i;
446
447 ure_write_2(sc, URE_USB_TGPHY_DATA, URE_MCU_TYPE_USB, data);
448
449 ure_write_2(sc, URE_USB_TGPHY_ADDR, URE_MCU_TYPE_USB, addr);
450 ure_write_2(sc, URE_USB_TGPHY_CMD, URE_MCU_TYPE_USB,
451 URE_TGPHY_CMD_BUSY | URE_TGPHY_CMD_WRITE);
452
453 for (i = 0; i < 10; i++) {
454 if (!(ure_read_2(sc, URE_USB_TGPHY_CMD, URE_MCU_TYPE_USB) &
455 URE_TGPHY_CMD_BUSY))
456 break;
457 usbd_delay_ms(sc->ure_udev, 1);
458 }
459 if (i == 10)
460 printf("%s: PHY write timeout\n", sc->ure_dev.dv_xname);
461}
462
463uint32_t
464ure_ocp_cmd_read(struct ure_softc *sc, uint16_t addr, int type)
465{
466 uint16_t cmd;
467 int i;
468
469 cmd = (type == URE_CMD_TYPE_BMU) ? URE_CMD_BMU : URE_CMD_IP;
470
471 for (i = 0; i < 10; i++) {
472 if (!(ure_read_2(sc, URE_USB_CMD, URE_MCU_TYPE_USB) &
473 URE_CMD_BUSY))
474 break;
475 usbd_delay_ms(sc->ure_udev, 1);
476 }
477 if (i == 10)
478 printf("%s: timeout waiting for read command\n",
479 sc->ure_dev.dv_xname);
480
481 ure_write_2(sc, URE_USB_CMD_ADDR, URE_MCU_TYPE_USB, addr);
482 ure_write_2(sc, URE_USB_CMD, URE_MCU_TYPE_USB, cmd | URE_CMD_BUSY);
483
484 for (i = 0; i < 10; i++) {
485 if (!(ure_read_2(sc, URE_USB_CMD, URE_MCU_TYPE_USB) &
486 URE_CMD_BUSY))
487 break;
488 usbd_delay_ms(sc->ure_udev, 1);
489 }
490 if (i == 10)
491 printf("%s: timeout waiting for read command\n",
492 sc->ure_dev.dv_xname);
493
494 return (ure_read_4(sc, URE_USB_CMD_DATA, URE_MCU_TYPE_USB));
495}
496
497void
498ure_ocp_cmd_write(struct ure_softc *sc, uint16_t addr, int type, uint32_t data)
499{
500 uint16_t cmd;
501 int i;
502
503 cmd = (type == URE_CMD_TYPE_BMU) ? URE_CMD_BMU : URE_CMD_IP;
504
505 for (i = 0; i < 10; i++) {
506 if (!(ure_read_2(sc, URE_USB_CMD, URE_MCU_TYPE_USB) &
507 URE_CMD_BUSY))
508 break;
509 usbd_delay_ms(sc->ure_udev, 1);
510 }
511 if (i == 10)
512 printf("%s: timeout waiting for write command\n",
513 sc->ure_dev.dv_xname);
514
515 ure_write_4(sc, URE_USB_CMD_DATA, URE_MCU_TYPE_USB, data);
516
517 ure_write_2(sc, URE_USB_CMD_ADDR, URE_MCU_TYPE_USB, addr);
518 ure_write_2(sc, URE_USB_CMD, URE_MCU_TYPE_USB,
519 cmd | URE_CMD_BUSY | URE_CMD_WRITE);
520}
521
522int
523ure_miibus_readreg(struct device *dev, int phy, int reg)
524{
525 struct ure_softc *sc = (void *)dev;
526 uint16_t val;
527
528 if (usbd_is_dying(sc->ure_udev))
529 return 0;
530
531 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */
532 if (reg == RL_GMEDIASTAT)
533 return ure_read_1(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA);
534
535 ure_lock_mii(sc);
536 val = ure_phy_read(sc, URE_OCP_BASE_MII + reg * 2);
537 ure_unlock_mii(sc);
538
539 return val; /* letoh16? */
540}
541
542void
543ure_miibus_writereg(struct device *dev, int phy, int reg, int val)
544{
545 struct ure_softc *sc = (void *)dev;
546
547 ure_lock_mii(sc);
548 ure_phy_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */
549 ure_unlock_mii(sc);
550}
551
552void
553ure_miibus_statchg(struct device *dev)
554{
555 struct ure_softc *sc = (void *)dev;
556 struct mii_data *mii = &sc->ure_mii;
557 struct ifnet *ifp = &sc->ure_ac.ac_if;
558
559 if ((ifp->if_flags & IFF_RUNNING) == 0)
560 return;
561
562 sc->ure_flags &= ~URE_FLAG_LINK;
563 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
564 (IFM_ACTIVE | IFM_AVALID)) {
565 switch (IFM_SUBTYPE(mii->mii_media_active)) {
566 case IFM_10_T:
567 case IFM_100_TX:
568 sc->ure_flags |= URE_FLAG_LINK;
569 break;
570 case IFM_1000_T:
571 if ((sc->ure_flags & URE_FLAG_8152) != 0)
572 break;
573 sc->ure_flags |= URE_FLAG_LINK;
574 break;
575 default:
576 break;
577 }
578 }
579
580 /* Lost link, do nothing. */
581 if ((sc->ure_flags & URE_FLAG_LINK) == 0)
582 return;
583
584 /*
585 * After a link change the media settings are getting reset on the
586 * hardware, and need to be re-initialized again for communication
587 * to continue work.
588 */
589 ure_ifmedia_init(ifp);
590}
591
592void
593ure_ifmedia_init(struct ifnet *ifp)
594{
595 struct ure_softc *sc = ifp->if_softc;
596 uint32_t reg = 0;
597
598 /* Set MAC address. */
599 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
600 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
601 sc->ure_ac.ac_enaddr, 8);
602 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
603
604 if (!(sc->ure_flags & URE_FLAG_8152)) {
605 if (sc->ure_flags & (URE_FLAG_8156B | URE_FLAG_8157))
606 URE_CLRBIT_2(sc, URE_USB_RX_AGGR_NUM, URE_MCU_TYPE_USB,
607 URE_RX_AGGR_NUM_MASK);
608
609 reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu);
610 if (sc->ure_flags & URE_FLAG_8157)
611 reg -= sizeof(struct ure_rxpkt_v2) + URE_8157_BUF_ALIGN;
612 else
613 reg -= sizeof(struct ure_rxpkt) + URE_RX_BUF_ALIGN;
614
615 if (sc->ure_flags &
616 (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B |
617 URE_FLAG_8157)) {
618 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB,
619 (sc->ure_flags & URE_FLAG_8157) ?
620 reg / URE_8157_BUF_ALIGN : reg / URE_RX_BUF_ALIGN);
621
622 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB,
623 (sc->ure_flags & URE_FLAG_8153B) ? 158 : 80);
624 ure_write_2(sc, URE_USB_PM_CTRL_STATUS,
625 URE_MCU_TYPE_USB, 1875);
626
627 if (sc->ure_udev->speed == USB_SPEED_HIGH) {
628 reg = ure_read_2(sc, URE_USB_L1_CTRL,
629 URE_MCU_TYPE_USB);
630 reg &= ~0x0f;
631 ure_write_2(sc, URE_USB_L1_CTRL,
632 URE_MCU_TYPE_USB, reg | 0x01);
633 }
634 } else {
635 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB,
636 reg / 4);
637 switch (sc->ure_udev->speed) {
638 case USB_SPEED_SUPER:
639 reg = URE_COALESCE_SUPER / 8;
640 break;
641 case USB_SPEED_HIGH:
642 reg = URE_COALESCE_HIGH / 8;
643 break;
644 default:
645 reg = URE_COALESCE_SLOW / 8;
646 break;
647 }
648 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB,
649 reg);
650 }
651
652 if (sc->ure_chip & URE_CHIP_VER_7420) {
653 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4,
654 URE_MCU_TYPE_PLA, URE_IDLE_SPDWN_EN);
655 }
656
657 if ((sc->ure_chip & URE_CHIP_VER_6010) ||
658 (sc->ure_flags & URE_FLAG_8156B)) {
659 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB,
660 URE_FC_PATCH_TASK);
661 usbd_delay_ms(sc->ure_udev, 1);
662 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB,
663 URE_FC_PATCH_TASK);
664 }
665 }
666
667 /* Reset the packet filter. */
668 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
669 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
670
671 /* Enable transmit and receive. */
672 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE);
673
674 if (sc->ure_flags &
675 (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B | URE_FLAG_8157)) {
676 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB,
677 URE_OWN_UPDATE | URE_OWN_CLEAR);
678 }
679
680 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
681}
682
683int
684ure_ifmedia_upd(struct ifnet *ifp)
685{
686 struct ure_softc *sc = ifp->if_softc;
687 struct mii_data *mii = &sc->ure_mii;
688 struct ifmedia *ifm = &sc->ure_ifmedia;
689 int anar, gig, err, reg;
690
691 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B | URE_FLAG_8157)) {
692 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
693 return (EINVAL);
694
695 if (!(sc->ure_chip & URE_CHIP_VER_7420)) {
696 reg = ure_phy_read(sc, URE_OCP_10GBT_CTRL);
697 if (reg == 0xffff)
698 return (EINVAL);
699 reg &= ~URE_ADV_2500TFDX;
700 }
701 if (sc->ure_flags & URE_FLAG_8157)
702 reg &= ~URE_ADV_5000TFDX;
703
704 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
705 gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
706
707 switch (IFM_SUBTYPE(ifm->ifm_media)) {
708 case IFM_AUTO:
709 if (!(sc->ure_chip & URE_CHIP_VER_7420))
710 reg |= URE_ADV_2500TFDX;
711 if (sc->ure_flags & URE_FLAG_8157)
712 reg |= URE_ADV_5000TFDX;
713 break;
714 case IFM_5000_T:
715 reg |= URE_ADV_2500TFDX | URE_ADV_5000TFDX;
716 ifp->if_baudrate = IF_Gbps(5);
717 break;
718 case IFM_2500_T:
719 reg |= URE_ADV_2500TFDX;
720 ifp->if_baudrate = IF_Mbps(2500);
721 break;
722 case IFM_1000_T:
723 ifp->if_baudrate = IF_Gbps(1);
724 break;
725 case IFM_100_TX:
726 anar &= ~(ANAR_10_FD | ANAR_10);
727 gig = 0;
728 ifp->if_baudrate = IF_Mbps(100);
729 break;
730 case IFM_10_T:
731 anar &= ~(ANAR_TX_FD | ANAR_TX);
732 gig = 0;
733 ifp->if_baudrate = IF_Mbps(10);
734 break;
735 default:
736 printf("%s: unsupported media type\n",
737 sc->ure_dev.dv_xname);
738 return (EINVAL);
739 }
740
741 ure_phy_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2,
742 anar | ANAR_PAUSE_ASYM | ANAR_FC);
743 ure_phy_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig);
744 if (!(sc->ure_chip & URE_CHIP_VER_7420))
745 ure_phy_write(sc, URE_OCP_10GBT_CTRL, reg);
746 ure_phy_write(sc, URE_OCP_BASE_MII + MII_BMCR,
747 BMCR_AUTOEN | BMCR_STARTNEG);
748
749 return (0);
750 }
751
752 if (mii->mii_instance) {
753 struct mii_softc *miisc;
754 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
755 PHY_RESET(miisc);
756 }
757
758 err = mii_mediachg(mii);
759 if (err == ENXIO)
760 return (0);
761 else
762 return (err);
763}
764
765void
766ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
767{
768 struct ure_softc *sc = ifp->if_softc;
769 struct mii_data *mii = &sc->ure_mii;
770 uint16_t status = 0;
771
772 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B | URE_FLAG_8157)) {
773 ifmr->ifm_status = IFM_AVALID;
774 if (ure_get_link_status(sc)) {
775 ifmr->ifm_status |= IFM_ACTIVE;
776 ifmr->ifm_active = IFM_ETHER;
777 status = ure_read_2(sc, URE_PLA_PHYSTATUS,
778 URE_MCU_TYPE_PLA);
779 if ((status & URE_PHYSTATUS_FDX) ||
780 (status & URE_PHYSTATUS_2500MBPS) ||
781 (status & URE_PHYSTATUS_5000MBPS))
782 ifmr->ifm_active |= IFM_FDX;
783 else
784 ifmr->ifm_active |= IFM_HDX;
785 if (status & URE_PHYSTATUS_10MBPS)
786 ifmr->ifm_active |= IFM_10_T;
787 else if (status & URE_PHYSTATUS_100MBPS)
788 ifmr->ifm_active |= IFM_100_TX;
789 else if (status & URE_PHYSTATUS_1000MBPS)
790 ifmr->ifm_active |= IFM_1000_T;
791 else if (status & URE_PHYSTATUS_2500MBPS)
792 ifmr->ifm_active |= IFM_2500_T;
793 else if (status & URE_PHYSTATUS_5000MBPS)
794 ifmr->ifm_active |= IFM_5000_T;
795 }
796 return;
797 }
798
799 mii_pollstat(mii);
800 ifmr->ifm_active = mii->mii_media_active;
801 ifmr->ifm_status = mii->mii_media_status;
802}
803
804void
805ure_add_media_types(struct ure_softc *sc)
806{
807 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
808 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
809 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
810 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0,
811 NULL);
812 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
813 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0,
814 NULL);
815 if (!(sc->ure_chip & URE_CHIP_VER_7420)) {
816 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T, 0, NULL);
817 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX,
818 0, NULL);
819 }
820 if (sc->ure_flags & URE_FLAG_8157) {
821 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_5000_T, 0, NULL);
822 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_5000_T | IFM_FDX,
823 0, NULL);
824 }
825}
826
827void
828ure_link_state(struct ure_softc *sc)
829{
830 struct ifnet *ifp = &sc->ure_ac.ac_if;
831 int link = LINK_STATE_DOWN;
832
833 if (ure_get_link_status(sc)) {
834 link = LINK_STATE_UP;
835 /* Enable transmit and receive. */
836 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA,
837 URE_CR_RE | URE_CR_TE);
838 }
839
840 if (ifp->if_link_state != link) {
841 ifp->if_link_state = link;
842 if_link_state_change(ifp);
843 }
844}
845
846int
847ure_get_link_status(struct ure_softc *sc)
848{
849 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
850 URE_PHYSTATUS_LINK) {
851 sc->ure_flags |= URE_FLAG_LINK;
852 return (1);
853 } else {
854 sc->ure_flags &= ~URE_FLAG_LINK;
855 return (0);
856 }
857}
858
859void
860ure_iff(struct ure_softc *sc)
861{
862 struct ifnet *ifp = &sc->ure_ac.ac_if;
863 struct ether_multi *enm;
864 struct ether_multistep step;
865 uint32_t hashes[2] = { 0, 0 };
866 uint32_t hash;
867 uint32_t rxmode;
868
869 if (usbd_is_dying(sc->ure_udev))
870 return;
871
872 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA);
873 rxmode &= ~URE_RCR_ACPT_ALL;
874 ifp->if_flags &= ~IFF_ALLMULTI;
875
876 /*
877 * Always accept frames destined to our station address.
878 * Always accept broadcast frames.
879 */
880 rxmode |= URE_RCR_APM | URE_RCR_AB;
881
882 if (ifp->if_flags & IFF_PROMISC || sc->ure_ac.ac_multirangecnt > 0) {
883 ifp->if_flags |= IFF_ALLMULTI;
884 rxmode |= URE_RCR_AM;
885 if (ifp->if_flags & IFF_PROMISC)
886 rxmode |= URE_RCR_AAP;
887 hashes[0] = hashes[1] = 0xffffffff;
888 } else {
889 rxmode |= URE_RCR_AM;
890
891 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm);
892 while (enm != NULL) {
893 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN)
894 >> 26;
895 if (hash < 32)
896 hashes[0] |= (1 << hash);
897 else
898 hashes[1] |= (1 << (hash - 32));
899
900 ETHER_NEXT_MULTI(step, enm);
901 }
902
903 hash = swap32(hashes[0]);
904 hashes[0] = swap32(hashes[1]);
905 hashes[1] = hash;
906 }
907
908 ure_write_mem(sc, URE_PLA_MAR, URE_MCU_TYPE_PLA | URE_BYTE_EN_DWORD,
909 hashes, sizeof(hashes));
910 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
911}
912
913void
914ure_rxvlan(struct ure_softc *sc)
915{
916 struct ifnet *ifp = &sc->ure_ac.ac_if;
917 uint16_t reg;
918
919 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B | URE_FLAG_8157)) {
920 reg = ure_read_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA);
921 reg &= ~(URE_INNER_VLAN | URE_OUTER_VLAN);
922 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)
923 reg |= (URE_INNER_VLAN | URE_OUTER_VLAN);
924 ure_write_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA, reg);
925 } else {
926 reg = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA);
927 reg &= ~URE_CPCR_RX_VLAN;
928 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)
929 reg |= URE_CPCR_RX_VLAN;
930 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, reg);
931 }
932}
933
934void
935ure_reset(struct ure_softc *sc)
936{
937 int i;
938
939 if (sc->ure_flags & URE_FLAG_8157)
940 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA,
941 URE_CR_TE | URE_CR_RE);
942 else if (sc->ure_flags & URE_FLAG_8156) {
943 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_TE);
944 URE_CLRBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB,
945 BMU_RESET_EP_IN);
946 URE_SETBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
947 URE_CDC_ECM_EN);
948 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE);
949 URE_SETBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB,
950 BMU_RESET_EP_IN);
951 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
952 URE_CDC_ECM_EN);
953 } else {
954 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
955
956 for (i = 0; i < URE_TIMEOUT; i++) {
957 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
958 URE_CR_RST))
959 break;
960 DELAY(100);
961 }
962 if (i == URE_TIMEOUT)
963 printf("%s: reset never completed\n",
964 sc->ure_dev.dv_xname);
965 }
966}
967
968void
969ure_watchdog(struct ifnet *ifp)
970{
971 struct ure_softc *sc = ifp->if_softc;
972 struct ure_chain *c;
973 usbd_status err;
974 int i, s;
975
976 ifp->if_timer = 0;
977
978 if (usbd_is_dying(sc->ure_udev))
979 return;
980
981 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP))
982 return;
983
984 sc = ifp->if_softc;
985 s = splnet();
986
987 ifp->if_oerrors++;
988 DPRINTF(("%s: watchdog timeout\n", sc->ure_dev.dv_xname));
989
990 for (i = 0; i < URE_TX_LIST_CNT; i++) {
991 c = &sc->ure_cdata.ure_tx_chain[i];
992 if (c->uc_cnt > 0) {
993 usbd_get_xfer_status(c->uc_xfer, NULL, NULL, NULL,
994 &err);
995 ure_txeof(c->uc_xfer, c, err);
996 }
997 }
998
999 if (ifq_is_oactive(&ifp->if_snd))
1000 ifq_restart(&ifp->if_snd);
1001 splx(s);
1002}
1003
1004void
1005ure_init(void *xsc)
1006{
1007 struct ure_softc *sc = xsc;
1008 struct ure_chain *c;
1009 struct ifnet *ifp = &sc->ure_ac.ac_if;
1010 usbd_status err;
1011 int s, i, error;
1012
1013 s = splnet();
1014
1015 /* Cancel pending I/O. */
1016 ure_stop(sc);
1017
1018 if (sc->ure_flags & URE_FLAG_8152)
1019 error = ure_rtl8152_nic_reset(sc);
1020 else
1021 error = ure_rtl8153_nic_reset(sc);
1022
1023 if (error != 0) {
1024 splx(s);
1025 return;
1026 }
1027
1028 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_rx_chain,
1029 sc->ure_rxbufsz, URE_RX_LIST_CNT) == ENOBUFS) {
1030 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname);
1031 splx(s);
1032 return;
1033 }
1034
1035 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_tx_chain,
1036 sc->ure_txbufsz, URE_TX_LIST_CNT) == ENOBUFS) {
1037 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname);
1038 splx(s);
1039 return;
1040 }
1041
1042 /* Initialize the SLIST we are using for the multiple tx buffers */
1043 SLIST_INIT(&sc->ure_cdata.ure_tx_free);
1044 for (i = 0; i < URE_TX_LIST_CNT; i++)
1045 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free,
1046 &sc->ure_cdata.ure_tx_chain[i], uc_list);
1047
1048 /* Setup MAC address, and enable TX/RX. */
1049 ure_ifmedia_init(ifp);
1050
1051 /* Load the multicast filter. */
1052 ure_iff(sc);
1053
1054 /* Open RX and TX pipes. */
1055 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX],
1056 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]);
1057 if (err) {
1058 printf("%s: open rx pipe failed: %s\n",
1059 sc->ure_dev.dv_xname, usbd_errstr(err));
1060 splx(s);
1061 return;
1062 }
1063
1064 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX],
1065 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]);
1066 if (err) {
1067 printf("%s: open tx pipe failed: %s\n",
1068 sc->ure_dev.dv_xname, usbd_errstr(err));
1069 splx(s);
1070 return;
1071 }
1072
1073 /* Start up the receive pipe. */
1074 for (i = 0; i < URE_RX_LIST_CNT; i++) {
1075 c = &sc->ure_cdata.ure_rx_chain[i];
1076 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX],
1077 c, c->uc_buf, c->uc_bufmax,
1078 USBD_SHORT_XFER_OK | USBD_NO_COPY,
1079 USBD_NO_TIMEOUT, ure_rxeof);
1080 usbd_transfer(c->uc_xfer);
1081 }
1082
1083 ure_ifmedia_upd(ifp);
1084
1085 /* Indicate we are up and running. */
1086 sc->ure_flags &= ~URE_FLAG_LINK;
1087 ifp->if_flags |= IFF_RUNNING;
1088 ifq_clr_oactive(&ifp->if_snd);
1089
1090 timeout_add_sec(&sc->ure_stat_ch, 1);
1091
1092 splx(s);
1093}
1094
1095void
1096ure_start(struct ifnet *ifp)
1097{
1098 struct ure_softc *sc = ifp->if_softc;
1099 struct ure_cdata *cd = &sc->ure_cdata;
1100 struct ure_chain *c;
1101 struct mbuf *m = NULL;
1102 uint32_t descsize, new_buflen;
1103 int s, mlen;
1104
1105 if (!(sc->ure_flags & URE_FLAG_LINK) ||
1106 (ifp->if_flags & (IFF_RUNNING|IFF_UP)) !=
1107 (IFF_RUNNING|IFF_UP)) {
1108 return;
1109 }
1110
1111 s = splnet();
1112
1113 c = SLIST_FIRST(&cd->ure_tx_free);
1114 while (c != NULL) {
1115 m = ifq_deq_begin(&ifp->if_snd);
1116 if (m == NULL)
1117 break;
1118
1119 mlen = m->m_pkthdr.len;
1120
1121 descsize = (sc->ure_flags & URE_FLAG_8157) ?
1122 sizeof(struct ure_txpkt_v2) : sizeof(struct ure_txpkt);
1123 /* Discard packet larger than buffer. */
1124 if (mlen + descsize >= c->uc_bufmax) {
1125 ifq_deq_commit(&ifp->if_snd, m);
1126 m_freem(m);
1127 ifp->if_oerrors++;
1128 continue;
1129 }
1130
1131 /*
1132 * If packet larger than remaining space, send buffer and
1133 * continue.
1134 */
1135 new_buflen = roundup(c->uc_buflen,
1136 (sc->ure_flags & URE_FLAG_8157) ?
1137 URE_8157_BUF_ALIGN : URE_TX_BUF_ALIGN);
1138 if (new_buflen + descsize + mlen >= c->uc_bufmax) {
1139 ifq_deq_rollback(&ifp->if_snd, m);
1140 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list);
1141 if (ure_encap_xfer(ifp, sc, c)) {
1142 SLIST_INSERT_HEAD(&cd->ure_tx_free, c,
1143 uc_list);
1144 break;
1145 }
1146 c = SLIST_FIRST(&cd->ure_tx_free);
1147 continue;
1148 }
1149
1150 /* Append packet to current buffer. */
1151 mlen = ure_encap_txpkt(sc, m, c->uc_buf + new_buflen,
1152 c->uc_bufmax - new_buflen);
1153 if (mlen <= 0) {
1154 ifq_deq_rollback(&ifp->if_snd, m);
1155 break;
1156 }
1157
1158 ifq_deq_commit(&ifp->if_snd, m);
1159 c->uc_cnt += 1;
1160 c->uc_buflen = new_buflen + mlen;
1161
1162#if NBPFILTER > 0
1163 if (ifp->if_bpf)
1164 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
1165#endif
1166
1167 m_freem(m);
1168 }
1169
1170 if (c != NULL) {
1171 /* Send current buffer unless empty */
1172 if (c->uc_buflen > 0 && c->uc_cnt > 0) {
1173 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list);
1174 if (ure_encap_xfer(ifp, sc, c)) {
1175 SLIST_INSERT_HEAD(&cd->ure_tx_free, c,
1176 uc_list);
1177 }
1178 c = SLIST_FIRST(&cd->ure_tx_free);
1179 }
1180 }
1181
1182 ifp->if_timer = 5;
1183 if (c == NULL)
1184 ifq_set_oactive(&ifp->if_snd);
1185 splx(s);
1186}
1187
1188void
1189ure_tick(void *xsc)
1190{
1191 struct ure_softc *sc = xsc;
1192
1193 if (sc == NULL)
1194 return;
1195
1196 if (usbd_is_dying(sc->ure_udev))
1197 return;
1198
1199 usb_add_task(sc->ure_udev, &sc->ure_tick_task);
1200}
1201
1202void
1203ure_stop(struct ure_softc *sc)
1204{
1205 struct ure_cdata *cd;
1206 struct ifnet *ifp;
1207 usbd_status err;
1208
1209 ure_reset(sc);
1210
1211 ifp = &sc->ure_ac.ac_if;
1212 ifp->if_timer = 0;
1213 ifp->if_flags &= ~IFF_RUNNING;
1214 ifq_clr_oactive(&ifp->if_snd);
1215
1216 timeout_del(&sc->ure_stat_ch);
1217 sc->ure_flags &= ~URE_FLAG_LINK;
1218
1219 if (sc->ure_ep[URE_ENDPT_RX] != NULL) {
1220 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]);
1221 if (err) {
1222 printf("%s: close rx pipe failed: %s\n",
1223 sc->ure_dev.dv_xname, usbd_errstr(err));
1224 }
1225 sc->ure_ep[URE_ENDPT_RX] = NULL;
1226 }
1227
1228 if (sc->ure_ep[URE_ENDPT_TX] != NULL) {
1229 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]);
1230 if (err) {
1231 printf("%s: close tx pipe failed: %s\n",
1232 sc->ure_dev.dv_xname, usbd_errstr(err));
1233 }
1234 sc->ure_ep[URE_ENDPT_TX] = NULL;
1235 }
1236
1237 cd = &sc->ure_cdata;
1238 ure_xfer_list_free(sc, cd->ure_rx_chain, URE_RX_LIST_CNT);
1239 ure_xfer_list_free(sc, cd->ure_tx_chain, URE_TX_LIST_CNT);
1240}
1241
1242int
1243ure_xfer_list_init(struct ure_softc *sc, struct ure_chain *ch,
1244 uint32_t bufsize, int listlen)
1245{
1246 struct ure_chain *c;
1247 int i;
1248
1249 for (i = 0; i < listlen; i++) {
1250 c = &ch[i];
1251 c->uc_sc = sc;
1252 c->uc_idx = i;
1253 c->uc_buflen = 0;
1254 c->uc_bufmax = bufsize;
1255 c->uc_cnt = 0;
1256 if (c->uc_xfer == NULL) {
1257 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev);
1258 if (c->uc_xfer == NULL)
1259 return (ENOBUFS);
1260 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, c->uc_bufmax);
1261 if (c->uc_buf == NULL) {
1262 usbd_free_xfer(c->uc_xfer);
1263 c->uc_xfer = NULL;
1264 return (ENOBUFS);
1265 }
1266 }
1267 }
1268
1269 return (0);
1270}
1271
1272void
1273ure_xfer_list_free(struct ure_softc *sc, struct ure_chain *ch, int listlen)
1274{
1275 int i;
1276
1277 for (i = 0; i < listlen; i++) {
1278 if (ch[i].uc_buf != NULL) {
1279 ch[i].uc_buf = NULL;
1280 }
1281 ch[i].uc_cnt = 0;
1282 if (ch[i].uc_xfer != NULL) {
1283 usbd_free_xfer(ch[i].uc_xfer);
1284 ch[i].uc_xfer = NULL;
1285 }
1286 }
1287}
1288
1289void
1290ure_rtl8152_init(struct ure_softc *sc)
1291{
1292 uint32_t pwrctrl;
1293
1294 /* Disable ALDPS. */
1295 ure_phy_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
1296 URE_DIS_SDSAVE);
1297 usbd_delay_ms(sc->ure_udev, 20);
1298
1299 if (sc->ure_chip & URE_CHIP_VER_4C00)
1300 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
1301 URE_LED_MODE_MASK);
1302
1303 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT);
1304 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB,
1305 URE_RESUME_INDICATE);
1306
1307 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
1308 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
1309 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
1310 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
1311 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
1312 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
1313 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
1314 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
1315 URE_SPDWN_LINKCHG_MSK);
1316
1317 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET);
1318
1319 /* Enable Rx aggregation. */
1320 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
1321 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1322}
1323
1324int
1325ure_rtl8153_init(struct ure_softc *sc)
1326{
1327 uint16_t reg;
1328 uint8_t u1u2[8];
1329 int i;
1330
1331 memset(u1u2, 0x00, sizeof(u1u2));
1332 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2,
1333 sizeof(u1u2));
1334
1335 for (i = 0; i < 500; i++) {
1336 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1337 URE_AUTOLOAD_DONE)
1338 break;
1339 usbd_delay_ms(sc->ure_udev, 20);
1340 }
1341 if (i == 500) {
1342 printf("%s: timeout waiting for chip autoload\n",
1343 sc->ure_dev.dv_xname);
1344 return (ETIMEDOUT);
1345 }
1346
1347 ure_rtl8153_phy_status(sc, 0);
1348
1349 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1350 URE_CHIP_VER_5C20)) {
1351 ure_phy_write(sc, URE_OCP_ADC_CFG,
1352 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1353 }
1354
1355 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON);
1356
1357 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1358
1359 if (sc->ure_chip & URE_CHIP_VER_5C10) {
1360 reg = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1361 reg &= ~URE_PWD_DN_SCALE_MASK;
1362 reg |= URE_PWD_DN_SCALE(96);
1363 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, reg);
1364
1365 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB,
1366 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1367 } else if (sc->ure_chip & URE_CHIP_VER_5C20) {
1368 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA,
1369 URE_ECM_ALDPS);
1370 }
1371 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1372 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB))
1373 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB,
1374 URE_DYNAMIC_BURST);
1375 else
1376 URE_CLRBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB,
1377 URE_DYNAMIC_BURST);
1378 }
1379
1380 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC);
1381
1382 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN);
1383
1384 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
1385 URE_LED_MODE_MASK);
1386
1387 if ((sc->ure_chip & URE_CHIP_VER_5C10) &&
1388 sc->ure_udev->speed != USB_SPEED_SUPER)
1389 reg = URE_LPM_TIMER_500MS;
1390 else
1391 reg = URE_LPM_TIMER_500US;
1392 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1393 URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM | reg);
1394
1395 reg = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1396 reg &= ~URE_SEN_VAL_MASK;
1397 reg |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1398 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, reg);
1399
1400 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1401
1402 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,
1403 URE_PWR_EN | URE_PHASE2_EN);
1404 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1405
1406 memset(u1u2, 0xff, sizeof(u1u2));
1407 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2,
1408 sizeof(u1u2));
1409
1410 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0);
1411 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 0);
1412 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 0);
1413 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0);
1414
1415 /* Enable Rx aggregation. */
1416 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
1417 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1418
1419 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET);
1420
1421 return (0);
1422}
1423
1424int
1425ure_rtl8153b_init(struct ure_softc *sc)
1426{
1427 uint16_t reg;
1428 int i;
1429
1430 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1431 URE_CLRBIT_1(sc, URE_USB_ECM_OP, URE_MCU_TYPE_USB,
1432 URE_EN_ALL_SPEED);
1433 ure_write_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 0);
1434 URE_SETBIT_2(sc, URE_USB_ECM_OPTION, URE_MCU_TYPE_USB,
1435 URE_BYPASS_MAC_RESET);
1436
1437 if (sc->ure_flags & URE_FLAG_8156B)
1438 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,
1439 URE_RX_DETECT8);
1440 }
1441
1442 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN);
1443
1444 if (sc->ure_flags & URE_FLAG_8156B) {
1445 if (ure_wait_for_flash(sc) != 0)
1446 return (ETIMEDOUT);
1447 }
1448
1449 for (i = 0; i < 500; i++) {
1450 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1451 URE_AUTOLOAD_DONE)
1452 break;
1453 usbd_delay_ms(sc->ure_udev, 20);
1454 }
1455 if (i == 500) {
1456 printf("%s: timeout waiting for chip autoload\n",
1457 sc->ure_dev.dv_xname);
1458 return (ETIMEDOUT);
1459 }
1460
1461 ure_rtl8153_phy_status(sc, 0);
1462 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON);
1463
1464 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1465
1466 /* MSC timer, 32760 ms. */
1467 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 4095);
1468
1469 if (!(sc->ure_flags & URE_FLAG_8153B)) {
1470 /* U1/U2/L1 idle timer, 500 us. */
1471 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500);
1472 }
1473
1474 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN);
1475 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1476
1477 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,
1478 URE_UPS_EN | URE_USP_PREWAKE);
1479 URE_CLRBIT_1(sc, URE_USB_MISC_2, URE_MCU_TYPE_USB,
1480 URE_UPS_FORCE_PWR_DOWN | URE_UPS_NO_UPS);
1481
1482 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA,
1483 URE_UPCOMING_RUNTIME_D3);
1484 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA,
1485 URE_LINK_CHG_EVENT);
1486 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA,
1487 URE_LINK_CHANGE_FLAG);
1488
1489 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1490 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA,
1491 URE_LINK_OFF_WAKE_EN);
1492 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1493
1494 if (sc->ure_flags & URE_FLAG_8153B) {
1495 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA);
1496 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1497 URE_PHYSTATUS_LINK)
1498 reg |= URE_CUR_LINK_OK;
1499 else
1500 reg &= ~URE_CUR_LINK_OK;
1501 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA,
1502 reg | URE_POLL_LINK_CHG);
1503 }
1504
1505 if (sc->ure_udev->speed == USB_SPEED_SUPER) {
1506 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB,
1507 LPM_U1U2_EN);
1508 }
1509
1510 if (sc->ure_flags & URE_FLAG_8156B) {
1511 URE_CLRBIT_2(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_SLOT_EN);
1512 URE_SETBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA,
1513 URE_FLOW_CTRL_EN);
1514
1515 /* Enable fc timer and set timer to 600 ms. */
1516 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB,
1517 URE_CTRL_TIMER_EN | 75);
1518
1519 reg = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB);
1520 if (!(ure_read_2(sc, URE_PLA_POL_GPIO_CTRL, URE_MCU_TYPE_PLA) &
1521 URE_DACK_DET_EN))
1522 reg |= URE_FLOW_CTRL_PATCH_2;
1523 reg &= ~URE_AUTO_SPEEDUP;
1524 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, reg);
1525
1526 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB,
1527 URE_FC_PATCH_TASK);
1528 }
1529
1530 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1531 /* MAC clock speed down. */
1532 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1533 URE_PLA_MCU_SPDWN_EN);
1534
1535 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA);
1536 reg &= ~URE_CUR_LINK_OK;
1537 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1538 URE_PHYSTATUS_LINK)
1539 reg |= URE_CUR_LINK_OK;
1540 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA,
1541 reg | URE_POLL_LINK_CHG);
1542 } else
1543 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1544 URE_MAC_CLK_SPDWN_EN);
1545
1546 /* Enable Rx aggregation. */
1547 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
1548 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1549
1550 if (sc->ure_flags & URE_FLAG_8156)
1551 URE_SETBIT_1(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB,
1552 URE_ACT_ODMA);
1553
1554 if (!(sc->ure_flags & URE_FLAG_8153B)) {
1555 /*
1556 * Select force mode through 0xa5b4 bit 15
1557 * 0: MDIO force mode
1558 * 1: MMD force mode
1559 */
1560 ure_phy_write(sc, 0xa5b4,
1561 ure_phy_read(sc, 0xa5b4) & ~0x8000);
1562 }
1563
1564 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET);
1565
1566 return (0);
1567}
1568
1569int
1570ure_rtl8157_init(struct ure_softc *sc)
1571{
1572 uint16_t reg;
1573 int i;
1574
1575 URE_SETBIT_1(sc, 0xcffe, URE_MCU_TYPE_USB, 0x0008);
1576 URE_CLRBIT_1(sc, 0xd3ca, URE_MCU_TYPE_USB, 0x0001);
1577 URE_CLRBIT_1(sc, URE_USB_ECM_OP, URE_MCU_TYPE_USB, URE_EN_ALL_SPEED);
1578 URE_SETBIT_2(sc, URE_USB_ECM_OPTION, URE_MCU_TYPE_USB,
1579 URE_BYPASS_MAC_RESET);
1580 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_RX_DETECT8);
1581
1582 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN);
1583
1584 for (i = 0; i < 500; i++) {
1585 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1586 URE_AUTOLOAD_DONE)
1587 break;
1588 usbd_delay_ms(sc->ure_udev, 20);
1589 }
1590 if (i == 500) {
1591 printf("%s: timeout waiting for chip autoload\n",
1592 sc->ure_dev.dv_xname);
1593 return (ETIMEDOUT);
1594 }
1595
1596 if (ure_wait_for_flash(sc) != 0)
1597 return (ETIMEDOUT);
1598
1599 ure_rtl8153_phy_status(sc, 0);
1600 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON);
1601
1602 URE_OCP_CMD_CLRBIT(sc, URE_USB_U2P3_CTRL2, URE_CMD_TYPE_IP,
1603 URE_U2P3_CTRL2_ENABLE);
1604
1605 /* Disable interrupt mitigation. */
1606 URE_CLRBIT_1(sc, 0xcf04, URE_MCU_TYPE_USB, 0x87);
1607
1608 URE_CLRBIT_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB,
1609 URE_RG_PWRDN_EN | URE_ALL_SPEED_OFF);
1610
1611 /* Enable auto speed up. */
1612 URE_SETBIT_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, URE_AUTO_SPEEDUP);
1613
1614 /* MSC timer = 4095 * 8ms = 32760 ms. */
1615 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 4095);
1616
1617 /* U1/U2/L1 idle timer, 500 us. */
1618 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500);
1619
1620 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN);
1621 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1622 URE_CLRBIT_1(sc, URE_USB_MISC_2, URE_MCU_TYPE_USB, 0x02);
1623
1624 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA,
1625 URE_UPCOMING_RUNTIME_D3);
1626 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA,
1627 URE_LINK_CHG_EVENT);
1628 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA,
1629 URE_LINK_CHANGE_FLAG);
1630
1631 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1632 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA,
1633 URE_LINK_OFF_WAKE_EN);
1634 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1635
1636 URE_CLRBIT_2(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_SLOT_EN);
1637 URE_SETBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, URE_FLOW_CTRL_EN);
1638
1639 /* Enable fc timer and set timer to 600 ms. */
1640 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB,
1641 URE_CTRL_TIMER_EN | 75);
1642
1643 reg = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB);
1644 reg &= ~URE_AUTO_SPEEDUP;
1645 if (!(ure_read_2(sc, URE_PLA_POL_GPIO_CTRL, URE_MCU_TYPE_PLA) &
1646 URE_DACK_DET_EN))
1647 reg |= URE_FLOW_CTRL_PATCH_2;
1648 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, reg);
1649
1650 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1651
1652 /* Disable bypass_turn_off_clk_in_aldps. */
1653 URE_CLRBIT_1(sc, 0xd3c8, URE_MCU_TYPE_PLA, 0x01);
1654
1655 /* MAC clock speed down. */
1656 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1657 URE_PLA_MCU_SPDWN_EN);
1658
1659 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA);
1660 reg &= ~URE_CUR_LINK_OK;
1661 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1662 URE_PHYSTATUS_LINK)
1663 reg |= URE_CUR_LINK_OK;
1664 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA,
1665 reg | URE_POLL_LINK_CHG);
1666
1667 /* Enable Rx aggregation. */
1668 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
1669 URE_RX_AGG_DISABLE | 0x0400);
1670
1671 /* Disable Rx zero len. */
1672 URE_OCP_CMD_CLRBIT(sc, 0x2300, URE_CMD_TYPE_BMU, 0x00000008);
1673
1674 URE_CLRBIT_1(sc, 0xd4ae, URE_MCU_TYPE_USB, 0x02);
1675
1676 reg = ure_phy_read(sc, 0xa5b4);
1677 if (reg == 0xffff)
1678 return (EINVAL);
1679 ure_phy_write(sc, 0xa5b4, reg & ~0x8000);
1680
1681 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET);
1682
1683 return (0);
1684}
1685
1686int
1687ure_rtl8152_nic_reset(struct ure_softc *sc)
1688{
1689 uint32_t rx_fifo1, rx_fifo2;
1690 int i;
1691
1692 /* Disable ALDPS. */
1693 ure_phy_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
1694 URE_DIS_SDSAVE);
1695 usbd_delay_ms(sc->ure_udev, 20);
1696
1697 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
1698
1699 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1700 ure_disable_teredo(sc);
1701 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1702 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
1703
1704 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
1705 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
1706 for (i = 0; i < URE_TIMEOUT; i++) {
1707 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1708 URE_LINK_LIST_READY)
1709 break;
1710 usbd_delay_ms(sc->ure_udev, 1);
1711 }
1712 if (i == URE_TIMEOUT) {
1713 printf("%s: timeout waiting for OOB control\n",
1714 sc->ure_dev.dv_xname);
1715 return (ETIMEDOUT);
1716 }
1717 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL);
1718 for (i = 0; i < URE_TIMEOUT; i++) {
1719 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1720 URE_LINK_LIST_READY)
1721 break;
1722 usbd_delay_ms(sc->ure_udev, 1);
1723 }
1724 if (i == URE_TIMEOUT) {
1725 printf("%s: timeout waiting for OOB control\n",
1726 sc->ure_dev.dv_xname);
1727 return (ETIMEDOUT);
1728 }
1729
1730 ure_reset(sc);
1731
1732 /* Configure Rx FIFO threshold. */
1733 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
1734 URE_RXFIFO_THR1_NORMAL);
1735 if (sc->ure_udev->speed == USB_SPEED_FULL) {
1736 rx_fifo1 = URE_RXFIFO_THR2_FULL;
1737 rx_fifo2 = URE_RXFIFO_THR3_FULL;
1738 } else {
1739 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
1740 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
1741 }
1742 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
1743 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
1744
1745 /* Configure Tx FIFO threshold. */
1746 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
1747 URE_TXFIFO_THR_NORMAL);
1748
1749 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
1750 URE_TX_AGG_MAX_THRESHOLD);
1751 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
1752 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
1753 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
1754
1755 ure_rxvlan(sc);
1756 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA,
1757 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1758 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO);
1759
1760 /* Enable ALDPS. */
1761 ure_phy_write(sc, URE_OCP_ALDPS_CONFIG,
1762 URE_ENPWRSAVE | URE_ENPDNPS | URE_LINKENA | URE_DIS_SDSAVE);
1763
1764 return (0);
1765}
1766
1767int
1768ure_rtl8153_nic_reset(struct ure_softc *sc)
1769{
1770 struct ifnet *ifp = &sc->ure_ac.ac_if;
1771 uint32_t reg = 0;
1772 uint8_t u1u2[8] = { 0 };
1773 int i;
1774
1775 switch (sc->ure_flags & URE_FLAG_CHIP_MASK) {
1776 case URE_FLAG_8153B:
1777 case URE_FLAG_8156:
1778 case URE_FLAG_8156B:
1779 case URE_FLAG_8157:
1780 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB,
1781 LPM_U1U2_EN);
1782 break;
1783 default:
1784 memset(u1u2, 0x00, sizeof(u1u2));
1785 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES,
1786 u1u2, sizeof(u1u2));
1787 break;
1788 }
1789 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1790
1791 /* Disable ALDPS. */
1792 ure_phy_write(sc, URE_OCP_POWER_CFG,
1793 ure_phy_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
1794 for (i = 0; i < 20; i++) {
1795 usbd_delay_ms(sc->ure_udev, 1);
1796 if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA) & 0x0100)
1797 break;
1798 }
1799
1800 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1801 ure_disable_teredo(sc);
1802
1803 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
1804
1805 ure_reset(sc);
1806 ure_reset_bmu(sc);
1807
1808 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
1809 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
1810
1811 if (!(sc->ure_flags &
1812 (URE_FLAG_8156 | URE_FLAG_8156B | URE_FLAG_8157))) {
1813 for (i = 0; i < URE_TIMEOUT; i++) {
1814 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1815 URE_LINK_LIST_READY)
1816 break;
1817 usbd_delay_ms(sc->ure_udev, 1);
1818 }
1819 if (i == URE_TIMEOUT) {
1820 printf("%s: timeout waiting for OOB control\n",
1821 sc->ure_dev.dv_xname);
1822 return (ETIMEDOUT);
1823 }
1824 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1825 URE_RE_INIT_LL);
1826 for (i = 0; i < URE_TIMEOUT; i++) {
1827 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1828 URE_LINK_LIST_READY)
1829 break;
1830 usbd_delay_ms(sc->ure_udev, 1);
1831 }
1832 if (i == URE_TIMEOUT) {
1833 printf("%s: timeout waiting for OOB control\n",
1834 sc->ure_dev.dv_xname);
1835 return (ETIMEDOUT);
1836 }
1837 }
1838
1839 ure_rxvlan(sc);
1840
1841 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA,
1842 URE_FRAMELEN(ifp->if_mtu));
1843 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA,
1844 (sc->ure_flags & URE_FLAG_8157) ? MTPS_MAX : MTPS_JUMBO);
1845
1846 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B | URE_FLAG_8157)) {
1847 ure_write_2(sc, URE_PLA_RX_FIFO_FULL, URE_MCU_TYPE_PLA,
1848 (sc->ure_flags & URE_FLAG_8156) ? 1024 : 512);
1849 ure_write_2(sc, URE_PLA_RX_FIFO_EMPTY, URE_MCU_TYPE_PLA,
1850 (sc->ure_flags & URE_FLAG_8156) ? 2048 : 1024);
1851
1852 /* Tx share fifo free credit full threshold. */
1853 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 8);
1854 ure_write_2(sc, URE_PLA_TXFIFO_FULL, URE_MCU_TYPE_PLA, 128);
1855
1856 if (sc->ure_flags & URE_FLAG_8156)
1857 URE_SETBIT_2(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB,
1858 URE_ACT_ODMA);
1859
1860 /* FIFO settings */
1861 reg = ure_read_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA);
1862 reg &= ~URE_RXFIFO_FULL_MASK;
1863 ure_write_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA,
1864 reg | 0x0008);
1865
1866 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1867 URE_PLA_MCU_SPDWN_EN);
1868
1869 if (!(sc->ure_flags & URE_FLAG_8157))
1870 URE_CLRBIT_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB,
1871 URE_RG_PWRDN_EN | URE_ALL_SPEED_OFF);
1872
1873 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB,
1874 0x00600400);
1875 } else {
1876 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,
1877 URE_TCR0_AUTO_FIFO);
1878 ure_reset(sc);
1879
1880 /* Configure Rx FIFO threshold. */
1881 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
1882 URE_RXFIFO_THR1_NORMAL);
1883 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA,
1884 URE_RXFIFO_THR2_NORMAL);
1885 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA,
1886 URE_RXFIFO_THR3_NORMAL);
1887
1888 /* Configure Tx FIFO threshold. */
1889 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
1890 URE_TXFIFO_THR_NORMAL2);
1891
1892 if (sc->ure_flags & URE_FLAG_8153B) {
1893 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB,
1894 URE_RX_THR_B);
1895
1896 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3,
1897 URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN);
1898 } else {
1899 URE_SETBIT_1(sc, URE_PLA_CONFIG6, URE_MCU_TYPE_PLA,
1900 URE_LANWAKE_CLR_EN);
1901 URE_CLRBIT_1(sc, URE_PLA_LWAKE_CTRL_REG,
1902 URE_MCU_TYPE_PLA, URE_LANWAKE_PIN);
1903 URE_CLRBIT_2(sc, URE_USB_SSPHYLINK1, URE_MCU_TYPE_USB,
1904 URE_DELAY_PHY_PWR_CHG);
1905 }
1906 }
1907
1908 /* Enable ALDPS. */
1909 ure_phy_write(sc, URE_OCP_POWER_CFG,
1910 ure_phy_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS);
1911
1912 if (sc->ure_flags & URE_FLAG_8157) {
1913 /* Clear SDR. */
1914 URE_SETBIT_1(sc, 0xd378, URE_MCU_TYPE_USB, 0x0080);
1915 URE_CLRBIT_2(sc, 0xcd06, URE_MCU_TYPE_USB, 0x8000);
1916 }
1917 if ((sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) ||
1918 (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)))
1919 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,
1920 URE_U2P3_ENABLE);
1921
1922 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) {
1923 if (sc->ure_udev->speed == USB_SPEED_SUPER)
1924 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB,
1925 LPM_U1U2_EN);
1926 } else if (!(sc->ure_flags & URE_FLAG_8157)) {
1927 memset(u1u2, 0xff, sizeof(u1u2));
1928 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES,
1929 u1u2, sizeof(u1u2));
1930 }
1931
1932 return (0);
1933}
1934
1935uint16_t
1936ure_rtl8153_phy_status(struct ure_softc *sc, int desired)
1937{
1938 uint16_t reg;
1939 int i;
1940
1941 for (i = 0; i < 500; i++) {
1942 reg = ure_phy_read(sc, URE_OCP_PHY_STATUS) &
1943 URE_PHY_STAT_MASK;
1944 if (desired) {
1945 if (reg == desired)
1946 break;
1947 } else {
1948 if (reg == URE_PHY_STAT_LAN_ON ||
1949 reg == URE_PHY_STAT_PWRDN ||
1950 reg == URE_PHY_STAT_EXT_INIT)
1951 break;
1952 }
1953 usbd_delay_ms(sc->ure_udev, 20);
1954 }
1955 if (i == 500)
1956 printf("%s: timeout waiting for phy to stabilize\n",
1957 sc->ure_dev.dv_xname);
1958
1959 return reg;
1960}
1961
1962int
1963ure_wait_for_flash(struct ure_softc *sc)
1964{
1965 int i;
1966
1967 if ((ure_read_2(sc, URE_PLA_GPHY_CTRL, URE_MCU_TYPE_PLA) &
1968 URE_GPHY_FLASH) &&
1969 !(ure_read_2(sc, URE_USB_GPHY_CTRL, URE_MCU_TYPE_USB) &
1970 URE_BYPASS_FLASH)) {
1971 for (i = 0; i < 100; i++) {
1972 if (ure_read_2(sc, URE_USB_GPHY_CTRL,
1973 URE_MCU_TYPE_USB) & URE_GPHY_PATCH_DONE)
1974 break;
1975 usbd_delay_ms(sc->ure_udev, 1);
1976 }
1977 if (i == 100) {
1978 printf("%s: timeout waiting for loading flash\n",
1979 sc->ure_dev.dv_xname);
1980 return (ETIMEDOUT);
1981 }
1982 }
1983
1984 return (0);
1985}
1986
1987void
1988ure_reset_bmu(struct ure_softc *sc)
1989{
1990 uint8_t reg;
1991
1992 if (sc->ure_flags & URE_FLAG_8157) {
1993 URE_OCP_CMD_SETBIT(sc, 0x2350, URE_CMD_TYPE_BMU, 0x00000002);
1994 URE_OCP_CMD_SETBIT(sc, 0x2360, URE_CMD_TYPE_BMU, 0x00000001);
1995 URE_OCP_CMD_SETBIT(sc, 0x2350, URE_CMD_TYPE_BMU, 0x00000001);
1996 URE_OCP_CMD_SETBIT(sc, 0x2450, URE_CMD_TYPE_BMU, 0x00000002);
1997 URE_OCP_CMD_SETBIT(sc, 0x2460, URE_CMD_TYPE_BMU, 0x00000001);
1998 URE_OCP_CMD_SETBIT(sc, 0x2450, URE_CMD_TYPE_BMU, 0x00000001);
1999 } else {
2000 reg = ure_read_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB);
2001 reg &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2002 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg);
2003 reg |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2004 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg);
2005 }
2006}
2007
2008void
2009ure_disable_teredo(struct ure_softc *sc)
2010{
2011 if (sc->ure_flags &
2012 (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B | URE_FLAG_8157))
2013 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff);
2014 else {
2015 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
2016 URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK |
2017 URE_OOB_TEREDO_EN);
2018 }
2019 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE);
2020 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
2021 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
2022}
2023
2024int
2025ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2026{
2027 struct ure_softc *sc = ifp->if_softc;
2028 struct ifreq *ifr = (struct ifreq *)data;
2029 int s, error = 0;
2030
2031 s = splnet();
2032
2033 switch (cmd) {
2034 case SIOCSIFADDR:
2035 ifp->if_flags |= IFF_UP;
2036 if (!(ifp->if_flags & IFF_RUNNING))
2037 ure_init(sc);
2038 break;
2039
2040 case SIOCSIFFLAGS:
2041 if (ifp->if_flags & IFF_UP) {
2042 if (ifp->if_flags & IFF_RUNNING)
2043 error = ENETRESET;
2044 else
2045 ure_init(sc);
2046 } else {
2047 if (ifp->if_flags & IFF_RUNNING)
2048 ure_stop(sc);
2049 }
2050 break;
2051
2052 case SIOCGIFMEDIA:
2053 case SIOCSIFMEDIA:
2054 if (sc->ure_flags &
2055 (URE_FLAG_8156 | URE_FLAG_8156B | URE_FLAG_8157))
2056 error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd);
2057 else
2058 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media,
2059 cmd);
2060 break;
2061
2062 default:
2063 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data);
2064 }
2065
2066 if (error == ENETRESET) {
2067 if (ifp->if_flags & IFF_RUNNING)
2068 ure_iff(sc);
2069 error = 0;
2070 }
2071
2072 splx(s);
2073
2074 return (error);
2075}
2076
2077int
2078ure_match(struct device *parent, void *match, void *aux)
2079{
2080 struct usb_attach_arg *uaa = aux;
2081
2082 if (uaa->iface == NULL || uaa->configno != 1)
2083 return (UMATCH_NONE);
2084
2085 return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ?
2086 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE);
2087}
2088
2089void
2090ure_attach(struct device *parent, struct device *self, void *aux)
2091{
2092 struct ure_softc *sc = (struct ure_softc *)self;
2093 struct usb_attach_arg *uaa = aux;
2094 usb_interface_descriptor_t *id;
2095 usb_endpoint_descriptor_t *ed;
2096 u_char eaddr[8]; /* 4byte padded */
2097 struct ifnet *ifp;
2098 int i, mii_flags = 0, s;
2099 uint16_t ver;
2100
2101 sc->ure_udev = uaa->device;
2102 sc->ure_iface = uaa->iface;
2103
2104 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc,
2105 USB_TASK_TYPE_GENERIC);
2106
2107 id = usbd_get_interface_descriptor(sc->ure_iface);
2108
2109 for (i = 0; i < id->bNumEndpoints; i++) {
2110 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i);
2111 if (!ed) {
2112 printf("%s: couldn't get ep %d\n",
2113 sc->ure_dev.dv_xname, i);
2114 return;
2115 }
2116 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
2117 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
2118 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress;
2119 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
2120 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
2121 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress;
2122 }
2123 }
2124
2125 sc->ure_txbufsz = URE_TX_BUFSZ;
2126 sc->ure_rxbufsz = URE_8153_RX_BUFSZ;
2127
2128 s = splnet();
2129
2130 sc->ure_phyno = 0;
2131 sc->ure_phy_read = ure_ocp_reg_read;
2132 sc->ure_phy_write = ure_ocp_reg_write;
2133 printf("%s: ", sc->ure_dev.dv_xname);
2134
2135 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
2136 switch (ver) {
2137 case 0x1030:
2138 sc->ure_flags = URE_FLAG_8157;
2139 sc->ure_txbufsz = URE_8156_TX_BUFSZ;
2140 sc->ure_phy_read = ure_rtl8157_ocp_reg_read;
2141 sc->ure_phy_write = ure_rtl8157_ocp_reg_write;
2142 printf("RTL8157 (0x1030)");
2143 break;
2144 case 0x4c00:
2145 sc->ure_flags = URE_FLAG_8152;
2146 sc->ure_rxbufsz = URE_8152_RX_BUFSZ;
2147 sc->ure_chip |= URE_CHIP_VER_4C00;
2148 printf("RTL8152 (0x4c00)");
2149 break;
2150 case 0x4c10:
2151 sc->ure_flags = URE_FLAG_8152;
2152 sc->ure_rxbufsz = URE_8152_RX_BUFSZ;
2153 sc->ure_chip |= URE_CHIP_VER_4C10;
2154 printf("RTL8152 (0x4c10)");
2155 break;
2156 case 0x5c00:
2157 sc->ure_chip |= URE_CHIP_VER_5C00;
2158 printf("RTL8153 (0x5c00)");
2159 break;
2160 case 0x5c10:
2161 sc->ure_chip |= URE_CHIP_VER_5C10;
2162 printf("RTL8153 (0x5c10)");
2163 break;
2164 case 0x5c20:
2165 sc->ure_chip |= URE_CHIP_VER_5C20;
2166 printf("RTL8153 (0x5c20)");
2167 break;
2168 case 0x5c30:
2169 sc->ure_chip |= URE_CHIP_VER_5C30;
2170 printf("RTL8153 (0x5c30)");
2171 break;
2172 case 0x6000:
2173 sc->ure_flags = URE_FLAG_8153B;
2174 printf("RTL8153B (0x6000)");
2175 break;
2176 case 0x6010:
2177 sc->ure_flags = URE_FLAG_8153B;
2178 printf("RTL8153B (0x6010)");
2179 break;
2180 case 0x7020:
2181 sc->ure_flags = URE_FLAG_8156;
2182 sc->ure_txbufsz = URE_8156_TX_BUFSZ;
2183 printf("RTL8156 (0x7020)");
2184 break;
2185 case 0x7030:
2186 sc->ure_flags = URE_FLAG_8156;
2187 sc->ure_txbufsz = URE_8156_TX_BUFSZ;
2188 printf("RTL8156 (0x7030)");
2189 break;
2190 case 0x7410:
2191 sc->ure_flags = URE_FLAG_8156B;
2192 sc->ure_txbufsz = URE_8156_TX_BUFSZ;
2193 printf("RTL8156B (0x7410)");
2194 break;
2195 case 0x7420:
2196 sc->ure_flags = URE_FLAG_8156B;
2197 sc->ure_chip = URE_CHIP_VER_7420;
2198 printf("RTL8153D (0x7420)");
2199 break;
2200 default:
2201 printf(", unknown ver %02x", ver);
2202 break;
2203 }
2204
2205 switch (sc->ure_flags & URE_FLAG_CHIP_MASK) {
2206 case URE_FLAG_8152:
2207 ure_rtl8152_init(sc);
2208 break;
2209 case URE_FLAG_8153B:
2210 case URE_FLAG_8156:
2211 case URE_FLAG_8156B:
2212 if (ure_rtl8153b_init(sc) != 0)
2213 return;
2214 break;
2215 case URE_FLAG_8157:
2216 if (ure_rtl8157_init(sc) != 0)
2217 return;
2218 break;
2219 default:
2220 if (ure_rtl8153_init(sc) != 0)
2221 return;
2222 break;
2223 }
2224
2225 if (sc->ure_chip & URE_CHIP_VER_4C00)
2226 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr,
2227 sizeof(eaddr));
2228 else
2229 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr,
2230 sizeof(eaddr));
2231
2232 printf(", address %s\n", ether_sprintf(eaddr));
2233
2234 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN);
2235
2236 ifp = &sc->ure_ac.ac_if;
2237 ifp->if_softc = sc;
2238 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ);
2239 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2240 ifp->if_ioctl = ure_ioctl;
2241 ifp->if_start = ure_start;
2242 ifp->if_watchdog = ure_watchdog;
2243
2244 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 |
2245 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
2246
2247#if NVLAN > 0
2248 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
2249#endif
2250
2251 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B | URE_FLAG_8157)) {
2252 ifmedia_init(&sc->ure_ifmedia, IFM_IMASK, ure_ifmedia_upd,
2253 ure_ifmedia_sts);
2254 ure_add_media_types(sc);
2255 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2256 ifmedia_set(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO);
2257 sc->ure_ifmedia.ifm_media = sc->ure_ifmedia.ifm_cur->ifm_media;
2258 } else {
2259 rw_init(&sc->ure_mii_lock, "uremii");
2260
2261 sc->ure_mii.mii_ifp = ifp;
2262 sc->ure_mii.mii_readreg = ure_miibus_readreg;
2263 sc->ure_mii.mii_writereg = ure_miibus_writereg;
2264 sc->ure_mii.mii_statchg = ure_miibus_statchg;
2265 sc->ure_mii.mii_flags = MIIF_AUTOTSLEEP;
2266
2267 ifmedia_init(&sc->ure_mii.mii_media, 0, ure_ifmedia_upd,
2268 ure_ifmedia_sts);
2269 if (!(sc->ure_flags & URE_FLAG_8152))
2270 mii_flags |= MIIF_DOPAUSE;
2271 mii_attach(self, &sc->ure_mii, 0xffffffff, sc->ure_phyno,
2272 MII_OFFSET_ANY, mii_flags);
2273 if (LIST_FIRST(&sc->ure_mii.mii_phys) == NULL) {
2274 ifmedia_add(&sc->ure_mii.mii_media,
2275 IFM_ETHER | IFM_NONE, 0, NULL);
2276 ifmedia_set(&sc->ure_mii.mii_media,
2277 IFM_ETHER | IFM_NONE);
2278 } else
2279 ifmedia_set(&sc->ure_mii.mii_media,
2280 IFM_ETHER | IFM_AUTO);
2281 }
2282
2283 if_attach(ifp);
2284 ether_ifattach(ifp);
2285
2286 timeout_set(&sc->ure_stat_ch, ure_tick, sc);
2287
2288 splx(s);
2289}
2290
2291int
2292ure_detach(struct device *self, int flags)
2293{
2294 struct ure_softc *sc = (struct ure_softc *)self;
2295 struct ifnet *ifp = &sc->ure_ac.ac_if;
2296 int s;
2297
2298 if (timeout_initialized(&sc->ure_stat_ch))
2299 timeout_del(&sc->ure_stat_ch);
2300
2301 if (sc->ure_ep[URE_ENDPT_TX] != NULL)
2302 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]);
2303 if (sc->ure_ep[URE_ENDPT_RX] != NULL)
2304 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]);
2305
2306 usb_rem_task(sc->ure_udev, &sc->ure_tick_task);
2307
2308 s = splusb();
2309
2310 if (--sc->ure_refcnt >= 0) {
2311 usb_detach_wait(&sc->ure_dev);
2312 }
2313
2314 if (ifp->if_flags & IFF_RUNNING)
2315 ure_stop(sc);
2316
2317 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY);
2318 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY);
2319 if (ifp->if_softc != NULL) {
2320 ether_ifdetach(ifp);
2321 if_detach(ifp);
2322 }
2323
2324 splx(s);
2325
2326 return 0;
2327}
2328
2329void
2330ure_tick_task(void *xsc)
2331{
2332 struct ure_softc *sc = xsc;
2333 struct mii_data *mii;
2334 int s;
2335
2336 if (sc == NULL)
2337 return;
2338
2339 if (usbd_is_dying(sc->ure_udev))
2340 return;
2341 mii = &sc->ure_mii;
2342
2343 s = splnet();
2344 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B | URE_FLAG_8157))
2345 ure_link_state(sc);
2346 else {
2347 mii_tick(mii);
2348 if ((sc->ure_flags & URE_FLAG_LINK) == 0)
2349 ure_miibus_statchg(&sc->ure_dev);
2350 }
2351 timeout_add_sec(&sc->ure_stat_ch, 1);
2352 splx(s);
2353}
2354
2355void
2356ure_lock_mii(struct ure_softc *sc)
2357{
2358 sc->ure_refcnt++;
2359 rw_enter_write(&sc->ure_mii_lock);
2360}
2361
2362void
2363ure_unlock_mii(struct ure_softc *sc)
2364{
2365 rw_exit_write(&sc->ure_mii_lock);
2366 if (--sc->ure_refcnt < 0)
2367 usb_detach_wakeup(&sc->ure_dev);
2368}
2369
2370void
2371ure_rxcsum(struct ure_rxpkt *rxhdr, struct mbuf *m)
2372{
2373 uint32_t cflags, rxvlan;
2374
2375 cflags = letoh32(rxhdr->ure_csum);
2376 rxvlan = letoh32(rxhdr->ure_vlan);
2377
2378 /* Check IP header checksum. */
2379 if ((rxvlan & URE_RXPKT_IPV4) && !(cflags & URE_RXPKT_IPSUMBAD))
2380 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
2381
2382 /* Check TCP/UDP checksum. */
2383 if ((rxvlan & (URE_RXPKT_IPV4 | URE_RXPKT_IPV6)) &&
2384 (((rxvlan & URE_RXPKT_TCP) && !(cflags & URE_RXPKT_TCPSUMBAD)) ||
2385 ((rxvlan & URE_RXPKT_UDP) && !(cflags & URE_RXPKT_UDPSUMBAD))))
2386 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
2387#if NVLAN > 0
2388 if (rxvlan & URE_RXPKT_VLAN_TAG) {
2389 m->m_pkthdr.ether_vtag = swap16(rxvlan & URE_RXPKT_VLAN_DATA);
2390 m->m_flags |= M_VLANTAG;
2391 }
2392#endif
2393}
2394
2395void
2396ure_rxcsum_v2(struct ure_rxpkt_v2 *rxhdr2, struct mbuf *m)
2397{
2398 uint32_t cflags, rxvlan, vtag;
2399
2400 cflags = letoh32(rxhdr2->ure_csum);
2401 rxvlan = letoh32(rxhdr2->ure_vlan);
2402 vtag = letoh32(rxhdr2->ure_pktlen);
2403
2404 /* Check IP header checksum. */
2405 if ((cflags & (URE_RXPKT_V2_IPV4 | URE_RXPKT_V2_IPSUMBAD)) !=
2406 (URE_RXPKT_V2_IPV4 | URE_RXPKT_V2_IPSUMBAD))
2407 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
2408
2409 /* Check TCP/UDP checksum. */
2410 if ((cflags & (URE_RXPKT_V2_IPV4 | URE_RXPKT_V2_IPV6)) &&
2411 (((cflags & (URE_RXPKT_V2_TCP | URE_RXPKT_V2_TCPSUMBAD)) ==
2412 URE_RXPKT_V2_TCP) ||
2413 ((cflags & (URE_RXPKT_V2_UDP | URE_RXPKT_V2_UDPSUMBAD)) ==
2414 URE_RXPKT_V2_UDP)))
2415 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
2416#if NVLAN > 0
2417 if (vtag & URE_RXPKT_V2_VLAN_TAG) {
2418 m->m_pkthdr.ether_vtag =
2419 swap16((rxvlan >> 16) & URE_RXPKT_VLAN_DATA);
2420 m->m_flags |= M_VLANTAG;
2421 }
2422#endif
2423}
2424
2425void
2426ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
2427{
2428 struct ure_chain *c = (struct ure_chain *)priv;
2429 struct ure_softc *sc = c->uc_sc;
2430 struct ifnet *ifp = &sc->ure_ac.ac_if;
2431 uint32_t total_len;
2432
2433 if (usbd_is_dying(sc->ure_udev))
2434 return;
2435
2436 if (!(ifp->if_flags & IFF_RUNNING))
2437 return;
2438
2439 if (status != USBD_NORMAL_COMPLETION) {
2440 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
2441 return;
2442 if (usbd_ratecheck(&sc->ure_rx_notice)) {
2443 printf("%s: usb errors on rx: %s\n",
2444 sc->ure_dev.dv_xname, usbd_errstr(status));
2445 }
2446 if (status == USBD_STALLED)
2447 usbd_clear_endpoint_stall_async(
2448 sc->ure_ep[URE_ENDPT_RX]);
2449 goto done;
2450 }
2451
2452 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL);
2453 DPRINTFN(3, ("received %d bytes\n", total_len));
2454 ure_decap(sc, c, total_len);
2455
2456done:
2457 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX], c, c->uc_buf,
2458 sc->ure_rxbufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY,
2459 USBD_NO_TIMEOUT, ure_rxeof);
2460 usbd_transfer(xfer);
2461}
2462
2463void
2464ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
2465{
2466 struct ure_softc *sc;
2467 struct ure_chain *c;
2468 struct ifnet *ifp;
2469 int s;
2470
2471 c = priv;
2472 sc = c->uc_sc;
2473 ifp = &sc->ure_ac.ac_if;
2474
2475 if (usbd_is_dying(sc->ure_udev))
2476 return;
2477
2478 if (status != USBD_NORMAL_COMPLETION)
2479 DPRINTF(("%s: %s uc_idx=%u : %s\n", sc->ure_dev.dv_xname,
2480 __func__, c->uc_idx, usbd_errstr(status)));
2481
2482 s = splnet();
2483
2484 c->uc_cnt = 0;
2485 c->uc_buflen = 0;
2486
2487 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, c, uc_list);
2488
2489 if (status != USBD_NORMAL_COMPLETION) {
2490 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
2491 splx(s);
2492 return;
2493 }
2494
2495 ifp->if_oerrors++;
2496 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname,
2497 usbd_errstr(status));
2498
2499 if (status == USBD_STALLED)
2500 usbd_clear_endpoint_stall_async(
2501 sc->ure_ep[URE_ENDPT_TX]);
2502 splx(s);
2503 return;
2504 }
2505
2506 ifp->if_timer = 0;
2507 if (ifq_is_oactive(&ifp->if_snd))
2508 ifq_restart(&ifp->if_snd);
2509 splx(s);
2510}
2511
2512void
2513ure_decap(struct ure_softc *sc, struct ure_chain *c, uint32_t len)
2514{
2515 struct ifnet *ifp = &sc->ure_ac.ac_if;
2516 u_char *buf = c->uc_buf;
2517 uint32_t hdrsize;
2518 struct mbuf_list ml = MBUF_LIST_INITIALIZER();
2519 struct mbuf *m;
2520 int pktlen = 0, align, s;
2521 struct ure_rxpkt rxhdr;
2522 struct ure_rxpkt_v2 rxhdr2;
2523
2524 align = (sc->ure_flags & URE_FLAG_8157) ?
2525 URE_8157_BUF_ALIGN : URE_RX_BUF_ALIGN;
2526 hdrsize = (sc->ure_flags & URE_FLAG_8157) ?
2527 sizeof(rxhdr2) : sizeof(rxhdr);
2528
2529 do {
2530 if (len < hdrsize) {
2531 DPRINTF(("too few bytes left for a packet header\n"));
2532 ifp->if_ierrors++;
2533 break;
2534 }
2535
2536 buf += roundup(pktlen, align);
2537
2538 if (sc->ure_flags & URE_FLAG_8157) {
2539 memcpy(&rxhdr2, buf, hdrsize);
2540 pktlen =
2541 letoh32(rxhdr2.ure_pktlen) & URE_RXPKT_V2_LEN_MASK;
2542 pktlen >>= 17;
2543 } else {
2544 memcpy(&rxhdr, buf, hdrsize);
2545 pktlen = letoh32(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK;
2546 }
2547
2548 len -= hdrsize;
2549 DPRINTFN(4, ("next packet is %d bytes\n", pktlen));
2550 if (pktlen > len) {
2551 DPRINTF(("not enough bytes left for next packet\n"));
2552 ifp->if_ierrors++;
2553 break;
2554 }
2555
2556 len -= roundup(pktlen, align);
2557 buf += hdrsize;
2558
2559 m = m_devget(buf, pktlen - ETHER_CRC_LEN, ETHER_ALIGN);
2560 if (m == NULL) {
2561 DPRINTF(("unable to allocate mbuf for next packet\n"));
2562 ifp->if_ierrors++;
2563 break;
2564 }
2565
2566 if (sc->ure_flags & URE_FLAG_8157)
2567 ure_rxcsum_v2(&rxhdr2, m);
2568 else
2569 ure_rxcsum(&rxhdr, m);
2570
2571 ml_enqueue(&ml, m);
2572 } while (len > 0);
2573
2574 s = splnet();
2575 if_input(ifp, &ml);
2576 splx(s);
2577 memset(c->uc_buf, 0, sc->ure_rxbufsz);
2578}
2579
2580int
2581ure_encap_txpkt(struct ure_softc *sc, struct mbuf *m, char *buf,
2582 uint32_t maxlen)
2583{
2584 struct ure_txpkt txhdr;
2585 struct ure_txpkt_v2 txhdr2;
2586 uint32_t len, cflags = 0;
2587
2588 len = (sc->ure_flags & URE_FLAG_8157) ? sizeof(txhdr2) : sizeof(txhdr);
2589 if (len + m->m_pkthdr.len > maxlen)
2590 return (-1);
2591
2592 if ((m->m_pkthdr.csum_flags &
2593 (M_IPV4_CSUM_OUT | M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) != 0) {
2594 cflags |= URE_TXPKT_IPV4;
2595 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT)
2596 cflags |= URE_TXPKT_TCP;
2597 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT)
2598 cflags |= URE_TXPKT_UDP;
2599 }
2600
2601#if NVLAN > 0
2602 if (m->m_flags & M_VLANTAG)
2603 cflags |= URE_TXPKT_VLAN_TAG | swap16(m->m_pkthdr.ether_vtag);
2604#endif
2605
2606 if (sc->ure_flags & URE_FLAG_8157) {
2607 txhdr2.ure_cmdstat = htole32(URE_TXPKT_TX_FS | URE_TXPKT_TX_LS);
2608 txhdr2.ure_vlan = htole32(cflags);
2609 txhdr2.ure_pktlen = htole32(m->m_pkthdr.len << 4);
2610 txhdr2.ure_signature = htole32(URE_TXPKT_SIGNATURE);
2611 memcpy(buf, &txhdr2, len);
2612 } else {
2613 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS |
2614 URE_TXPKT_TX_LS);
2615 txhdr.ure_vlan = htole32(cflags);
2616 memcpy(buf, &txhdr, len);
2617 }
2618
2619 m_copydata(m, 0, m->m_pkthdr.len, buf + len);
2620 len += m->m_pkthdr.len;
2621
2622 return (len);
2623}
2624
2625int
2626ure_encap_xfer(struct ifnet *ifp, struct ure_softc *sc, struct ure_chain *c)
2627{
2628 usbd_status err;
2629
2630 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX], c, c->uc_buf,
2631 c->uc_buflen, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 10000,
2632 ure_txeof);
2633
2634 err = usbd_transfer(c->uc_xfer);
2635 if (err != USBD_IN_PROGRESS) {
2636 c->uc_cnt = 0;
2637 c->uc_buflen = 0;
2638 ure_stop(sc);
2639 return (EIO);
2640 }
2641
2642 return (0);
2643}