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1/* $OpenBSD: plgpio.c,v 1.3 2021/10/24 17:52:26 mpi Exp $ */
2/*
3 * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <sys/param.h>
19#include <sys/systm.h>
20#include <sys/device.h>
21
22#include <machine/intr.h>
23#include <machine/bus.h>
24#include <machine/fdt.h>
25
26#include <dev/ofw/openfirm.h>
27#include <dev/ofw/ofw_gpio.h>
28#include <dev/ofw/fdt.h>
29
30/* Registers. */
31#define GPIODATA(pin) ((1 << pin) << 2)
32#define GPIODIR 0x400
33
34#define HREAD1(sc, reg) \
35 (bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)))
36#define HWRITE1(sc, reg, val) \
37 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
38#define HSET1(sc, reg, bits) \
39 HWRITE1((sc), (reg), HREAD1((sc), (reg)) | (bits))
40#define HCLR1(sc, reg, bits) \
41 HWRITE1((sc), (reg), HREAD1((sc), (reg)) & ~(bits))
42
43struct plgpio_softc {
44 struct device sc_dev;
45 bus_space_tag_t sc_iot;
46 bus_space_handle_t sc_ioh;
47
48 struct gpio_controller sc_gc;
49};
50
51int plgpio_match(struct device *, void *, void *);
52void plgpio_attach(struct device *, struct device *, void *);
53
54const struct cfattach plgpio_ca = {
55 sizeof (struct plgpio_softc), plgpio_match, plgpio_attach
56};
57
58struct cfdriver plgpio_cd = {
59 NULL, "plgpio", DV_DULL
60};
61
62void plgpio_config_pin(void *, uint32_t *, int);
63int plgpio_get_pin(void *, uint32_t *);
64void plgpio_set_pin(void *, uint32_t *, int);
65
66int
67plgpio_match(struct device *parent, void *match, void *aux)
68{
69 struct fdt_attach_args *faa = aux;
70
71 return OF_is_compatible(faa->fa_node, "arm,pl061");
72}
73
74void
75plgpio_attach(struct device *parent, struct device *self, void *aux)
76{
77 struct plgpio_softc *sc = (struct plgpio_softc *)self;
78 struct fdt_attach_args *faa = aux;
79
80 if (faa->fa_nreg < 1) {
81 printf(": no registers\n");
82 return;
83 }
84
85 sc->sc_iot = faa->fa_iot;
86
87 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
88 faa->fa_reg[0].size, 0, &sc->sc_ioh)) {
89 printf(": can't map registers\n");
90 return;
91 }
92
93 sc->sc_gc.gc_node = faa->fa_node;
94 sc->sc_gc.gc_cookie = sc;
95 sc->sc_gc.gc_config_pin = plgpio_config_pin;
96 sc->sc_gc.gc_get_pin = plgpio_get_pin;
97 sc->sc_gc.gc_set_pin = plgpio_set_pin;
98 gpio_controller_register(&sc->sc_gc);
99
100 printf("\n");
101}
102
103void
104plgpio_config_pin(void *cookie, uint32_t *cells, int config)
105{
106 struct plgpio_softc *sc = cookie;
107 uint32_t pin = cells[0];
108
109 if (pin >= 8)
110 return;
111
112 if (config & GPIO_CONFIG_OUTPUT)
113 HSET1(sc, GPIODIR, (1 << pin));
114 else
115 HCLR1(sc, GPIODIR, (1 << pin));
116}
117
118int
119plgpio_get_pin(void *cookie, uint32_t *cells)
120{
121 struct plgpio_softc *sc = cookie;
122 uint32_t pin = cells[0];
123 uint32_t flags = cells[1];
124 uint32_t reg;
125 int val;
126
127 if (pin >= 8)
128 return 0;
129
130 reg = HREAD1(sc, GPIODATA(pin));
131 val = !!reg;
132 if (flags & GPIO_ACTIVE_LOW)
133 val = !val;
134 return val;
135}
136
137void
138plgpio_set_pin(void *cookie, uint32_t *cells, int val)
139{
140 struct plgpio_softc *sc = cookie;
141 uint32_t pin = cells[0];
142 uint32_t flags = cells[1];
143
144 if (pin >= 8)
145 return;
146
147 if (flags & GPIO_ACTIVE_LOW)
148 val = !val;
149 if (val)
150 HWRITE1(sc, GPIODATA(pin), (1 << pin));
151 else
152 HWRITE1(sc, GPIODATA(pin), 0);
153}