jcs.org
Control intel backlight on FreeBSD (and OpenBSD)
openbsd
1/*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#ifndef INTEL_GPU_TOOLS_H
29#define INTEL_GPU_TOOLS_H
30
31#include <stdint.h>
32#include <sys/types.h>
33#include <pciaccess.h>
34
35#include "intel_chipset.h"
36#include "intel_reg.h"
37
38#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
39
40extern void *mmio;
41void intel_get_mmio(struct pci_device *pci_dev);
42
43/* New style register access API */
44int intel_register_access_init(struct pci_device *pci_dev, int safe);
45void intel_register_access_fini(void);
46uint32_t intel_register_read(uint32_t reg);
47void intel_register_write(uint32_t reg, uint32_t val);
48int intel_register_access_needs_fakewake(void);
49
50/* Following functions are relevant only for SoCs like Valleyview */
51uint32_t intel_dpio_reg_read(uint32_t reg);
52void intel_dpio_reg_write(uint32_t reg, uint32_t val);
53
54int intel_punit_read(uint8_t addr, uint32_t *val);
55int intel_punit_write(uint8_t addr, uint32_t val);
56int intel_nc_read(uint8_t addr, uint32_t *val);
57int intel_nc_write(uint8_t addr, uint32_t val);
58
59#define INTEL_RANGE_RSVD (0<<0) /* Shouldn't be read or written */
60#define INTEL_RANGE_READ (1<<0)
61#define INTEL_RANGE_WRITE (1<<1)
62#define INTEL_RANGE_RW (INTEL_RANGE_READ | INTEL_RANGE_WRITE)
63#define INTEL_RANGE_END (1<<31)
64
65struct intel_register_range {
66 uint32_t base;
67 uint32_t size;
68 uint32_t flags;
69};
70
71struct intel_register_map {
72 struct intel_register_range *map;
73 uint32_t top;
74 uint32_t alignment_mask;
75};
76struct intel_register_map intel_get_register_map(uint32_t devid);
77struct intel_register_range *intel_get_register_range(struct intel_register_map map, uint32_t offset, int mode);
78
79
80static inline uint32_t
81INREG(uint32_t reg)
82{
83 return *(volatile uint32_t *)((volatile char *)mmio + reg);
84}
85
86static inline void
87OUTREG(uint32_t reg, uint32_t val)
88{
89 *(volatile uint32_t *)((volatile char *)mmio + reg) = val;
90}
91
92struct pci_device *intel_get_pci_device(void);
93
94uint32_t intel_get_drm_devid(int fd);
95int intel_gen(uint32_t devid);
96uint64_t intel_get_total_ram_mb(void);
97uint64_t intel_get_total_swap_mb(void);
98
99void intel_map_file(char *);
100
101enum pch_type {
102 PCH_NONE,
103 PCH_IBX,
104 PCH_CPT,
105 PCH_LPT,
106};
107
108extern enum pch_type pch;
109void intel_check_pch(void);
110
111#define HAS_IBX (pch == PCH_IBX)
112#define HAS_CPT (pch == PCH_CPT)
113#define HAS_LPT (pch == PCH_LPT)
114
115#endif /* INTEL_GPU_TOOLS_H */