huwcampbell.com
Reactos
1
2
3#pragma once
4
5#if defined(__cplusplus)
6extern "C" {
7#endif
8
9typedef enum _tag_ARMINTR_SHIFT_T
10{
11 _ARM_LSR = 0,
12 _ARM_LSL = 1,
13 _ARM_ASR = 2,
14 _ARM_ROR = 3
15} _ARMINTR_SHIFT_T;
16
17typedef enum _tag_ARMINTR_CPS_OP
18{
19 _ARM_CPS_ENABLE_INTERRUPTS = 1,
20 _ARM_CPS_DISABLE_INTERRUPTS = 2,
21 _ARM_CPS_CHANGE_MODE = 4
22} _ARMINTR_CPS_OP;
23
24typedef enum _tag_ARMINTR_CPS_FLAG
25{
26 _ARM_CPS_INTERRUPT_FLAG_F = 1,
27 _ARM_CPS_INTERRUPT_FLAG_I = 2,
28 _ARM_CPS_INTERRUPT_FLAG_A = 4
29} _ARMINTR_CPS_FLAG;
30
31typedef enum _tag_ARMINTR_BARRIER_TYPE
32{
33 _ARM_BARRIER_SY = 0xF,
34 _ARM_BARRIER_ST = 0xE,
35 _ARM_BARRIER_ISH = 0xB,
36 _ARM_BARRIER_ISHST = 0xA,
37 _ARM_BARRIER_NSH = 0x7,
38 _ARM_BARRIER_NSHST = 0x6,
39 _ARM_BARRIER_OSH = 0x3,
40 _ARM_BARRIER_OSHST = 0x2
41} _ARMINTR_BARRIER_TYPE;
42
43typedef enum _tag_ARMINTR_BANKED_REG
44{
45 _ARM_BANKED_R8_USR = 0x0,
46 _ARM_BANKED_R9_USR = 0x1,
47 _ARM_BANKED_R10_USR = 0x2,
48 _ARM_BANKED_R11_USR = 0x3,
49 _ARM_BANKED_R12_USR = 0x4,
50 _ARM_BANKED_R13_USR = 0x5,
51 _ARM_BANKED_SP_USR = 0x5,
52 _ARM_BANKED_R14_USR = 0x6,
53 _ARM_BANKED_LR_USR = 0x6,
54 _ARM_BANKED_R8_FIQ = 0x8,
55 _ARM_BANKED_R9_FIQ = 0x9,
56 _ARM_BANKED_R10_FIQ = 0xA,
57 _ARM_BANKED_R11_FIQ = 0xB,
58 _ARM_BANKED_R12_FIQ = 0xC,
59 _ARM_BANKED_R13_FIQ = 0xD,
60 _ARM_BANKED_SP_FIQ = 0xD,
61 _ARM_BANKED_R14_FIQ = 0xE,
62 _ARM_BANKED_LR_FIQ = 0xE,
63 _ARM_BANKED_R14_IRQ = 0x10,
64 _ARM_BANKED_LR_IRQ = 0x10,
65 _ARM_BANKED_R13_IRQ = 0x11,
66 _ARM_BANKED_SP_IRQ = 0x11,
67 _ARM_BANKED_R14_SVC = 0x12,
68 _ARM_BANKED_LR_SVC = 0x12,
69 _ARM_BANKED_R13_SVC = 0x13,
70 _ARM_BANKED_SP_SVC = 0x13,
71 _ARM_BANKED_R14_ABT = 0x14,
72 _ARM_BANKED_LR_ABT = 0x14,
73 _ARM_BANKED_R13_ABT = 0x15,
74 _ARM_BANKED_SP_ABT = 0x15,
75 _ARM_BANKED_R14_UND = 0x16,
76 _ARM_BANKED_LR_UND = 0x16,
77 _ARM_BANKED_R13_UND = 0x17,
78 _ARM_BANKED_SP_UND = 0x17,
79 _ARM_BANKED_R14_MON = 0x1C,
80 _ARM_BANKED_LR_MON = 0x1C,
81 _ARM_BANKED_R13_MON = 0x1D,
82 _ARM_BANKED_SP_MON = 0x1D,
83 _ARM_BANKED_ELR_HYP = 0x1E,
84 _ARM_BANKED_R13_HYP = 0x1F,
85 _ARM_BANKED_SP_HYP = 0x1F,
86 _ARM_BANKED_SPSR_FIQ = 0x2E,
87 _ARM_BANKED_SPSR_IRQ = 0x30,
88 _ARM_BANKED_SPSR_SVC = 0x32,
89 _ARM_BANKED_SPSR_ABT = 0x34,
90 _ARM_BANKED_SPSR_UND = 0x36,
91 _ARM_BANKED_SPSR_MON = 0x3C,
92 _ARM_BANKED_SPSR_HYP = 0x3E
93} _ARMINTR_BANKED_REG;
94
95void __dmb(unsigned int Type);
96void __dsb(unsigned int Type);
97void __isb(unsigned int Type);
98
99#pragma intrinsic(__dmb)
100#pragma intrinsic(__dsb)
101#pragma intrinsic(__isb)
102
103
104#if defined(__cplusplus)
105} // extern "C"
106#endif