huwcampbell.com
Reactos
1/*
2 * PROJECT: ReactOS Hardware Abstraction Layer
3 * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4 * PURPOSE: PC/AT hardware header file
5 * COPYRIGHT: ...
6 */
7
8#pragma once
9
10/* CMOS Registers and Ports */
11#define CMOS_CONTROL_PORT (PUCHAR)0x70
12#define CMOS_DATA_PORT (PUCHAR)0x71
13#define RTC_REGISTER_A 0x0A
14#define RTC_REG_A_UIP 0x80
15#define RTC_REGISTER_B 0x0B
16#define RTC_REG_B_PI 0x40
17#define RTC_REGISTER_C 0x0C
18#define RTC_REG_C_IRQ 0x80
19#define RTC_REGISTER_D 0x0D
20#define RTC_REGISTER_CENTURY 0x32
21
22//
23// BIOS Interrupts
24//
25#define VIDEO_SERVICES 0x10
26
27//
28// Operations for INT 10h (in AH)
29//
30#define SET_VIDEO_MODE 0x00
31
32//
33// Video Modes for INT10h AH=00 (in AL)
34//
35#define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
36
37#if defined(SARCH_XBOX)
38//
39// For some unknown reason the PIT of the Xbox is fixed at 1.125000 MHz,
40// which is ~5.7% lower than on the PC.
41//
42#define PIT_FREQUENCY 1125000
43#else
44//
45// Commonly stated as being 1.19318MHz
46//
47// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
48// p. 471
49//
50// However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
51// of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
52//
53// Note that Windows uses 1.193167MHz which seems to have no basis. However, if
54// one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
55// infinite series) and divides it by three, one obtains 1.19318167.
56//
57// It may be that the original NT HAL source code introduced a typo and turned
58// 119318167 into 1193167 by ommitting the "18". This is very plausible as the
59// number is quite long.
60//
61#define PIT_FREQUENCY 1193182
62#endif
63
64//
65// These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
66//
67#define TIMER_CHANNEL0_DATA_PORT 0x40
68#define TIMER_CHANNEL1_DATA_PORT 0x41
69#define TIMER_CHANNEL2_DATA_PORT 0x42
70#define TIMER_CONTROL_PORT 0x43
71
72//
73// Mode 0 - Interrupt On Terminal Count
74// Mode 1 - Hardware Re-triggerable One-Shot
75// Mode 2 - Rate Generator
76// Mode 3 - Square Wave Generator
77// Mode 4 - Software Triggered Strobe
78// Mode 5 - Hardware Triggered Strobe
79//
80typedef enum _TIMER_OPERATING_MODES
81{
82 PitOperatingMode0,
83 PitOperatingMode1,
84 PitOperatingMode2,
85 PitOperatingMode3,
86 PitOperatingMode4,
87 PitOperatingMode5,
88 PitOperatingMode2Reserved,
89 PitOperatingMode5Reserved
90} TIMER_OPERATING_MODES;
91
92typedef enum _TIMER_ACCESS_MODES
93{
94 PitAccessModeCounterLatch,
95 PitAccessModeLow,
96 PitAccessModeHigh,
97 PitAccessModeLowHigh
98} TIMER_ACCESS_MODES;
99
100typedef enum _TIMER_CHANNELS
101{
102 PitChannel0,
103 PitChannel1,
104 PitChannel2,
105 PitReadBack
106} TIMER_CHANNELS;
107
108typedef union _TIMER_CONTROL_PORT_REGISTER
109{
110 struct
111 {
112 UCHAR BcdMode:1;
113 UCHAR OperatingMode:3;
114 UCHAR AccessMode:2;
115 UCHAR Channel:2;
116 };
117 UCHAR Bits;
118} TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
119
120//
121// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
122// P. 400
123//
124// This port is controled by the i8255 Programmable Peripheral Interface (PPI)
125//
126#define SYSTEM_CONTROL_PORT_A 0x92
127#define SYSTEM_CONTROL_PORT_B 0x61
128typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
129{
130 struct
131 {
132 UCHAR Timer2GateToSpeaker:1;
133 UCHAR SpeakerDataEnable:1;
134 UCHAR ParityCheckEnable:1;
135 UCHAR ChannelCheckEnable:1;
136 UCHAR RefreshRequest:1;
137 UCHAR Timer2Output:1;
138 UCHAR ChannelCheck:1;
139 UCHAR ParityCheck:1;
140 };
141 UCHAR Bits;
142} SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
143
144//
145// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
146// P. 396, 397
147//
148// These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
149//
150#define PIC1_CONTROL_PORT 0x20
151#define PIC1_DATA_PORT 0x21
152#define PIC2_CONTROL_PORT 0xA0
153#define PIC2_DATA_PORT 0xA1
154
155#define PIC_TIMER_IRQ 0
156#define PIC_CASCADE_IRQ 2
157#define PIC_RTC_IRQ 8
158
159//
160// Definitions for ICW/OCW Bits
161//
162typedef enum _I8259_ICW1_OPERATING_MODE
163{
164 Cascade,
165 Single
166} I8259_ICW1_OPERATING_MODE;
167
168typedef enum _I8259_ICW1_INTERRUPT_MODE
169{
170 EdgeTriggered,
171 LevelTriggered
172} I8259_ICW1_INTERRUPT_MODE;
173
174typedef enum _I8259_ICW1_INTERVAL
175{
176 Interval8,
177 Interval4
178} I8259_ICW1_INTERVAL;
179
180typedef enum _I8259_ICW4_SYSTEM_MODE
181{
182 Mcs8085Mode,
183 New8086Mode
184} I8259_ICW4_SYSTEM_MODE;
185
186typedef enum _I8259_ICW4_EOI_MODE
187{
188 NormalEoi,
189 AutomaticEoi
190} I8259_ICW4_EOI_MODE;
191
192typedef enum _I8259_ICW4_BUFFERED_MODE
193{
194 NonBuffered,
195 NonBuffered2,
196 BufferedSlave,
197 BufferedMaster
198} I8259_ICW4_BUFFERED_MODE;
199
200typedef enum _I8259_READ_REQUEST
201{
202 InvalidRequest,
203 InvalidRequest2,
204 ReadIdr,
205 ReadIsr
206} I8259_READ_REQUEST;
207
208typedef enum _I8259_EOI_MODE
209{
210 RotateAutoEoiClear,
211 NonSpecificEoi,
212 InvalidEoiMode,
213 SpecificEoi,
214 RotateAutoEoiSet,
215 RotateNonSpecific,
216 SetPriority,
217 RotateSpecific
218} I8259_EOI_MODE;
219
220//
221// Definitions for ICW Registers
222//
223typedef union _I8259_ICW1
224{
225 struct
226 {
227 UCHAR NeedIcw4:1;
228 UCHAR OperatingMode:1;
229 UCHAR Interval:1;
230 UCHAR InterruptMode:1;
231 UCHAR Init:1;
232 UCHAR InterruptVectorAddress:3;
233 };
234 UCHAR Bits;
235} I8259_ICW1, *PI8259_ICW1;
236
237typedef union _I8259_ICW2
238{
239 struct
240 {
241 UCHAR Sbz:3;
242 UCHAR InterruptVector:5;
243 };
244 UCHAR Bits;
245} I8259_ICW2, *PI8259_ICW2;
246
247typedef union _I8259_ICW3
248{
249 union
250 {
251 struct
252 {
253 UCHAR SlaveIrq0:1;
254 UCHAR SlaveIrq1:1;
255 UCHAR SlaveIrq2:1;
256 UCHAR SlaveIrq3:1;
257 UCHAR SlaveIrq4:1;
258 UCHAR SlaveIrq5:1;
259 UCHAR SlaveIrq6:1;
260 UCHAR SlaveIrq7:1;
261 };
262 struct
263 {
264 UCHAR SlaveId:3;
265 UCHAR Reserved:5;
266 };
267 };
268 UCHAR Bits;
269} I8259_ICW3, *PI8259_ICW3;
270
271typedef union _I8259_ICW4
272{
273 struct
274 {
275 UCHAR SystemMode:1;
276 UCHAR EoiMode:1;
277 UCHAR BufferedMode:2;
278 UCHAR SpecialFullyNestedMode:1;
279 UCHAR Reserved:3;
280 };
281 UCHAR Bits;
282} I8259_ICW4, *PI8259_ICW4;
283
284typedef union _I8259_OCW2
285{
286 struct
287 {
288 UCHAR IrqNumber:3;
289 UCHAR Sbz:2;
290 UCHAR EoiMode:3;
291 };
292 UCHAR Bits;
293} I8259_OCW2, *PI8259_OCW2;
294
295typedef union _I8259_OCW3
296{
297 struct
298 {
299 UCHAR ReadRequest:2;
300 UCHAR PollCommand:1;
301 UCHAR Sbo:1;
302 UCHAR Sbz:1;
303 UCHAR SpecialMaskMode:2;
304 UCHAR Reserved:1;
305 };
306 UCHAR Bits;
307} I8259_OCW3, *PI8259_OCW3;
308
309typedef union _I8259_ISR
310{
311 struct
312 {
313 UCHAR Irq0:1;
314 UCHAR Irq1:1;
315 UCHAR Irq2:1;
316 UCHAR Irq3:1;
317 UCHAR Irq4:1;
318 UCHAR Irq5:1;
319 UCHAR Irq6:1;
320 UCHAR Irq7:1;
321 };
322 UCHAR Bits;
323} I8259_ISR, *PI8259_ISR;
324
325typedef I8259_ISR I8259_IDR, *PI8259_IDR;
326
327//
328// See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
329// P. 34, 35
330//
331// These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
332//
333#define EISA_ELCR_MASTER 0x4D0
334#define EISA_ELCR_SLAVE 0x4D1
335
336typedef union _EISA_ELCR
337{
338 struct
339 {
340 struct
341 {
342 UCHAR Irq0Level:1;
343 UCHAR Irq1Level:1;
344 UCHAR Irq2Level:1;
345 UCHAR Irq3Level:1;
346 UCHAR Irq4Level:1;
347 UCHAR Irq5Level:1;
348 UCHAR Irq6Level:1;
349 UCHAR Irq7Level:1;
350 } Master;
351 struct
352 {
353 UCHAR Irq8Level:1;
354 UCHAR Irq9Level:1;
355 UCHAR Irq10Level:1;
356 UCHAR Irq11Level:1;
357 UCHAR Irq12Level:1;
358 UCHAR Irq13Level:1;
359 UCHAR Irq14Level:1;
360 UCHAR Irq15Level:1;
361 } Slave;
362 };
363 USHORT Bits;
364} EISA_ELCR, *PEISA_ELCR;
365
366typedef union _PIC_MASK
367{
368 struct
369 {
370 UCHAR Master;
371 UCHAR Slave;
372 };
373 USHORT Both;
374} PIC_MASK, *PPIC_MASK;