picologic
logic pro compatible fpga based logic analyzer
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Add Verilog USB test and official LPF; document hardware finding

- Add picologic_top.v: minimal Verilog USB device test with explicit TRELLIS_IO buffers, pull-up control, and LED status indicators - Replace custom LPF with official icepi-zero-v1_3.lpf from upstream - Fix top.py USB clock domains and connect signal - Hardware testing confirmed: FPGA programming and LED IO work correctly, but USB D+/D- does not enumerate on either GPIO USB port despite correct pin mapping (F15/E16/G15). Likely board-level issue with USB-C connector wiring or ESD protection. 💘 Generated with Crush Assisted-by: Crush:qwen3.7-max

Author dunkirk.sh
Date Commit Parent ce0cd233
+314 -37
3 changed files
Unified Split
+314 -37
3 changed files